KR20030006425A - Field region of semiconductor device and the method of fabricating thereof - Google Patents

Field region of semiconductor device and the method of fabricating thereof Download PDF

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Publication number
KR20030006425A
KR20030006425A KR1020010042151A KR20010042151A KR20030006425A KR 20030006425 A KR20030006425 A KR 20030006425A KR 1020010042151 A KR1020010042151 A KR 1020010042151A KR 20010042151 A KR20010042151 A KR 20010042151A KR 20030006425 A KR20030006425 A KR 20030006425A
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South Korea
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trench
semiconductor substrate
insulating layer
oxide
oxide film
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KR1020010042151A
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Korean (ko)
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김경철
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주식회사 하이닉스반도체
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Priority to KR1020010042151A priority Critical patent/KR20030006425A/en
Publication of KR20030006425A publication Critical patent/KR20030006425A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Abstract

PURPOSE: An isolation region of semiconductor devices and a method for forming the same are provided to improve step coverage between an active and isolation region by using a trench isolation layer having a double structure. CONSTITUTION: A trench is formed in a semiconductor substrate(100). A thermal oxide layer(106) is formed in the trench by thermal oxidation. The first insulating layer(110) is partially filled in the trench. The second insulating layer(114) is then entirely filled into the trench. At this time, the first insulating layer(110) is made up of an oxide layer and the second insulating layer(114) is composed of a nitride layer.

Description

반도체장치의 소자격리영역 및 그의 형성방법{Field region of semiconductor device and the method of fabricating thereof}Device isolation region of semiconductor device and method of forming the same

본 발명은 반도체 장치의 소자격리영역을 형성하는 것으로 특히, 트렌치 내부에 제1절연층 제2절연층의 이중구조로 트렌치를 메워 반도체 장치를 제조하는 공정에서 절연층의 손실을 줄이고 절연층의 손실로 발생되는 단차로 인한 누설전류를 줄이기 위한 것이다.The present invention provides a device isolation region of a semiconductor device. In particular, in the process of manufacturing a semiconductor device by filling a trench with a double structure of a first insulating layer and a second insulating layer inside the trench, the loss of the insulating layer and the loss of the insulating layer This is to reduce the leakage current caused by the step difference generated.

반도체장치의 집적화가 거듭되면서 반도체장치의 상당한 면적을 점유하는 소자격리영역을 줄이기 위한 기술 개발이 활발히 진행되고 있다.As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

일반적으로 반도체장치는 LOCOS(Local Oxidation of Silicon) 방법으로 소자를 격리하였다. LOCOS 방법은 활성영역을 한정하는 산화마스크인 질화막과 반도체기판의 열적 특성이 다르기 때문에 발생하는 스트레스를 해소하기 위하여 질화막과 반도체기판 사이에 박막의 패드산화막(pad oxide)을 형성하고 산화시켜 소자격리영역으로 이용되는 필드산화막를 형성한다. 상기에서 필드산화막은 반도체기판의 수직 방향으로 성장할 뿐만 아니라 산화체(Oxidant : 02)가 패드산화막을 따라 수평 방향으로도 확산되므로 질화막의 패턴 엣지(edge)밑으로 성장되게 되는 특징을 갖는다.In general, semiconductor devices have isolated devices by LOCOS (Local Oxidation of Silicon) method. The LOCOS method is a device isolation region by forming and oxidizing a pad oxide film between the nitride film and the semiconductor substrate in order to solve the stress caused by the thermal characteristics of the nitride film and the semiconductor substrate, which are the oxide masks defining the active region. A field oxide film to be used is formed. The field oxide film is grown not only in the vertical direction of the semiconductor substrate but also in the oxidizer (Oxidant: 0 2 ) in the horizontal direction along the pad oxide film, so that the field oxide film is grown under the pattern edge of the nitride film.

이와같이 필드산화막이 활성 영역을 잠식하는 현상을 그 형상이 새의 부리 모양과 유사하여 버즈 비크(Bird's Beak)이라 한다. 이러한 버즈 비크의 길이는 필드산화막 두께의 1/2이나 된다. 그러므로, 활성 영역의 크기가 감소되는 것을 줄이기 위하여는 버즈 비크의 길이를 최소화 하여야 한다.The phenomenon in which the field oxide film encroaches on the active region is called Bird's Beak because its shape is similar to that of a bird's beak. This buzz beak is half the thickness of the field oxide film. Therefore, the length of the buzz bek should be minimized to reduce the size of the active area.

버즈 비크의 길이를 줄이기 위한 방법으로 필드산화막의 두께를 감소시키는 방식이 도입되었으나 16M DRAM급 이상에서 필드산화막의 두께를 감소시키면 배선과 반도체기판 사이의 정전 용량이 증가되어 신호전달 속도가 저하되는 문제가 발생된다. 또한, 소자의 게이트로 사용되는 배선에 의해 소자 사이의 격리영역에 형성되는 기생 트랜지스터의 문턱전압(Vt)이 저하되어 소자 사이의 격리특성이 저하되는 문제점이 있다.In order to reduce the length of the buzz beak, a method of reducing the thickness of the field oxide film was introduced. However, when the thickness of the field oxide film is reduced in the 16M DRAM class or higher, the capacitance between the wiring and the semiconductor substrate increases and the signal transmission speed decreases. Is generated. In addition, there is a problem that the threshold voltage Vt of the parasitic transistor formed in the isolation region between the elements is lowered by the wiring used as the gate of the element, thereby lowering the isolation characteristic between the elements.

따라서, 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법이 개발되었다. 버즈 비크의 길이를 감소시키면서 소자격리를 하는 방법으로는 스트레스 완충용 패드산화막의 두께를 낮추고 반도체기판과 질화막 사이에 다결정실리콘층을 개입시킨 PBLOCOS(Poly Si Buffered LOCOS), 패드산화막의 측벽을 질화막으로 보호하는 SILO(Sealed Interface LOCOS), 그리고, 반도체기판 내에 필드산화막을 형성시키는 리세스(Recessed) LOCOS 기술들이 있다.Thus, a method for device isolation while reducing the length of the buzz bee has been developed. As a method of isolation of the device while reducing the length of the buzz beak, the thickness of the pad buffer oxide film is reduced and the polysilicon buffered polysilicon layer (PBLOCOS) between the semiconductor substrate and the nitride film and the sidewall of the pad oxide film are nitrided. There are shielded interface LOCOS (SILO) to protect, and recessed LOCOS techniques to form a field oxide film in a semiconductor substrate.

그러나, 상기 기술들은 격리 영역 표면의 평탄도와 정밀한 디자인 룰(Design Rule) 등의 이유로 256M DRAM급 이상의 집적도를 갖는 차세대 소자의 소자격리기술로 적합하지 않게 되었다.However, the above techniques are not suitable for device isolation technology of next-generation devices having an integration level of 256M DRAM or more due to the flatness of the isolation region surface and the precise design rule.

따라서, 기존의 여러 소자격리기술들의 문제점을 극복할 수 있는 BOX(buried oxide)형 얕은트렌치소자격리(shallow trench isolation) 기술이 개발되었다. BOX형 소자격리기술 반도체기판에 트렌치를 형성하고 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 산화실리콘 또는 불순물이 도핑되지 않은 다결정실리콘을 매립한 구조를 갖는다. 그러므로, 버즈 비크가 발생되지 않아 활성영역의 손실이 전혀 없으며, 또한, 산화막을 매립하고 에치 백(etch back)하여 평탄한 표면을 얻을 수 있다. STI 방식은 LOCOS에 비해 필드절연층의 크기를 줄여 활성영역을 확보할수 있으나 공정단계가 LOCOS에 비해 복잡하고, 세이트 산화막 세정이나 후속공정의 습식, 건식각등으로 인한 트렌치 내부의 옥사이드의 손실이 발생한다. 이때 손실되는 옥사이드 량은 수십~수백Å정도 생기는 문제점이 있다. 그로 인해 활성영역과 소자격리영역 경계간의 단차가 발생되어 트랜지스터의 불량을 초래하는 문제점이 있다.Therefore, a BOX (buried oxide) type shallow trench isolation technology has been developed that can overcome the problems of various device isolation technologies. BOX type device isolation technology A trench is formed on a semiconductor substrate and has a structure in which silicon oxide or polycrystalline silicon which is not doped with impurities is embedded by chemical vapor deposition (hereinafter referred to as CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film. The STI method reduces the size of the field insulation layer compared to the LOCOS to secure the active area, but the process step is more complicated than the LOCOS, and oxides in the trench are lost due to the wet oxide cleaning or wet or dry etching of the subsequent process. do. At this time, the amount of oxide lost has a problem that occurs about tens to hundreds of kPa. As a result, a step is generated between the active region and the device isolation region boundary, resulting in a defect of the transistor.

따라서, 본 발명의 목적은 트렌치 내부에 채워진 절연층의 손실이 적은 반도체 장치의 소자격리영역을 제공함에 있다.Accordingly, an object of the present invention is to provide a device isolation region of a semiconductor device with little loss of an insulating layer filled in a trench.

또한, 본 발명의 다른 목적은 트렌치 내부에 채워진 절연층의 손실을 줄일 수 있는 반도체 장치의 소자격리영역을 형성하는 방법을 제공하기 위한 것이다.In addition, another object of the present invention is to provide a method for forming a device isolation region of the semiconductor device that can reduce the loss of the insulating layer filled in the trench.

상기한 목적을 달성하기 위한 본 발명에 따른 반도체 장치의 소자격리영역은 반도체 기판과 상기 반도체 기판에 형성된 트렌치와 상기 트렌치 내부를 산화하여 형성된 산화막과 상기 반도체 기판보다 낮게 상기 산화막이 형성된 트렌치에 채워진 제1 절연층과 상기 트렌치 내부의 상기 제1 절연층 위에 채워진 제2 절연층을 포함하여 이루어진다.The device isolation region of the semiconductor device according to the present invention for achieving the above object is a semiconductor substrate, a trench formed in the semiconductor substrate, an oxide film formed by oxidizing the inside of the trench and a trench filled in the oxide film formed lower than the semiconductor substrate; And a second insulating layer filled over the first insulating layer and the first insulating layer in the trench.

상기한 다른 목적을 달성하기 위한 본 발명에 따른 반도체 장치의 소자격리영역을 형성하는 방법은 반도체 기판상에 표면산화막, 패드 질화막을 형성하는 제1공정과; 상기 패드질화막을 패터닝하여 소자격리 영역을 한정하고 패드질화막, 표면산화막, 반도체 기판을 식각하여 트렌치를 형성하는 제2공정과; 산화 공정으로 상기 트렌치 내부의 반도체 기판 표면에 산화막을 형성하는 제3공정과; 상기 트렌치에 옥사이드를 채우고 어닐링 공정을 실시한 후 반도체 기판 표면을 평탄화하게 하고, 이어서 상기 반도체 기판 표면보다 낮도록 옥사이드의 제거하여 제1절연층을 형성하는 제4공정과; 상기 옥사이드가 제거된 부분을 메우도록 니트라이드를 도포한후 패드옥사이드가 드러날 때까지 CMP 공정으로 평탄화하는 제5 공정을 포함하여 이루어진다.According to another aspect of the present invention, there is provided a method of forming a device isolation region of a semiconductor device, comprising: forming a surface oxide film and a pad nitride film on a semiconductor substrate; Patterning the pad nitride film to define an isolation region, and etching the pad nitride film, the surface oxide film, and the semiconductor substrate to form a trench; A third step of forming an oxide film on a surface of the semiconductor substrate in the trench by an oxidation process; A fourth process of filling the trench with an oxide and performing an annealing process to planarize the surface of the semiconductor substrate, and then removing the oxide to be lower than the surface of the semiconductor substrate to form a first insulating layer; And a fifth process of applying nitride to fill the oxide-removed portion and then planarizing the CMP process until the pad oxide is exposed.

도1a 내지 도1e 는 본 발명에 따른 반도체 장치의 소자격리영역의 제조방법을 도시하는 공정도1A to 1E are process drawings showing a method for manufacturing a device isolation region of a semiconductor device according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

100. 반도체 기판 102. 표면산화막100. Semiconductor substrate 102. Surface oxide film

104. 패드질화막 105. 트렌치104. Pad nitride film 105. Trench

106. 산화막 108. 옥사이드층106. Oxide layer 108. Oxide layer

110. 제1절연층 112. 니트라이드층110. First insulating layer 112. Nitride layer

114. 제2절연층114. Second Insulation Layer

이하, 본 발명에 따른 실시예를 첨부된 도면에 따라 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도1a에서와 같이, 반도체 기판(100) 상에 표면산화막(102), 패드 질화막(104)을 형성한다.As shown in FIG. 1A, a surface oxide film 102 and a pad nitride film 104 are formed on the semiconductor substrate 100.

패드질화막(104)상에 포토레지스터를 도포한 후 패터닝하여 소자격리영역을 한정한다. 포토레지스터를 마스크로하여 패드질화막(104)과 표면산화막(102), 반도체 기판(100)을 순차적으로 건식식각하여 트렌치(105)를 형성한 후 포토레스지스터를 제거한다.A photoresist is applied on the pad nitride film 104 and then patterned to define the device isolation region. Using the photoresist as a mask, the pad nitride film 104, the surface oxide film 102, and the semiconductor substrate 100 are sequentially dry-etched to form the trench 105, and then the photoresist is removed.

다음으로 도1b에서와 같이, 트렌치(105) 내부의 반도체 기판(100)을 산화하여 산화막(106)을 형성한다. 산화막(106)은 트렌치(105) 형성을 위한 식각시 손상(damage)된 부분을 보완한다.Next, as shown in FIG. 1B, an oxide film 106 is formed by oxidizing the semiconductor substrate 100 inside the trench 105. The oxide layer 106 compensates for the damaged portion during etching for forming the trench 105.

산화막(106)이 형성된 트렌치(105)에 HDP(high density plasma)방식으로 옥사이드를 증착하여 옥사이드층(108)을 형성한 후 어닐링(annealing)한다. 이때, 트렌치(105) 내부의 옥사이드층(108) 표면은 패드질화막(104)보다 낮아서 접시(dish)모양의 형상(profile)이된다.An oxide is deposited on the trench 105 in which the oxide film 106 is formed by HDP (high density plasma) to form an oxide layer 108 and then annealed. At this time, the surface of the oxide layer 108 in the trench 105 is lower than the pad nitride film 104 to have a dish-shaped profile.

도1c에서와 같이, 접시 모양의 형상으로 인한 단차를 줄여주기 위해 포토공정을 진행한다. 포토레지스터를 반도체기판(100) 전면에 도포한 후 상대적으로 표면이 낮은 옥사이드층(108) 표면에만 포토레지스터를 남기고 그 외 부분에는 포토레지스터를 제거한다. 이후 노출된 면에 식각공정을 진행하여 옥사이드층(108) 표면과 패드질화막(104) 표면간 경계의 단차를 줄여주어 이후 CMP(Chemical mechanical polishing)가 원활히 이루어지도록 한다.As shown in Figure 1c, the photo process is performed to reduce the step due to the dish-like shape. After the photoresist is applied to the entire surface of the semiconductor substrate 100, the photoresist is left only on the surface of the oxide layer 108 having a relatively low surface, and the photoresist is removed at the other part. Thereafter, an etching process is performed on the exposed surface to reduce the step difference between the oxide layer 108 surface and the pad nitride film 104 surface, thereby smoothly performing chemical mechanical polishing (CMP).

포토공정으로도 어느 정도 단차를 줄여준 반도체 기판에 CMP를 진행하여 반도체 기판(100)전체의 표면을 평탄화시킨다.In the photo process, the surface of the semiconductor substrate 100 is planarized by performing CMP on the semiconductor substrate to which the step is reduced.

평탄화된 반도체 기판(100)을 건식식각하여 옥사이드층(108)의 일부를 제거하여 제1절연층(110)을 형성한다. 이때, 제1절연층(110)은 반도체 기판(100) 표면보다 400~500Å정도 낮도록 형성한다.A portion of the oxide layer 108 is removed by dry etching the planarized semiconductor substrate 100 to form the first insulating layer 110. In this case, the first insulating layer 110 is formed to be about 400 ~ 500 낮 lower than the surface of the semiconductor substrate 100.

도1d에서와 같이, 제1절연층(110)이 형성된 트렌치(105) 내부에 산화를 실시하여 옥사이드층(108)의 일부를 제거를 할 때 손상된 트렌치(105) 내벽의 손상을 보상하여 후속공정으로 형성되는 제2절연층(114)으로 인한 스트레스(stress)를 완화시킨다.As shown in FIG. 1D, when the oxide layer 108 is removed by oxidizing the inside of the trench 105 in which the first insulating layer 110 is formed, the damage of the inner wall of the damaged trench 105 is compensated for. The stress caused by the second insulating layer 114 is reduced.

그리고, 트렌치(105) 내부를 완전히 메우도록 니트라이드(nitride)를 도포하여 니트라이드층(112)을 형성한다.In addition, nitride is applied to completely fill the inside of the trench 105 to form the nitride layer 112.

도1e 에서와 같이, 니트라이드층(112)의 표면에 평탄화공정을 진행하여 표면산화막(102)이 노출되도록 하여 제1절연층(110)상에 제2절연층(114)이 형성된 소자격리영역(116)을 형성한다.As shown in FIG. 1E, a planarization process is performed on the surface of the nitride layer 112 so that the surface oxide film 102 is exposed so that the second insulating layer 114 is formed on the first insulating layer 110. 116 is formed.

STI기술로 형성된 트렌치 내부를 옥사이드 하나로만 채워 소자격리영역을 형성함으로서 이후에 진행되는 게이트 산화막 형성시 실시하는 전세정등과 같은 후속공정에서 트렌치 내부의 옥사이드가 수십 ~수백 Å 정도 제거되는 문제점을 본 발명에 따른 트렌치 내부를 옥사이드로 된 제1절연층과 니트라이드로 된 제2절연층의 2중 구조로 형성함으로 후속공정에서 옥사이드가 손실되는 것을 줄일수 있다. 또한, 옥사이드의 손실로 인한 활성영역과 소자격리영역의 경계간의 단차를 줄여준다. 단차로 인해 발생되는 정크션누설전류를 감소시킬수 있어 소자특성의 신뢰성을 확보하고 불량률을 줄일수 있다.By forming the device isolation region by filling the inside of the trench formed by STI technology with only one oxide, the oxides in the trench are removed from the trenches in the subsequent process such as pre-cleaning during the gate oxide film formation. In the trench according to the present invention, a double structure of an oxide first insulating layer and a nitride second insulating layer may reduce oxide loss in a subsequent process. In addition, the step difference between the boundary between the active region and the device isolation region due to the loss of oxide is reduced. Junction leakage current caused by the step can be reduced, which ensures the reliability of device characteristics and reduces the defective rate.

Claims (6)

반도체 기판과;A semiconductor substrate; 상기 반도체 기판에 형성된 트렌치와;Trenches formed in the semiconductor substrate; 상기 트렌치 내부를 산화하여 형성된 산화막과;An oxide film formed by oxidizing the inside of the trench; 상기 반도체 기판보다 낮게 상기 산화막이 형성된 트렌치에 채워진 제1 절연층과,A first insulating layer filled in the trench in which the oxide film is formed lower than the semiconductor substrate; 상기 트렌치를 채우며 상기 제1 절연층 위에 형성된 제2 절연층을 포함하여 이루어지는 반도체 장치의 소자격리영역.And a second insulating layer filling the trench and formed on the first insulating layer. 청구항 1에 있어서,The method according to claim 1, 상기 제1절연층은 옥사이드로 형성하고 상기 제2절연층은 니트라이드로 형성하는 것을 특징으로 하는 반도체 장치의 소자격리영역.And the first insulating layer is formed of oxide, and the second insulating layer is formed of nitride. 반도체 기판상에 표면산화막, 패드 질화막을 형성하는 제1공정과;A first step of forming a surface oxide film and a pad nitride film on the semiconductor substrate; 상기 패드질화막을 패터닝하여 소자격리 영역을 한정하고 패드질화막, 표면산화막, 반도체 기판을 식각하여 트렌치를 형성하는 제2공정과;Patterning the pad nitride film to define an isolation region, and etching the pad nitride film, the surface oxide film, and the semiconductor substrate to form a trench; 산화 공정으로 상기 트렌치 내부의 반도체 기판 표면에 산화막을 형성하는 제3공정과;A third step of forming an oxide film on a surface of the semiconductor substrate in the trench by an oxidation process; 상기 트렌치에 옥사이드를 채우고 어닐링 공정을 실시한 후 상기 반도체 기판 표면을 평탄화하게 하고, 이어서 상기 반도체 기판 표면보다 낮도록 옥사이드를 제거하여 제1절연층을 형성하는 제4공정과A fourth process of filling the trench with an oxide and performing an annealing process to planarize the surface of the semiconductor substrate, and then removing the oxide to be lower than the surface of the semiconductor substrate to form a first insulating layer; 상기 옥사이드가 제거된 부분을 메우도록 니트라이드를 도포한후 패드옥사이드가 드러날 때까지 CMP 공정으로 평탄화하여 제2절연층을 형성하는 제5 공정을 포함하여 이루어지는 반도체 장치의 소자격리영역 형성방법.And forming a second insulating layer by coating nitride to fill the oxide-removed portion and then planarizing the CMP process until the pad oxide is exposed, thereby forming a second insulating layer. 청구항 3에 있어서,The method according to claim 3, 상기 제4공정에 있어서,In the fourth step, 상기 제1절연층은 400-500Å정도의 깊이만큼 제거하는 것을 특징으로 하는 반도체 장치의 소자격리영역 형성방법.And removing the first insulating layer by a depth of about 400-500 Å. 청구항3에 있어서,The method according to claim 3, 상기 제5 공정에 있어,In the fifth step, 상기 평탄화 공정은 포토공정으로 옥사이드보다 높게 형성된 패드질화막을 식각하여 단차를 줄인후, 반도체 기판 전면에 CMP를 진행하여 반도체 기판 표면을 평탄화하는 공정을 더 포함하여 이루어지는 것이 특징인 반도체 장치의 소자격리영역 형성방법The planarization process may further include a step of reducing a step by etching a pad nitride film formed higher than oxide by a photo process, and then performing a CMP on the entire surface of the semiconductor substrate to planarize the surface of the semiconductor substrate. Formation method 청구항 3 또는 5에있어서,According to claim 3 or 5, 상기 제5공정에 있어서,In the fifth step, 상기 옥사이드를 제거한 후 트렌치 내부를 재 산화하는 공정을 더 포함하여 이루어지는 것이 특징인 반도체 장치의 소자격리영역 형성방법.And removing the oxide to reoxidize the inside of the trench.
KR1020010042151A 2001-07-12 2001-07-12 Field region of semiconductor device and the method of fabricating thereof KR20030006425A (en)

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Publication number Priority date Publication date Assignee Title
KR100660030B1 (en) * 2005-05-27 2006-12-20 삼성전자주식회사 Trench isolation structure and method of forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660030B1 (en) * 2005-05-27 2006-12-20 삼성전자주식회사 Trench isolation structure and method of forming the same

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