JPS61268038A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61268038A JPS61268038A JP11068285A JP11068285A JPS61268038A JP S61268038 A JPS61268038 A JP S61268038A JP 11068285 A JP11068285 A JP 11068285A JP 11068285 A JP11068285 A JP 11068285A JP S61268038 A JPS61268038 A JP S61268038A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- semiconductor
- semiconductor substrate
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置の製造方法に関し、特にシリコン
半導体基板上での素子分離構造の形成方法に係るもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an element isolation structure on a silicon semiconductor substrate.
半導体装置における素子間分離構造の形成方法の従来例
として1選択酸化法による場合を92図(a)ないしく
C)について説明する。A conventional method for forming an element isolation structure in a semiconductor device using a single selective oxidation method will be described with reference to FIGS. 92(a) to 92(c).
即ち、この従来例方法においては、まず、シリコン半導
体基板(1)上の全面にあって、下敷シリコン峻化膜(
2)及び選択酸化時に耐酸化性マスクとなるシリコン窒
化膜+31を順次形成し、かつ写真製版技術で形成され
たフォトレジストマスク(41を耐エツチング性マスク
に用い、このシリコン窒化III t3+の素子分離形
成領域を選択的にエツチング除去し、かつこの素子分離
領域に、例えば、シリコン半導体基板(1)の導電形が
p形であれば、フォトレジストマスク(4)をイオン注
入のマスクとして、シリコン半導体基板(1)中に、ボ
ロンのようなp形の不純物をイオン注入し、後にチャネ
ルカット領域となる不純物注入層+51を形成する〔第
2図(a)〕。That is, in this conventional method, first, an underlying silicon thickening film (
2) A silicon nitride film +31, which serves as an oxidation-resistant mask during selective oxidation, is sequentially formed, and a photoresist mask (41 is used as an etching-resistant mask) formed by photolithography to separate the elements of this silicon nitride III t3+. For example, if the conductivity type of the silicon semiconductor substrate (1) is p-type, the silicon semiconductor is etched by selectively etching away the formation region and using the photoresist mask (4) as a mask for ion implantation. A p-type impurity such as boron is ion-implanted into the substrate (1) to form an impurity implantation layer +51 which will later become a channel cut region [FIG. 2(a)].
次に、前記シリコン窒化膜(3)をマスクにして選択的
に酸化処理することによって、前記素子分離領域部分に
素子分離のためのシリコン酸化膜(61ft形成し〔第
2図(bl 〕、さらに、これらの素子形成領域上のシ
リコン窒化膜131及び下敷シリコ/酸化膜(2)を除
去して、同部分の基板面を露出させ〔第2図(C)〕、
このようにして素素子間分離層を形成するようにしてい
るのである。Next, by selectively oxidizing using the silicon nitride film (3) as a mask, a silicon oxide film (61 ft) for element isolation is formed in the element isolation region [Fig. 2 (bl)]. , the silicon nitride film 131 and the underlying silicon/oxide film (2) on these element forming regions are removed to expose the substrate surface in the same portions [FIG. 2(C)],
In this way, the element isolation layer is formed.
しかしながら前記従来例方法による素子間分離構造にお
いては、第2図(C)からも明らかなように、選択酔化
処理に際し、素子分離シリコン酸化膜(6)の成長に伴
い、耐酸化性マスクであるシリコン窒化膜(3)のパタ
ーンエツジから、素子分離シリコン酸化膜(6)が素子
形成領域に大きく食い込み、素子形成領域が狭くなり、
素子集積度の向上に問題があった。However, in the element isolation structure according to the conventional method, as is clear from FIG. 2(C), during selective intoxication treatment, the oxidation-resistant mask is From the pattern edge of a certain silicon nitride film (3), the element isolation silicon oxide film (6) largely digs into the element formation area, narrowing the element formation area.
There was a problem in improving the degree of device integration.
この発明は従来例方法のような欠点を改善しようとする
もので、微細かつ高性能な素子分離特性を有する素子分
離領域を形成し、素子集積度の向上を可能にする半導体
装置の製造方法を提供することを目的とするものでざる
。This invention aims to improve the drawbacks of conventional methods, and provides a semiconductor device manufacturing method that forms a fine device isolation region with high-performance device isolation characteristics and enables an improvement in device integration. It is not intended to provide.
この発明に係る半導体装置の製造方法においては、半導
体基板に形成した溝以外の基板表面に耐酸化性マスクを
形成し、溝埋め込みに用いた半導体膜を酸化し、絶縁膜
に変換することによって、容易にシリコン溝を絶縁膜で
埋め込み、これを素子間分離層とするものである。In the method for manufacturing a semiconductor device according to the present invention, an oxidation-resistant mask is formed on the substrate surface other than the groove formed in the semiconductor substrate, and the semiconductor film used for filling the groove is oxidized and converted into an insulating film. The silicon trench is easily filled with an insulating film and used as an element isolation layer.
この発明方法の場合、半導体基板の平坦部のみ耐酸化性
マスクが形成されており、溝部を含む半導体基板表面に
絶縁膜、半導体膜を形成し、この半導体膜を少なくとも
基板平坦部上の部分は全て酸化する程度に酸化し絶縁膜
とすることによって、上記溝に空隙を作らず、かつ平坦
な素子分離領域を形成することが可能である。In the method of this invention, an oxidation-resistant mask is formed only on the flat portion of the semiconductor substrate, and an insulating film and a semiconductor film are formed on the surface of the semiconductor substrate including the groove portion, and this semiconductor film is applied to at least the portion on the flat portion of the substrate. By oxidizing to such an extent that the entire structure is oxidized to form an insulating film, it is possible to form a flat element isolation region without creating a void in the trench.
以下、この発明に係る半導体装置の製造方法の実権例を
、第1図(a)ないしくf)について説明する。Hereinafter, a practical example of the method for manufacturing a semiconductor device according to the present invention will be explained with reference to FIGS. 1(a) to 1(f).
この実施例方法においてけ、まず、シリコン半導体基板
(II上に下敷シリコン酸化膜(2)及び後工程で耐駿
化性マスクとして働くシリコン窒化膜(31を順次形成
し、かつこのシリコン窒化膜13+上に写真製版技術で
形成された7オトレジストマスク(41ヲ耐エツチング
性マスクとして用い、素子分離形成領域のシリコン窒化
膜(3I、シリコン酸化膜(2)及びシリコン半導体基
板[1)のある深さまでを選択的にエツチング除去して
溝(〕)を形成する〔第1図(a)〕。In this embodiment method, first, on a silicon semiconductor substrate (II), an underlying silicon oxide film (2) and a silicon nitride film (31) which will serve as a oxidation-resistant mask in the subsequent process are sequentially formed, and this silicon nitride film 13+ A 7-photoresist mask (41) formed on the top by photolithography is used as an etching-resistant mask to form a silicon nitride film (3I) in the element isolation formation region, a silicon oxide film (2), and a silicon semiconductor substrate [1] at a certain depth. The grooves are selectively etched away to form grooves ( ) [FIG. 1(a)].
次に、フォトレジストマスク(41yk除去し必要なら
ば、形成した溝(7)の内面からシリコン半導体基板(
1)と同じ導電性を有する不純物を拡散させ不純物注入
層(51を形成する。さらに、シリコン窒化膜(31の
表面及び溝j7)の内面に絶縁膜、例えばシリコン酸化
膜(8)を形成し、さらにこのシリコン酸化膜(8)上
に半導体膜、例えば多結晶シリコン膜1914−溝(7
)が完全に埋め込まれるように形成する〔第1図(bD
。Next, the photoresist mask (41yk) is removed, and if necessary, the silicon semiconductor substrate (
An impurity implanted layer (51) is formed by diffusing an impurity having the same conductivity as in 1).Furthermore, an insulating film, for example, a silicon oxide film (8) is formed on the surface of the silicon nitride film (31 and the inner surface of the groove j7). Further, a semiconductor film, for example, a polycrystalline silicon film 1914-groove (7) is formed on this silicon oxide film (8).
) is completely embedded [Figure 1 (bD
.
さらに、最表面に形成されている多結晶シリコン膜(9
1を酸化雰囲気によって酸化しシリコン酸化膜(8)に
変換する。このとき素子形成領域上にt−1耐酸化性膜
のシリコン窒化膜+31が形成されているので、酸化処
理を行なっても素子形成領域は影響を及ぼすことなく保
たれ、一方、溝(7)に形成されている多結晶シリコン
膜(91ij深くまで酸化が進み、シリコン酸化膜(8
)に変換されることになり、シリコン窒化膜(3)が形
成されているレベルまで多結晶シリコン膜(91をシリ
コン酸化膜(8)に変換する〔第1図(C)〕。次に、
シリコン酸化膜(8)をシリコン窒化膜(3]の表面が
露出するまでエツチング除去し〔第1図釦〕、シリコン
窒化膜(3j、下敷シリコン酸化膜(2)を除去すると
、溝(7)は、シリコン酸化膜(8)及び多結晶シリコ
ン膜(91で完全に埋め込まれ素子分離領域が形成され
ることになる〔第1図(e)〕。Furthermore, a polycrystalline silicon film (9
1 is oxidized in an oxidizing atmosphere and converted into a silicon oxide film (8). At this time, since the silicon nitride film +31, which is a t-1 oxidation-resistant film, is formed on the element formation region, the element formation region is maintained without any influence even if the oxidation treatment is performed. The oxidation progresses to the depth of the polycrystalline silicon film (91ij) formed on the silicon oxide film (81ij).
), and the polycrystalline silicon film (91) is converted to a silicon oxide film (8) to the level where the silicon nitride film (3) is formed [FIG. 1(C)].Next,
After removing the silicon oxide film (8) by etching until the surface of the silicon nitride film (3) is exposed [see button in Figure 1], and removing the silicon nitride film (3j) and the underlying silicon oxide film (2), a groove (7) is formed. is completely buried with a silicon oxide film (8) and a polycrystalline silicon film (91) to form an element isolation region [FIG. 1(e)].
また、上記実施例では多結晶シリコン膜(9)の酸化を
途中で止め、溝(7)の中にシリコン酸化膜(8)で囲
まれる構造となっているが、この多結晶シリコン膜(9
1を完全にシリコン酸化膜に変換させることも可能であ
るC畜1mtf)l。Further, in the above embodiment, the oxidation of the polycrystalline silicon film (9) is stopped midway, and the trench (7) is surrounded by the silicon oxide film (8).
It is also possible to completely convert 1 to a silicon oxide film.
以上のように、この発明では半導体基板に形成した溝を
絶縁膜と半導体膜とで埋め込むので、溝を空隙なく埋め
込むことができ、平坦部に形成した耐酸化性膜によシ半
導体膜を酸化しても素子形成領域に悪い影響を与えるこ
とな(、微細な素子分離領域を形成でき、かつ、平坦な
分離が可能となる。As described above, in this invention, a trench formed in a semiconductor substrate is filled with an insulating film and a semiconductor film, so the trench can be filled without any voids, and the semiconductor film can be oxidized by the oxidation-resistant film formed on the flat part. Even if the device is separated, it does not adversely affect the device formation region (it is possible to form a fine device isolation region, and it is possible to achieve flat isolation).
第1図(al〜(f)はこの発明の一実施例の、第2図
(a)〜(c)は従来の半導体装置の製造方法における
素子分離領域形成の主要段階での状態を示す断面図であ
る。
図において、filは半導体基板、(3)は耐酸化性膜
としてのシリコン窒化膜、(6)は不純物拡散層、(7
)け溝、+81 I/f絶縁膜たとえばシリコン酸化膜
、(91は半導体膜たとえば多結晶シリコン膜である。
なお、各図中の同−符J8−け同−又は相当部分を示す
。FIGS. 1(a-1f) are cross-sectional views showing one embodiment of the present invention, and FIGS. 2(a)-(c) are cross-sectional views showing the main stages of forming an element isolation region in a conventional semiconductor device manufacturing method. In the figure, fil is a semiconductor substrate, (3) is a silicon nitride film as an oxidation-resistant film, (6) is an impurity diffusion layer, and (7) is a silicon nitride film as an oxidation-resistant film.
) trench, +81 I/f insulating film, such as a silicon oxide film, (91 is a semiconductor film, such as a polycrystalline silicon film. Note that the same reference numeral J8 in each figure indicates the same or a corresponding portion.
Claims (3)
る耐酸化性膜を形成する第1の工程、この耐酸化性膜を
エッチングマスクとして上記半導体基板に溝を形成する
第2の工程、この溝の内部を含めて上記半導体基板上の
上記耐酸化性膜の表面上に絶縁膜及び半導体膜を順次形
成する第3の工程、上記半導体膜に酸化処理を施して、
少なくとも上記半導体基板の上面平坦部上の上記半導体
膜をすべて絶縁膜に変換する第4の工程、並びに上記半
導体基板上面平坦部上の上記絶縁膜及び上記耐酸化性膜
を除去して、上記半導体基板の上面平坦部を露出させる
とともに上記溝内に素子間分離絶縁層を残す第5の工程
を備えたことを特徴とする半導体装置の製造方法。(1) A first step of forming an oxidation-resistant film having an opening in an element isolation formation region on a semiconductor substrate; a second step of forming a groove in the semiconductor substrate using this oxidation-resistant film as an etching mask; a third step of sequentially forming an insulating film and a semiconductor film on the surface of the oxidation-resistant film on the semiconductor substrate including the inside of the groove; oxidizing the semiconductor film;
a fourth step of converting at least all of the semiconductor film on the flat upper surface of the semiconductor substrate into an insulating film, and removing the insulating film and the oxidation-resistant film on the flat upper surface of the semiconductor substrate, A method of manufacturing a semiconductor device, comprising a fifth step of exposing a flat upper surface of the substrate and leaving an element isolation insulating layer in the groove.
面の少なくとも一部の半導体基板にこの半導体基板の導
電形と同じ導電形の不純物を拡散させた後に形成するこ
とを特徴とする特許請求の範囲第1項記載の半導体装置
の製造方法。(2) A patent characterized in that the insulating film and the semiconductor film in the third step are formed after diffusing impurities of the same conductivity type as that of the semiconductor substrate into at least a portion of the semiconductor substrate on the inner surface of the groove. A method for manufacturing a semiconductor device according to claim 1.
耐酸化性膜として窒化シリコン膜を、絶縁膜として酸化
シリコン膜を、半導体膜として多結晶シリコン膜を用い
ることを特徴とする特許請求の範囲第1項または第2項
記載の半導体装置の製造方法。(3) A silicon single crystal semiconductor substrate as a semiconductor substrate,
A method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that a silicon nitride film is used as the oxidation-resistant film, a silicon oxide film is used as the insulating film, and a polycrystalline silicon film is used as the semiconductor film. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11068285A JPS61268038A (en) | 1985-05-22 | 1985-05-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11068285A JPS61268038A (en) | 1985-05-22 | 1985-05-22 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61268038A true JPS61268038A (en) | 1986-11-27 |
Family
ID=14541776
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11068285A Pending JPS61268038A (en) | 1985-05-22 | 1985-05-22 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61268038A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010093053A (en) * | 2008-10-08 | 2010-04-22 | Toyota Motor Corp | Method of manufacturing semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54589A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Burying method of insulator |
JPS5968942A (en) * | 1982-10-12 | 1984-04-19 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS6018930A (en) * | 1983-07-13 | 1985-01-31 | Hitachi Ltd | Manufacture of semiconductor device |
-
1985
- 1985-05-22 JP JP11068285A patent/JPS61268038A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54589A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Burying method of insulator |
JPS5968942A (en) * | 1982-10-12 | 1984-04-19 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS6018930A (en) * | 1983-07-13 | 1985-01-31 | Hitachi Ltd | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010093053A (en) * | 2008-10-08 | 2010-04-22 | Toyota Motor Corp | Method of manufacturing semiconductor device |
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