JPH01274448A - Method for forming element isolating region - Google Patents

Abstract

PURPOSE:To alleviate crystal defects, to suppress a narrow channel effect and to achieve high density, by sequentially etching and removing a nitride film and a pad oxide film, forming an opening part, forming a groove part through the opening part, forming an inner surface oxide film in the groove, etching and removing the oxide film at the bottom surface, thereafter forming an embedded layer, growing an oxide film, and forming an element isolating region. CONSTITUTION:After a groove part 29 is formed, an inner surface oxide film 31 is formed. A bottom surface oxide film 31a of said inner surface oxide film 31 is removed. Thus, an embedded layer 33 can be grown with selected silicon. The layer 33 can be formed with high concentration impurities. Therefore, even if the thickness of an oxide film 35 that is formed by a thermal oxidation step has a small value, the breakdown strength of an element isolating region can be sufficiently secured. Alleviation in heating condition can shorten the time required for growing the thick film. The occurring frequency of crystal defects can be decreased by alleviating the treatment under the high temperature condition.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of forming an element isolation region suitable for application to the manufacture of various semiconductor devices 1.

(Conventional Area) In manufacturing various semiconductor devices, element isolation regions are widely used for functionally separating semiconductor elements from each other and fabricating a plurality of elements on a substrate. As such an element isolation region, for example, literature: rPhilips
Re5earch Reports (Philips Research Reports) J (25,1), 118-13
2, 1970), selective oxidation (Loc
alOxidation of 5ilicon:LO
GOS) method is mainly adopted.

Below, as an example of the conventional element isolation region, the above-mentioned LOG
Drawing ¥ for OS method! Refer to and explain.

FIGS. 2(A) to 2(E) are explanatory diagrams showing schematic cross-sections of a substrate for each formation step in order to explain conventional element isolation regions. Further, in order to facilitate understanding of the explanation, various constituent components arranged for each step will be comprehensively represented as a base. Roughly speaking, in the figure, 11 is made of, for example, p-type crystal silicon (Si), and (+00)
A substrate 13 is made of silicon oxide (for example, SiO□
), 15 is a nitride film made of silicon nitride (for example, Sj3N4), 17 is a field region, 19 is an opening, 21 is a channel stop region, 23 is an oxide film, and 25 is in v4 contact with the field region 17. The active region 27 indicates an element isolation region.

First, dry oxidation is performed with the surface of the substrate 11 exposed to form a bad oxide film 13 with a thickness of about 300 mm. Subsequently, LP-CVD (Low Pressure Chemical) is applied on the above-mentioned bad oxide film 13.
icalVapor Deposition: Reduced pressure CV
A nitride film 15 is deposited to a thickness of about 1,500 layers by method D) to obtain the base shown in FIG. 2(A).

Next, a resist pattern (not shown) exposing only the surface of the nitride film 15 corresponding to the field region 17 of the substrate 11 is formed. After that, using the pattern as an etching mask, for example, reactive ion etching (React etching) is performed.
The above-mentioned enriched film 15 is etched by etching (RIE) method or other anisotropic etching region.
remove.

Subsequently, for example, after removing the resist pattern, the remaining nitride film 15 is removed by etching as an etching mask, and the opening 19 is formed to expose the surface of the substrate 11 described above.
Figure 2 (B)).

Next, using at least the remaining nitride film 15 as a mask for ion implantation, impurity ions, such as boron (B), according to the design of the semiconductor device are implanted as ions (in the figure,
Indicated by a series of arrows a. ), and a channel stop region 21 (in the figure,
- to form ) (shown enclosed by a dotted chain line) (Figure 2 (C))
.

The impurity concentration implanted at this time is set to a predetermined value depending on the design of the desired semiconductor device.
x 1013 (approximately 30 (at implantation density of 1013)
Apply an ion energy of about 1×10” (eV) to
A channel stop region is formed at a concentration of am-3) to prevent channel inversion.

Next, with the substrate 11 exposed through the aforementioned opening 19, wet oxidation is performed using the remaining nitride film 15 as an oxidation mask.In this way, the substrate 11 exposed to the field region 17 is thermally oxidized. Continuing with the bad oxide film 13, an oxide film 23 is formed to a thickness of about 6000 (λ) according to the design (FIG. 2(D)).

After that, the above-mentioned nitride film 15 and the pad oxide film 13 remaining in the active region 25 are removed by etching.
An element M region 27 as shown in FIG. 2(E) is formed.

(Problem to be Solved by the Invention) However, in the conventional method for forming the element M region described above, during the thermal oxidation treatment for forming the element isolation region, the underside of the nitride film that acts as an oxidation-resistant mask is However, there is a problem in that an oxide film grows and a so-called bird's beak occurs.

To explain this point in detail, after forming the pad oxide film 13 and the nitride film 15 with the thicknesses described above, the oxide film 23 is
When grown to a film thickness of about 6000 (λ),
The dimensions of the opening for the purpose of forming the element isolation region are LE (
9) in FIG. 2(B), and the dimension LF of the M region for the element actually formed (see FIG. 2(E)), then LF
The conversion difference ΔD determined by LE is about 0.9 (μm). As can be understood from this, the width of the bird's beak corresponds to ΔD/2, and the occurrence of this bird's beak increases the size of the field area. For this reason, when manufacturing a semiconductor device after device isolation, mask misalignment occurs in the photolithography process for forming various components in the active region, resulting in a decrease in yield.

Further, the above-mentioned expansion of the field region poses a problem in increasing the density of semiconductor devices.

In order to reduce this bird's beak, it is effective to keep the thickness of the bad oxide film small and increase the thickness of the nitride film as described above, but stress is concentrated at the boundary of the resulting element isolation region. This creates a new problem. This stress concentration causes crystal defects, leading to, for example, deterioration of the element isolation region due to an increase in leakage current.

Further, in the conventional region described above, a channel stop region is formed in a portion of the substrate corresponding to the lower side of the element isolation region for the purpose of preventing inversion of a parasitic transistor (field transistor).

Along with the above-described thermal oxidation treatment, thermal diffusion of impurities implanted into the channel stop region also progresses.

For this reason, in particular, the lateral diffusion of the impurity causes a substantial reduction in the size of the active region, and there is a problem that, for example, the so-called narrow channel effect is likely to occur, such as increasing the threshold value V of the transistor. .

The present invention has been made in view of the various problems of the conventional technology described above, and by reducing the conversion difference ΔD described above, crystal defects are reduced, narrow channel effects are suppressed, and semiconductor snow production is improved. It is an object of the present invention to provide a method for forming an element isolation region that can achieve high density.

(Means for Solving the Problems) In order to achieve this object, the method for forming an element isolation region of the present invention includes the steps of sequentially forming a bad oxide film and a nitride film on the surface of a substrate made of single crystal silicon. and a step of sequentially etching and removing the nitride film and pad oxide film formed in the field region of the substrate to form an opening, and removing the substrate corresponding to the field region through the opening. a step of forming a groove on the groove, a step of forming an inner oxide film consisting of a side oxide film and a bottom oxide film in the groove, a step of etching away the bottom oxide film, and a buried layer backfilling the groove. The method is characterized in that it includes a step of forming an element isolation region by selective silicon growth, and a step of growing an oxide film on the surface of the buried layer described above to form an element isolation region.

(Function) According to the configuration of the method for forming an element isolation region according to the present invention, first, when growing an oxide film by thermal oxidation treatment, the oxygen diffusion direction is different from the pad oxide film to the side oxide film in the trench. Distributed in the direction of extension.

Therefore, compared to the conventional method, it is possible to reduce the conversion difference ΔD described above without changing the composition of the component that functions as an oxidation-resistant mask, and to reduce the bird's beak without causing deterioration in breakdown voltage of the element isolation region. can be achieved.

Further, according to this method, the buried layer is formed with a sufficient impurity concentration so that the side oxide film reduces lateral diffusion of impurities implanted into the buried layer. Because of this,
Even if the film thickness of the element isolation region is made smaller than that of the element isolation region of the conventional structure, a sufficient breakdown voltage can be achieved.

In general, according to the method of the present invention, since the bottom oxide film described above is removed and the buried layer is formed with the single crystal silicon substrate exposed, only the inside of the trench can be selectively backfilled.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the drawings referred to in the following description are only schematic illustrations to the extent that the present invention can be understood, and the present invention is not limited only to these illustrated examples.

FIGS. 1(A) to (G) are explanatory diagrams showing schematic cross-sections of the substrate for each process, similar to FIGS. 2(A) to (E), in order to explain the present invention in detail. . In these figures, components having the same functions as those already described are designated by the same reference numerals.

First, as in the conventional area described above, the substrate 11
Dry oxidation is performed on the surface of the pad oxide film 13 to form a pad oxide film 13 with a thickness of about 300 (λ). Subsequently, approximately 1.0% of
A nitride film 15 is deposited to a thickness of about 500 (people),
The base shown in FIG. 1(A) is obtained.

Next, a resist pattern (not shown) 8 is formed that exposes only the surface of the nitride film 15 corresponding to the field region 17. Using this resist pattern as an etching mask,
By RIE method or other anisotropic etching region,
Nitride film 15 and pad oxide film 1 on field region [17]
3 are sequentially removed to form an opening 19 that exposes the surface of the substrate 11 described above.

Roughly, using the above-mentioned resist pattern as a mask, an anisotropic etching process was performed on the substrate 11, as shown in FIG.
A groove portion 29 as shown in 8) is formed.

Here, the above-mentioned steps will be explained in detail.

In this embodiment, a case has been described in which a resist pattern is used as an etching mask when forming the opening 19 and the groove 29. However, when forming the above-mentioned components by etching, it is necessary to etch at least three layers in one resist pattern formation. Therefore, if it is difficult to form a resist pattern with a sufficient thickness as an etching mask, a film made of silicon oxide (not shown in the figure) may be formed on the upper side of the nitride film 15 in the step explained in FIG. 1(A). M) may be applied and this M may be used as an etching mask.

Further, in this embodiment, the substrate 11 was removed by etching to a depth of about 0.3 (μm) to form a groove 29 as shown.

Next, the pattern oxide film 1 described above is applied to the base described above.
3, a dry oxidation process is performed to form an inner oxide film 31 on the substrate 11 exposed from the groove 29 (see FIG.
C)).

The above-mentioned inner surface oxide film 31 is formed by using the remaining nitride film 15 as an oxidation-resistant mask, and includes a side surface oxide film 31a formed on the surface corresponding to the inner side of the groove portion 29 and a side surface oxide film 31a formed on the surface corresponding to the bottom portion of the groove portion 29. A bottom oxide film 31b is formed. Further, in this example, the dry oxidation conditions were set so that the thickness of the above-mentioned inner surface oxide film 31 was about 400 (layers).

Next, only the bottom oxide film 31a described above is removed by the RIE method or other anisotropic etching method described above, and the substrate 1 is etched at the bottom of the groove 29 as shown in FIG. 1(D).
Obtain a base in which 1 is exposed.

Subsequently, the buried layer 33 is selectively grown on the upper side of the single crystal silicon constituting the substrate 11 using a conventionally well-known selective silicon growth region, and the trench 29 described above is backfilled.
A base as shown in FIG. 1(E) is obtained.

Semiconductor materials constituting this buried layer 33 include single crystal silicon, polysilicon, and amorphous silicon, which contain impurities that constitute the channel stop region t*2+ (see FIG. 2 (C)) in the conventional region. Cover it in the condition.

As already explained, the impurity concentration at this time can be set to a value depending on the design of the desired semiconductor device; All you need to do is to form a layer.

Furthermore, according to the method of this embodiment, the channel stop is formed by depositing a semiconductor material containing impurities. Therefore, compared to the conventional region, the channel stop can be formed with an impurity having a relatively high degree of J. is also possible.

Next, with the buried layer 33 exposed through the opening 19 described above, wet oxidation is performed using the nitride film 15 as an oxidation mask, as in the conventional method. In this way, an oxide film 35 is formed continuous with the pad oxide film 13 and has a thickness of about 4000 (λ) according to the design (FIG. 1(F)).

After going through various steps in this way, the nitride film 15 and pad oxide film 13 remaining in the active region 25 are etched away to form an element isolation region 37 as shown in FIG. 1(G). .

Here, the film thickness and formation state of the element isolation region formed by the method of the present invention will be explained in detail.

As can be understood from the above description, after forming the groove portion 29, the inner surface oxide film 31 is formed in the portion 29. By removing the bottom oxide film 31a of the inner surface oxide film 31, the buried layer 33 can be selectively grown with silicon, and can be formed with a high concentration of impurities. Therefore, even if the thickness of the oxide film 35 formed by the above-described thermal oxidation step is smaller than that of the conventional structure, a sufficient breakdown voltage of the element isolation region can be ensured. Relaxation of the heat treatment conditions makes it possible to shorten the time required for film thickness growth, and by relaxing the treatment of the base under high temperature conditions, it is also possible to reduce the frequency of occurrence of crystal defects.

In addition, since the conditions for forming the oxide film 35 can be relatively relaxed in this way, it is possible to reduce the conversion difference ΔD mentioned above, and under the above conditions ΔD has a value of about 0.4 (um) or less. As a result, a reduction in bird's beak was observed. Such an effect is achieved not only by the growth conditions (reduction in film thickness) of the oxide film 35, but also by the aforementioned lateral diffusion of oxygen into both the bad oxide film 13 and the side oxide film 31b. The fact that it can be dispersed is also considered to be a factor.

Roughly speaking, this side oxide film 31b has an effect not only on the formation of the oxide film 35, but also on the buried layer 33.
Even when the impurity contained in the active region 25 is at a high concentration, it also serves to prevent impurity diffusion in one direction of the active region 25. In this case, the height of the above-mentioned side oxide film 31b (corresponding to the depth of the above-mentioned trench 29) is determined depending on the depth of the substrate used as the desired active region of the semiconductor device.
If is designed to have a sufficiently large value l, the aforementioned narrow channel effect can be reduced.

Although the embodiments of the present invention have been described above, the present invention is not limited to the specific conditions described above.

For example, in the above-described embodiment, the buried layer 33 itself is deposited with 8 doped impurities added thereto. However, according to the method of the present invention, various methods can be used to form the buried layer.

First, ions are implanted into the base in the state described with reference to FIG. 1 (D) 8 to diffuse impurities only to the bottom of the trench, and then a buried layer is formed by selective silicon growth. You can also. In this case, for example, impurities are diffused into the buried layer side by thermal oxidation treatment when growing an oxide film, forming a channel stop.
By providing the side oxide film, diffusion toward the active region becomes substantially negligible.

It is clear that these materials, dimensions, layout, numerical conditions, and other conditions may be modified and modified as desired within the scope of the present invention.

(Effects of the Invention) As is clear from the above explanation, according to the method for forming the element region 111 of the present invention, the oxidation treatment of the buried layer is performed with the side oxide film provided, so that oxygen diffusion is prevented. The directions are dispersed in the respective extending directions of the pad oxide film and the side oxide film. Therefore, the above-mentioned conversion difference ΔD can be reduced, and bird's beak can be reduced without deteriorating the withstand voltage of the element isolation region.

Further, the buried layer is formed with a sufficient impurity concentration so that the side oxide film reduces lateral diffusion of impurities implanted into the buried layer. Therefore, even if the film thickness of the element isolation region is reduced, sufficient breakdown voltage can be achieved, the conversion difference D is reduced, and the heat treatment time is shortened.
The frequency of occurrence of crystal defects can be reduced.

According to the method of the present invention, since the bottom oxide film mentioned above is removed and the buried layer is formed with the single crystal silicon substrate exposed, it is possible to selectively backfill only the inside of the trench. can.

Therefore, by reducing the conversion difference ΔD, it is possible to reduce crystal defects, suppress the narrow channel effect, and form an element isolation region that can realize high density semiconductor devices. can provide various semiconductor devices M having excellent characteristics at a high yield and at low cost.

[Brief explanation of the drawing]

FIGS. 1(A) to (G) are explanatory diagrams showing schematic cross-sections of the substrate for each step in order to explain an embodiment of the method of the present invention, and FIGS. 2(A) to (E) are conventional FIG. 1 is an explanatory diagram similar to FIGS. 1(A) to (G) for explaining the area of FIG. 11... Substrate, 13... Pad oxide film, 15...
...Nitride film 17...Field region, 19...
- Opening 21...Channel stop region, 23.3
5...Oxide film 25...Active region, 27
．． 37... Element isolation region 29... Groove, U...
...Inner surface oxide film 31a...Bottom surface oxide film, 31b
... Side oxide film 33 ... Buried layer. Patent applicant Oki Electric Industry Co., Ltd. 31b
31b3 Old oxide film 25 Explanatory diagram of the near-active region (Explanatory diagram of the conventional area Fig. 1)

Claims (1)

[Claims] (1) A step of sequentially forming a pad oxide film and a nitride film on the surface of a substrate made of single crystal silicon, and sequentially etching away the nitride film and pad oxide film formed in the field region of the substrate to form an opening. forming a groove in the substrate corresponding to the field region through the opening; forming an inner oxide film consisting of a side oxide film and a bottom oxide film in the groove; The method includes the steps of etching and removing a bottom oxide film, selectively growing a buried layer to fill back the trench, and growing an oxide film on the surface of the buried layer to form an element isolation region. A method for forming an element isolation region.