JPH01295438A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form a minute element isolating structure which is equal to the size of a mask, by implanting oxygen ions or nitrogen ions into a polycrystalline silicon film, performing heat treatment transforming the upper surface of the polycrystalline silicon film into an oxide film or a nitride film, and forming a cap layer. CONSTITUTION:First insulating films 110 and 120 are formed on a semiconductor substrate 100. The first insulating films 110 and 120 at a desired regions are etched. The semiconductor substrate 100 is further etched to a desired depth, and an opening part is formed. A second insulating film 150 is formed at the opening part. Thereafter, a semiconductor film 160 is deposited on the entire surface and in the opening part. Back etching is performed, and the semiconductor film 160 is made to remain only in the opening part. Then, oxygen ions or nitrogen ions are implanted. Heat treatment is further performed. Thus, a third insulating film 180 is formed on the upper surface of the semiconductor film 160. Thereafter, the first insulating films 110 and 120 are removed. In this way, miniaturization can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, particularly a semiconductor device having an element isolation structure using grooves.

2. Description of the Related Art In order to achieve higher integration and higher speed of semiconductor devices, it is necessary to form element isolation regions with narrower widths.

As a method capable of solving the above problem, an element isolation method using a groove has been announced, in which a groove is formed on a semiconductor substrate and the groove is filled with an insulating film or the like to isolate the elements. Furthermore, considering the stress exerted on the semiconductor substrate during heat treatment, an element isolation method in which a polycrystalline silicon film is buried is desirable. For example, as shown in FIG. 3(a), a method for forming the groove isolation structure is to sequentially form a thermal oxide film 2 of about 500 Å and a nitride film 11E3 of about 1500 Å on the surface of a P-type semiconductor substrate 1, and then use photolithography to form grooves. A resist 4 is formed to cover areas other than the area to be formed. Next, as shown in FIG. 3(b), using the resist 4 as a mask, the nitride film 3 and the thermal oxide film 2 are removed.
Further, the semiconductor substrate 1 is etched to a depth of about 3 μm to form a groove 5 for element isolation, and then boron ions are implanted into the bottom of the groove 5 to form a channel stopper region 6. Thereafter, the resist 4 is removed and the groove 5 is thermally oxidized. Next, as shown in FIG. 3C, a polycrystalline silicon film 7 is deposited within the trench 5 and on the surface of the semiconductor substrate 1.

As shown in FIG. 3(d), the polycrystalline silicon film 7 is etched until the nitride film '3 is exposed.

Next, as shown in FIG. 3(e), the surface of the polycrystalline silicon film 7 is oxidized to form a thick oxide film 8 above the groove 5. After that, the nitride film 3 and thermal oxide film 2 remaining on the semiconductor substrate 1
By removing , an element isolation structure shown in FIG. 3(f) is obtained.

Problems to be Solved by the Invention When the above-mentioned conventional technique is applied to a semiconductor device, as shown in FIG. 3(e), when the surface of the polycrystalline silicon film 7 is oxidized, the oxide film 8 seeps into the element region directly under the nitride film 3. For this reason, a pattern conversion difference occurs between the width of the finished isolation region and the mask dimension, which impedes miniaturization.

Furthermore, when the surface of the polycrystalline silicon film 7 is oxidized, the oxide film 8 penetrates not only into the element region but also along the oxide film formed on the side walls of the trench 5. As a result, semiconductor substrate 1
This adds stress to the semiconductor substrate, causing crystal defects in the semiconductor substrate.

Means for Solving the Problems A method of manufacturing a semiconductor device according to the present invention includes the following steps.

forming a first insulating film on a semiconductor substrate, etching the first insulating film in a desired region, further etching the semiconductor substrate to a desired depth to form an opening; and etching a second insulating film in the opening. The process of forming an insulating film, the process of depositing a semiconductor film on the entire surface and inside the opening, and the process of leaving the semiconductor film only in the opening by back-etching, the process of implanting oxygen ions or nitrogen ions, and further heat-treating the semiconductor film. The method includes a step of forming a third insulating film on the upper surface of the film and a step of removing the first insulating film.

Function In the present invention, instead of oxidizing the surface of a polycrystalline silicon film to form a cap layer, oxygen ions or nitrogen ions are ion-implanted, and then heat treatment is performed to form an oxide film or a nitrided film on the top surface of the polycrystalline silicon film. A cap layer is formed instead of a membrane.

Therefore, the oxide film does not seep into the element region, and no difference in pattern conversion occurs between the width of the finished isolation region and the mask dimension. Further, since the oxide film does not seep along the oxide film formed on the sidewalls of the element region and the trench, no crystal defects are caused in the semiconductor substrate.

Example (Example 1) Example 1 of the present invention will be described below using FIGS. 1(a) to (g). As shown in FIG. 1(a), on the surface of the P-type semiconductor substrate 100, a thermally oxidized WXllO film of about 500 amps and a nitride film 120 of about 1500 amps are sequentially formed, and then photolithography is applied to cover areas other than the area where the groove is to be formed. 130 is formed. As shown in FIG. 1(b), the nitride film 320 and the thermal oxide film 110 are etched using the resist 130 as a mask, and the semiconductor substrate 100 is further etched to a depth of about 3 μm to form a trench for element isolation. A channel stopper region 140 is formed by implanting boron ions into the bottom surface. Thereafter, the resist 130 is removed and a thermal oxide film 150 of about 1000 Å is formed in the groove. Next, as shown in FIG. 1C, polycrystalline silicon 16G is deposited in the trench and on the surface of the semiconductor substrate 100. As shown in FIG. 1(d), the polycrystalline silicon film 111i0 is etched until the nitride film 120 is exposed. Then the first
As shown in figure (e), the acceleration voltage is 20 K e V,
Ion implantation of 0◆ is performed at a dose of 110I6 to 10''/cm''. After that, for 30 to 60 minutes in N2 atmosphere, 115
When heat-treated at 0° C., an oxide film cap layer 180 with a thickness of about 200 OA is formed as shown in FIG. 1(f). Next, by removing the nitride film 120 and the thermal oxide film 110, an element isolation structure using grooves as shown in FIG. 1(g) is obtained.

(Example 2) Example 2 of the present invention will be described below using FIGS. 2(a) to (g). As shown in FIG. 2(a), after a thermal oxide film 210 of about 2000 Å is formed on the surface of a P-type semiconductor substrate 200, a resist 220 is formed by photolithography to cover areas other than the area where the groove is to be formed.

As shown in FIG. 2(b), the thermal oxide film 210 is etched using the resist 220 as a mask, and then the semiconductor substrate 210 is etched.
00 to a depth of about 3 μm to form a groove for element isolation, and then boron ions are implanted into the bottom of the groove to form a channel stopper region 230.

Thereafter, the resist 22G is removed and a thermal oxide film 240 of about 100 OA is formed in the groove. Next, as shown in FIG. 2C, polycrystalline silicon 250 is deposited in the trench and on the surface of semiconductor substrate 200. As shown in FIG. 2(d), the polycrystalline silicon film 250 is etched until the thermally oxidized M210 is exposed. Next, as shown in FIG. 3(e), the acceleration voltage was set to 40 K e V and the dose was set to 1016 to 10"/c.
ion implantation of N2φ at a temperature of
When heat-treated at 900° C. for 0 minutes, a nitride film cap layer 270 is formed with a thickness of about 200 OA, as shown in FIG. 2(f). Next, when the thermal oxide film 210 is removed, FIG. 2(g)
An element isolation structure using grooves shown in FIG. 1 can be obtained.

Effects of the Invention According to the present invention described above, the cap layer of the polycrystalline silicon film is formed by ion implantation of oxygen ions or nitrogen ions and heat treatment without using oxidation as in the conventional technology, so that the width of the finished isolation region can be reduced. There is no difference in pattern conversion between the mask dimensions and the mask dimensions.

In addition, since oxidation is not used to form the cap layer as in the conventional technology, the oxide film does not seep along the oxide film formed on the element region and the sidewalls of the trench, so it does not cause crystal defects in the semiconductor substrate. . As a result, leakage current is reduced. As described above, according to the present invention, a fine element isolation structure equal to the mask size can be formed, and the element characteristics are significantly improved.

[Brief explanation of the drawing]

1(a)-(g) and FIG. 2(a)-(g) are process sectional views showing an example of forming an isolation structure using a groove using the present invention, and FIG. 3(a)-(g). (D) is a process cross-sectional view of forming an isolation structure using a groove using a conventional technique. 100, 200...P-type semiconductor substrate, 110. 1
50. 210. 240... thermal oxide film, 130.
220... resist, 140. 230...Channel stopper, IGo, 250...Polycrystalline silicon, 17G...0◆Ion implantation region, 260...N
2” ion implantation region, 180... oxide film cap layer,
270...Nitride film cap layer. Name of agent Patent attorney Toshio Nakao Figure 18 too'”F Kensen IIA
Body substrate tto, tsθ...-naheihihi membrane Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] A first insulating film is formed on a semiconductor substrate, and a first insulating film is formed on a desired region.
etching the insulating film and further etching the semiconductor substrate to a desired depth to form an opening, forming a second insulating film in the opening, and depositing a semiconductor film on the entire surface and inside the opening. , a step of leaving the semiconductor film only in the opening by back-etching, a step of ion-implanting oxygen ions or nitrogen ions, and forming a third insulating film on the upper surface of the semiconductor film by further performing heat treatment; a step of removing an insulating film, the semiconductor film is surrounded by a third insulating film in a surface region of the opening, a second insulating film in a lower surface region and a side region, and the semiconductor film is placed in the opening. A method for manufacturing a semiconductor device characterized by embedding.