JPS6362252A - Manufacture of dielectric isolation substrate - Google Patents
Manufacture of dielectric isolation substrateInfo
- Publication number
- JPS6362252A JPS6362252A JP20592486A JP20592486A JPS6362252A JP S6362252 A JPS6362252 A JP S6362252A JP 20592486 A JP20592486 A JP 20592486A JP 20592486 A JP20592486 A JP 20592486A JP S6362252 A JPS6362252 A JP S6362252A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- single crystal
- crystal silicon
- polished
- approx
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 238000002955 isolation Methods 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 7
- 238000005498 polishing Methods 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract 1
- 239000013078 crystal Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 229910052594 sapphire Inorganic materials 0.000 description 3
- 239000010980 sapphire Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) この発明は、誘電体絶縁分離基板の製造方法に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a method for manufacturing a dielectric insulation isolation substrate.
(従来の技術)
従来ICJPLSIなどで各素子間の分離を絶縁体で行
なういわゆる誘電体分離法はp −n接合分離に比べて
、(1)もれ電流を極めて小さくすることができる%(
2)耐圧を大きくすることができる、(3)電圧印加の
方向に気を配る必要がない、等の利点を有する。理想的
な誘電体分離は各素子を電極接続部を除いて絶縁体で完
全に包み込むことで達成される。このような素子は例え
ばサファイア上にシリコンをエピタキシャル成長させた
SO8基板を用いて形成することができる。しかしなが
らサファイアは高価でありまたシリコンとの結晶整合性
も完全ではなく良質の単結晶が得られない膜厚を充分厚
くすることができないなどの理由で作製できる素子の種
類に制限がある。サファイアのような絶縁体基板を用い
ない誘電体分離法もこれまで数多く提案されている。そ
の−例を第3図(a)〜(d)で説明する。(Prior Art) Conventionally, the so-called dielectric isolation method in which each element is isolated using an insulator, such as in ICJPLSI, has the following advantages over p-n junction isolation: (1) Leakage current can be extremely reduced by % (
It has advantages such as 2) the withstand voltage can be increased, and (3) there is no need to pay attention to the direction of voltage application. Ideal dielectric isolation is achieved by completely encasing each element with an insulator except for electrode connections. Such an element can be formed using, for example, an SO8 substrate in which silicon is epitaxially grown on sapphire. However, sapphire is expensive, its crystal consistency with silicon is not perfect, and the types of devices that can be manufactured are limited for reasons such as the inability to obtain a high-quality single crystal and the inability to make the film thick enough. Many dielectric isolation methods that do not use an insulating substrate such as sapphire have been proposed so far. An example thereof will be explained with reference to FIGS. 3(a) to 3(d).
まず第3図(a)は、シリコン単結晶基板31で通常結
゛晶方位(100)面を主面として結晶方位によってエ
ツチング速度の差を有するアルカリ系のエツチング液に
よる異方性エツチング技術により複数の分離7字溝32
を形成し、第3図(b)に示すように全面をSin、膜
等の絶縁膜33で覆う。この後第3図(C)に示すよう
に絶縁膜上に多結晶シリコン支持体層34を堆積する。First, FIG. 3(a) shows a silicon single-crystal substrate 31 that is etched using an anisotropic etching technique using an alkaline etching solution that has a (100) crystal orientation as its main surface and has different etching rates depending on the crystal orientation. Separation 7-shaped groove 32
The entire surface is covered with an insulating film 33 such as a Si film or the like, as shown in FIG. 3(b). Thereafter, a polycrystalline silicon support layer 34 is deposited on the insulating film as shown in FIG. 3(C).
次に裏表を逆にしてシリコン基板31を研磨エツチング
等により各単結晶が完全に分離されるまで削り落とす。Next, the silicon substrate 31 is turned upside down and polished off by etching or the like until each single crystal is completely separated.
そして第3図(d)に示すようにこの分離された単結晶
内31 (a)(b)に半導体層3 s (a)(b)
を形成して誘電体分離された素子を得る。As shown in FIG. 3(d), semiconductor layers 3s (a) and (b) are formed within the separated single crystal 31 (a) and (b).
to obtain dielectrically isolated elements.
′ この様な従来の方法での最大の問題は、支持体層の
形成が必須である点にある。例えば良く使われる多結晶
シリコンの場合でも堆積速度が遅いために研磨等の工程
に耐え得る充分な厚さを得るために非常に長い時間を要
する。さらに充分な厚さの多結晶シリコンを形成した場
合、この多結晶シリコンと単結晶シリコンの熱膨張係数
の違いから生ずる反りが発生し、場合によっては数百ミ
クロンの反りによる変形が発生し、支持体層形成後のフ
ォトエツチング工程が困難になり製品の歩留りが非常に
悪い欠点があった。' The biggest problem with such conventional methods is that it is essential to form a support layer. For example, even in the case of commonly used polycrystalline silicon, the deposition rate is slow, so it takes a very long time to obtain a sufficient thickness to withstand polishing and other steps. Furthermore, if polycrystalline silicon is formed to a sufficient thickness, warping will occur due to the difference in thermal expansion coefficients between polycrystalline silicon and single crystal silicon, and deformation due to warping of several hundred microns may occur in some cases. The photo-etching process after forming the body layer is difficult, resulting in a very poor product yield.
(発明が解決しようとする問題点)
本発明は、上述した従来技術の問題点を改良したもので
反りによる変形を防止した接合体を用いた誘電体絶縁分
離基板の製造方法を提供することを目的とする。(Problems to be Solved by the Invention) The present invention improves the above-mentioned problems of the prior art and provides a method for manufacturing a dielectric insulation isolation substrate using a bonded body that prevents deformation due to warping. purpose.
(問題点を解決するための手段)
本発明は二枚の半導体基板の表面が充分平滑に研磨され
ている時その研磨面同士を充分に清浄な雰囲気下で直接
密着させることにより強固な基板接合体が得られるとい
う知見に基き、この技術を誘電体分離に適用する。(Means for Solving the Problems) The present invention provides strong substrate bonding by directly bringing the polished surfaces of two semiconductor substrates into close contact with each other in a sufficiently clean atmosphere when the surfaces of two semiconductor substrates have been sufficiently polished. Based on the knowledge that it is possible to obtain dielectric materials, we will apply this technology to dielectric separation.
(作用)
誘電体分離形半導体装置における素子間分離のV形溝の
深さは一般に数十ミクロンであり、これを充分lC埋込
む程度の多結晶シリコン層の形成では基板の反りは無視
できる。従って反りが発生する直前で多結晶シリコン層
の形成を終了し表面を充分平滑に研磨した後に前記手段
により強固な基板接合体を形成する事により反りが無く
、信頼性の高い誘電体絶縁分離基板を製造する事が可能
となる。(Function) The depth of the V-shaped groove for isolation between elements in a dielectrically isolated semiconductor device is generally several tens of microns, and when a polycrystalline silicon layer is formed to the extent that it is sufficiently filled with 1C, warping of the substrate can be ignored. Therefore, by completing the formation of the polycrystalline silicon layer just before warpage occurs, polishing the surface sufficiently smooth, and then forming a strong substrate assembly using the above-mentioned method, a highly reliable dielectric insulating separated substrate with no warpage can be obtained. It becomes possible to manufacture.
(実施例) 以下本発明の実施例を図を参照して説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第1図は本発明の断面構造を示した一実施例で、誘電体
膜2でとり囲まれた厚みの異替る単結晶の島1a及び1
bの中にそれぞれ不純物拡散層7a及び7bが導入され
誘電体分離された半導体装置が形成されている。埋込み
の為の多結晶シリコン3は充分平滑に研磨され接合すべ
き第2の単結晶シリコン基板5との間で誘電体膜6を介
在させて4の位置で接合体を形成させ、誘電体絶縁分離
基板を構成している。FIG. 1 shows an embodiment showing a cross-sectional structure of the present invention, in which single crystal islands 1a and 1 of different thicknesses are surrounded by a dielectric film 2.
Impurity diffusion layers 7a and 7b are introduced into the semiconductor device 7a and 7b, respectively, to form a dielectrically isolated semiconductor device. The polycrystalline silicon 3 for embedding is polished sufficiently smooth and a dielectric film 6 is interposed between it and the second single-crystal silicon substrate 5 to be bonded to form a bonded body at the position 4. It constitutes a separate substrate.
′□ 第′2図(a)〜(e)は実際に本発明を
用いて誘電体絶縁分離基板を製造する場合の一実施例を
示す図である。第2図ta>は面指数(100)のN型
単結晶シリコン基板1を例えばKOHを主成分とするア
ルカリ性エツチング液を用い分離用の7字溝を約50ミ
クロンの深さで形成する。図中メサの段差が異なるのは
一般に知られているフォトエツチング工程を二度行なう
ことにより容易に所望の段差を形成することが可能であ
る。Figures 2(a) to 2(e) are diagrams showing an embodiment in which a dielectric insulation isolation substrate is actually manufactured using the present invention. In FIG. 2, 7-shaped grooves for separation are formed at a depth of approximately 50 microns on an N-type single crystal silicon substrate 1 having a surface index of (100) using, for example, an alkaline etching solution containing KOH as a main component. In the figure, the difference in level between the mesas is different because the desired level difference can be easily formed by performing a generally known photo-etching process twice.
第2図(blは、酸化雰囲気中で熱酸化膜2を約1ミク
ロン形成しこの上に第2図(C)に示すように多結晶ポ
リシリコン3を約80ミクロン堆積させる。In FIG. 2(bl), a thermal oxide film 2 of about 1 micron is formed in an oxidizing atmosphere, and polycrystalline silicon 3 of about 80 micron is deposited thereon as shown in FIG. 2(C).
次に第2図(d)に示すように多結晶ポリシリコン側を
充分平滑になるように化学的又は機械的に研磨を行ない
熱酸化膜2が露出する手前で研磨が終了するように多結
晶ポリシリコンの研磨面4を形成する。さらに上記基板
の多結晶ポリシリコンと熱酸化膜6でおおわれたもう一
方の単結晶シリコン基板5との相対向する面の鏡面研磨
側どうしを向けて、第2図(e)に示すように密着させ
、200℃以上の温度で熱処理して接合させる。このよ
うに形成された基板接合体の一方の単結晶シリコン基板
1側から研磨、エツチング等により各単結晶が完全に分
離されるまで削り落とし第1図に示すような欅造の誘電
体絶縁分離基板を完成することができる。Next, as shown in FIG. 2(d), the polycrystalline silicon side is chemically or mechanically polished to make it sufficiently smooth, and the polishing is completed before the thermal oxide film 2 is exposed. A polished surface 4 of polysilicon is formed. Further, the polycrystalline polysilicon of the above substrate and the other single crystal silicon substrate 5 covered with the thermal oxide film 6 are brought into close contact with each other with the mirror-polished sides of their opposing surfaces facing each other as shown in FIG. 2(e). and then heat-treated at a temperature of 200° C. or higher to bond them. The single crystal silicon substrate 1 side of the substrate assembly thus formed is ground down by polishing, etching, etc. until each single crystal is completely separated, and the keyaki-zukuri dielectric insulation is separated as shown in Fig. 1. The board can be completed.
上記実施例では、接合すべき多結晶シリコン面に対し、
半導体単結晶シリコン基板を用いたが。In the above embodiment, for the polycrystalline silicon surface to be bonded,
A semiconductor single-crystal silicon substrate was used.
多結晶シリコン基板を用いたもの?ζおいても本発明を
適用することができる。Something using a polycrystalline silicon substrate? The present invention can also be applied to ζ.
本発明によれば誘電体分離された単結晶シリコンの島の
厚みが異なる半導体装置を容易に作製することが可能で
、基板の反りを無視することができ、従来技術と比較し
て短時間で製造ができ、信頼性が高く、かつ支持体層の
単結晶シリコン基板の厚さを任意に選択することができ
る為シリコンウニ゛ハの径が大口径になっても取り扱い
上なんら支障がおきず1歩留りの高い誘電体絶縁分離基
板を提供することができる。According to the present invention, it is possible to easily fabricate semiconductor devices in which dielectrically separated single-crystal silicon islands have different thicknesses, the warpage of the substrate can be ignored, and it is possible to fabricate semiconductor devices in a shorter time than with conventional techniques. It is easy to manufacture, highly reliable, and the thickness of the single crystal silicon substrate of the support layer can be selected arbitrarily, so there is no problem in handling even if the diameter of the silicon wafer becomes large. 1. A dielectric insulation isolation substrate with high yield can be provided.
第1図は本発明の一実施例における断面図、第2図は本
発明の一実施例の製造方法を説明するための工程断面図
、第3図は従来の誘電体絶縁分離基板の製造方法を説明
するための工程順の断面図である。
1:結晶面(100)を主面とする半導体単結晶シリコ
ン基板、2:絶縁膜、3:多結晶シリコン層。
4:多結晶シリコン層の研磨面(接合面)、5:半導体
単結晶シリコン基板、6:絶縁膜。
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
第1図
第2図Fig. 1 is a cross-sectional view of an embodiment of the present invention, Fig. 2 is a process cross-sectional view for explaining a manufacturing method of an embodiment of the present invention, and Fig. 3 is a conventional method of manufacturing a dielectric insulation isolation substrate. FIG. 1: Semiconductor single crystal silicon substrate with crystal plane (100) as the main surface, 2: Insulating film, 3: Polycrystalline silicon layer. 4: Polished surface (joint surface) of polycrystalline silicon layer, 5: Semiconductor single crystal silicon substrate, 6: Insulating film. Agent Patent Attorney Noriyuki Chika Yudo Kikuo Takehana Figure 1 Figure 2
Claims (2)
エッチングした後、この表面を誘電体膜で覆い、さらに
支持体層を形成した後誘電体膜で絶縁分離された単結晶
シリコンの多数の島領域を有する誘電体絶縁基板の製造
方法において、支持体層の形成を多結晶シリコン層と第
2の半導体単結晶シリコン基板との間に誘電体膜を介在
させて接合体を形成したことを特徴とする誘電体絶縁分
離基板の製造方法。(1) After etching the surface of a semiconductor single crystal silicon substrate into a desired shape, this surface is covered with a dielectric film, and a support layer is further formed. In a method for manufacturing a dielectric insulating substrate having an island region, a support layer is formed by interposing a dielectric film between a polycrystalline silicon layer and a second semiconductor single crystal silicon substrate to form a bonded body. A method for manufacturing a dielectric insulation isolation substrate.
コン層と半導体多結晶シリコン基板とで行なったことを
特徴とする特許請求の範囲第1項記載の誘電体絶縁分離
基板の製造方法。(2) The method for manufacturing a dielectric insulating isolated substrate according to claim 1, characterized in that the support layer to be bonded is formed by the polycrystalline silicon layer and the semiconductor polycrystalline silicon substrate. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20592486A JPS6362252A (en) | 1986-09-03 | 1986-09-03 | Manufacture of dielectric isolation substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20592486A JPS6362252A (en) | 1986-09-03 | 1986-09-03 | Manufacture of dielectric isolation substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6362252A true JPS6362252A (en) | 1988-03-18 |
Family
ID=16514993
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20592486A Pending JPS6362252A (en) | 1986-09-03 | 1986-09-03 | Manufacture of dielectric isolation substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6362252A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01302739A (en) * | 1988-05-30 | 1989-12-06 | Toshiba Corp | Dielectric isolation semiconductor device and manufacture thereof |
EP0531018A2 (en) * | 1991-08-31 | 1993-03-10 | Shin-Etsu Handotai Company Limited | Method for production of dielectric-separation substrate |
JPH06151575A (en) * | 1992-11-12 | 1994-05-31 | Nippondenso Co Ltd | Manufacture of semiconductor substrate |
EP2266675A2 (en) | 2009-06-25 | 2010-12-29 | Chisso Corporation | Chromatography medium, preparation method of the same, and method for producing virus vaccine using the chromatography medium |
-
1986
- 1986-09-03 JP JP20592486A patent/JPS6362252A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01302739A (en) * | 1988-05-30 | 1989-12-06 | Toshiba Corp | Dielectric isolation semiconductor device and manufacture thereof |
EP0531018A2 (en) * | 1991-08-31 | 1993-03-10 | Shin-Etsu Handotai Company Limited | Method for production of dielectric-separation substrate |
EP0531018A3 (en) * | 1991-08-31 | 1994-06-01 | Shinetsu Handotai Kk | Method for production of dielectric-separation substrate |
JPH06151575A (en) * | 1992-11-12 | 1994-05-31 | Nippondenso Co Ltd | Manufacture of semiconductor substrate |
EP2266675A2 (en) | 2009-06-25 | 2010-12-29 | Chisso Corporation | Chromatography medium, preparation method of the same, and method for producing virus vaccine using the chromatography medium |
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