JPH056883A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

Info

Publication number
JPH056883A
JPH056883A JP27674291A JP27674291A JPH056883A JP H056883 A JPH056883 A JP H056883A JP 27674291 A JP27674291 A JP 27674291A JP 27674291 A JP27674291 A JP 27674291A JP H056883 A JPH056883 A JP H056883A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
film
manufacturing
substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP27674291A
Other languages
Japanese (ja)
Inventor
Kenji Anzai
賢二 安西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP27674291A priority Critical patent/JPH056883A/en
Publication of JPH056883A publication Critical patent/JPH056883A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To provide a method for forming an SOI (Silicon on Insulator) substrate having excellent crystallinity. CONSTITUTION:An oxide film 2 is formed on a first silicon substrate 1, an epitaxial silicon grown film 4 is formed on a second silicon substrate 3, and both are bonded at the film 2 side and the film 4 side. The bonded laminated substrates are deleted at the substrate 3 until the film 4 is exposed, and an SOI structure of the film 4, the film 2, and the substrate 1, is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、SOI(Semiconducto
r-On-Insulator) 構造を有する半導体基板の製造方法に
関する。
The present invention relates to an SOI (Semiconducto)
The present invention relates to a method for manufacturing a semiconductor substrate having an r-On-Insulator) structure.

【0002】[0002]

【従来の技術】SOI基板は、半導体シリコン基板上に
SiO2 等の絶縁層を形成して絶縁基板とし、その上に
更に半導体シリコン層を形成したものである。
2. Description of the Related Art An SOI substrate is one in which an insulating layer such as SiO 2 is formed on a semiconductor silicon substrate to form an insulating substrate, and a semiconductor silicon layer is further formed on the insulating substrate.

【0003】しかしながら、絶縁層上に形成する半導体
シリコン層として、いわゆるバルクシリコンを貼り合わ
せ形成したものは、結晶性がわるく、リーク特性、耐圧
特性等に問題があった。
However, the semiconductor silicon layer formed on the insulating layer, which is formed by laminating so-called bulk silicon, has poor crystallinity and has problems such as leak characteristics and withstand voltage characteristics.

【0004】一方、エピタキシャル成長による単結晶の
半導体シリコン層は、結晶欠陥が少なく、不純物の混入
制御も容易なことから、半導体装置に用いられている
(例えば特開昭60−144949号)。また、2枚の
半導体基板の表面を互いに酸化させ、その酸化された面
どうしを貼り合わせる方法が提案されている(例えば特
開昭63−65648号)。
On the other hand, a single-crystal semiconductor silicon layer formed by epitaxial growth has been used in a semiconductor device because it has few crystal defects and the control of impurities is easy (for example, JP-A-60-144949). Further, a method has been proposed in which the surfaces of two semiconductor substrates are mutually oxidized and the oxidized surfaces are bonded to each other (for example, JP-A-63-65648).

【0005】[0005]

【発明が解決しようとする課題】しかしながら、例えば
SOIを形成すべく、絶縁基板上に直接シリコンエピタ
キシャル層を成長させると、そのシリコン層はアモルフ
ァスか多結晶になるので、これを単結晶化するために、
再結晶の処理が必要であった。また、2枚の半導体基板
を互いに酸化させ、その酸化された面どうしを貼り合わ
せる方法では酸化膜面を両基板の主面に形成しなければ
ならないため、製造工程が増加するという問題がある。
However, when a silicon epitaxial layer is grown directly on an insulating substrate in order to form, for example, SOI, the silicon layer becomes amorphous or polycrystalline, so that it is made into a single crystal. To
Recrystallization process was required. Further, in the method of oxidizing two semiconductor substrates to each other and bonding the oxidized surfaces to each other, the oxide film surface has to be formed on the main surfaces of both substrates, which causes a problem that the number of manufacturing steps increases.

【0006】そこで、本発明は、絶縁基板上に直接単結
晶のシリコンエピタキシャル層を形成することができる
半導体基板の製造方法を提供することを目的としてい
る。
[0006] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor substrate in which a single crystal silicon epitaxial layer can be directly formed on an insulating substrate.

【0007】[0007]

【課題を解決するための手段】本発明は、上記目的を達
成するために、第1面を有する第1の半導体基板の上記
第1面に酸化膜を形成する第1の工程と、第2面及びこ
の第2面の裏面である第3面とを有する第2の半導体基
板の上記第2面に単結晶の半導体層を形成する第2の工
程と、この第2の工程を経て上記第2面に単結晶の半導
体層が形成された上記第2の半導体基板と上記第1の工
程を経て酸化膜が形成された上記第1の半導体基板の上
記第1面とを貼り合わせる第3の工程と、この第3の工
程により貼り合わされた上記第2の半導体基板をその第
3面側から上記単結晶の半導体層が露出するまで研摩す
る第4の工程とを備えて構成した。
In order to achieve the above object, the present invention provides a first step of forming an oxide film on the first surface of a first semiconductor substrate having a first surface, and a second step. A second step of forming a single crystal semiconductor layer on the second surface of the second semiconductor substrate having a surface and a third surface which is the back surface of the second surface, and the second step through the second step. A second semiconductor substrate having a single-crystal semiconductor layer formed on its two faces and the first surface of the first semiconductor substrate having an oxide film formed through the first step; And a fourth step of polishing the second semiconductor substrate bonded by the third step from the third surface side thereof until the single crystal semiconductor layer is exposed.

【0008】[0008]

【作用】本発明は、上記構成により、酸化膜を形成した
第1の半導体基板と単結晶の半導体層を形成した第2の
半導体層とを互いに貼り合わせることによって半導体積
層基板を形成する。そのため、絶縁基板上に直接結晶性
のよい単結晶の半導体層を形成することができ、再結晶
処理が不要となる。
According to the present invention, the semiconductor laminated substrate is formed by bonding the first semiconductor substrate having the oxide film and the second semiconductor layer having the single crystal semiconductor layer to each other with the above-described structure. Therefore, a single-crystal semiconductor layer with good crystallinity can be formed directly on the insulating substrate, and recrystallization treatment is unnecessary.

【0009】また、第2の半導体基板の主面にあらかじ
め所定パターンの酸化膜を形成しておけば、その酸化膜
を素子分離用の酸化膜として用いることができるととも
に、研摩の際のストッパーとして利用することができ
る。
If an oxide film having a predetermined pattern is previously formed on the main surface of the second semiconductor substrate, the oxide film can be used as an oxide film for element isolation and also as a stopper for polishing. Can be used.

【0010】[0010]

【実施例】以下に本発明の実施例を図面を参照して説明
する。図1は本発明の一実施例であるSOI構造の半導
体基板の製造方法を製造工程順に示す断面図である。
Embodiments of the present invention will be described below with reference to the drawings. 1A to 1D are cross-sectional views showing a method of manufacturing an SOI structure semiconductor substrate according to an embodiment of the present invention in the order of manufacturing steps.

【0011】まず、図1(a)に示すように、第1の半
導体シリコン基板1の表面上にCVD法によりSiO2
膜2を0.5〜2μm厚に形成する。この時、例えばP
2 5 やB2 3 を用いてリンまたはホウ素を4〜8w
t%混入させると、クラック等が入りにくくなるので好
ましい。また、CVD法の他熱酸化法でも所定の膜が形
成されればよいが、この場合は、1μm以上のSiO2
膜形成には長時間の熱処理が必要となるので、CVD法
の方が好ましい。
First, as shown in FIG. 1A, SiO 2 is formed on the surface of the first semiconductor silicon substrate 1 by the CVD method.
The film 2 is formed to have a thickness of 0.5 to 2 μm. At this time, for example, P
Phosphorus or boron 4 to 8 w using 2 O 5 or B 2 O 3
When t% is mixed, cracks are less likely to occur, which is preferable. A predetermined film may be formed by a thermal oxidation method other than the CVD method. In this case, SiO 2 having a thickness of 1 μm or more is used.
Since the film formation requires a long time heat treatment, the CVD method is preferable.

【0012】一方、図1(b)に示すように、第2の半
導体シリコン基板3上にシリコンのエピタキシャル膜4
を0.5〜2μm厚に成長させる。成長方法は、例えば
1150〜1200℃の高温度下でシラン(SiH4
の水素還元法による。
On the other hand, as shown in FIG. 1B, a silicon epitaxial film 4 is formed on the second semiconductor silicon substrate 3.
Are grown to a thickness of 0.5 to 2 μm. The growth method is, for example, silane (SiH 4 ) at a high temperature of 1150 to 1200 ° C.
Hydrogen reduction method.

【0013】次いで、図1(c)に示すように、第1の
半導体シリコン基板1と第2の半導体シリコン基板3と
を向かい合わせて、その主面どうしを貼り合わせ、10
00〜1200℃の高温下、水蒸気雰囲気中で熱処理し
て互いに接着する。
Then, as shown in FIG. 1C, the first semiconductor silicon substrate 1 and the second semiconductor silicon substrate 3 are opposed to each other, and their principal surfaces are bonded together.
Heat treatment is performed in a steam atmosphere at a high temperature of 00 to 1200 ° C. to bond them to each other.

【0014】しかる後、第2の半導体シリコン基板3を
その裏面側から機械的に研摩する。そして、第2の半導
体シリコン基板3が1〜2μm程度残っている状態で、
機械的研摩を止め、その後は、HF:HNO3 :CH3
COOH = 1:3:8の溶液によって溶解研摩す
る。これにより、図1(d)に示すように、シリコンエ
ピタキシャル膜4を露出させる。
After that, the second semiconductor silicon substrate 3 is mechanically polished from its back surface side. Then, in a state where the second semiconductor silicon substrate 3 remains about 1 to 2 μm,
After stopping mechanical polishing, HF: HNO 3 : CH 3
Dissolve polish with a solution of COOH = 1: 3: 8. As a result, the silicon epitaxial film 4 is exposed as shown in FIG.

【0015】以上のように構成することによって、Si
2 膜2の上に直接単結晶のシリコンエピタキシャル膜
4が形成されたSOI基板を得ることができる。
By configuring as described above, Si
It is possible to obtain an SOI substrate in which the single crystal silicon epitaxial film 4 is directly formed on the O 2 film 2.

【0016】図2に本発明の第2の実施例を示す。本実
施例においては、図2(a)に示すように、第2の半導
体シリコン基板3の周辺部に予め約2mm幅のSiO2
膜5を1〜2μm厚に形成しておく。このSiO2 膜5
の膜厚は、後に成長させるシリコンエピタキシャル膜の
膜厚に等しい膜厚とする。
FIG. 2 shows a second embodiment of the present invention. In this embodiment, as shown in FIG. 2 (a), SiO 2 having a width of about 2 mm is previously formed on the peripheral portion of the second semiconductor silicon substrate 3.
The film 5 is formed to have a thickness of 1 to 2 μm. This SiO 2 film 5
The film thickness of is equal to the film thickness of the silicon epitaxial film to be grown later.

【0017】次に、図2(b)に示すように、この第2
の半導体シリコン基板3の上のSiO2 膜5の部分を除
いた部分にのみ、選択エピタキシャル成長技術を用い
て、シリコンエピタキシャル膜4を成長させる。
Next, as shown in FIG.
The silicon epitaxial film 4 is grown only on the portion of the semiconductor silicon substrate 3 excluding the portion of the SiO 2 film 5 by using the selective epitaxial growth technique.

【0018】しかる後、図2(c)に示すように、上述
した第1の実施例と同様、この第2の半導体シリコン基
板3とSiO2 膜2を形成した第1の半導体シリコン基
板1とを互いに貼り合わせて、熱処理により接着する。
Thereafter, as shown in FIG. 2C, as in the case of the above-described first embodiment, the second semiconductor silicon substrate 3 and the first semiconductor silicon substrate 1 having the SiO 2 film 2 formed thereon are formed. Are bonded to each other and bonded by heat treatment.

【0019】そして、図2(d)に示すように、第2の
半導体シリコン基板3をその裏面側から研摩してシリコ
ンエピタキシャル膜4を露出させる。この時、SiO2
の研摩速度はシリコンに比較して小さいので、SiO2
膜5を研摩のストッパーとして利用することができ、従
って、シリコンエピタキシャル膜4の膜厚を精密に制御
することができる。
Then, as shown in FIG. 2D, the second semiconductor silicon substrate 3 is polished from the rear surface side to expose the silicon epitaxial film 4. At this time, SiO 2
Since the polishing rate of SiO 2 is smaller than that of silicon, SiO 2
The film 5 can be used as a stopper for polishing, so that the film thickness of the silicon epitaxial film 4 can be precisely controlled.

【0020】図3に本発明の第3の実施例を示す。本実
施例においては、図3(a)に示すように、第2の半導
体シリコン基板3の周辺部に研摩ストッパー用のSiO
2 膜5を形成する際、予め素子分離用のSiO2 膜6も
同時にパターン形成しておく。
FIG. 3 shows a third embodiment of the present invention. In this embodiment, as shown in FIG. 3A, SiO for a polishing stopper is formed on the peripheral portion of the second semiconductor silicon substrate 3.
When forming the 2 film 5, the SiO 2 film 6 for element isolation is also patterned in advance at the same time.

【0021】その後、第2の実施例と同様に工程を進め
ていくと、最終的に図3(d)に示すように、シリコン
エピタキシャル膜4に素子分離用のSiO2 部6が形成
されたSOI基板を得ることができる。
After that, when the steps were carried out in the same manner as in the second embodiment, finally, as shown in FIG. 3D, the SiO 2 portion 6 for element isolation was formed in the silicon epitaxial film 4. An SOI substrate can be obtained.

【0022】なお、本実施例のように素子分離用のSi
2 膜6を形成する場合には、このSiO2 膜6を研摩
ストッパーとしても用いることができるので、研摩スト
ッパー用のSiO2 膜5はあえて形成する必要はない。
しかしながら、研摩ストッパーは、第2の半導体シリコ
ン基板3の中央部のみに存在するよりは周辺部にあった
方が作業上有利であるので、SiO2 膜5を設ける方が
より好ましい。
As in the present embodiment, Si for element isolation is used.
When the O 2 film 6 is formed, the SiO 2 film 6 can also be used as a polishing stopper, so that it is not necessary to form the SiO 2 film 5 for the polishing stopper.
However, it is more advantageous in terms of work to have the polishing stopper in the peripheral portion of the second semiconductor silicon substrate 3 than in the central portion thereof. Therefore, it is more preferable to provide the SiO 2 film 5.

【0023】[0023]

【発明の効果】以上説明したように本発明によれば、絶
縁基板上に直接結晶性のよい半導体エピタキシャル層を
形成することができるので、簡単且つ確実な方法で、特
性の良い半導体積層基板を製造することができる。
As described above, according to the present invention, since a semiconductor epitaxial layer having good crystallinity can be formed directly on an insulating substrate, a semiconductor laminated substrate having excellent characteristics can be obtained by a simple and reliable method. It can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を示す半導体基板の製造
方法の工程順概略断面図である。
FIG. 1 is a schematic cross-sectional view in order of the steps of a method for manufacturing a semiconductor substrate, which shows a first embodiment of the present invention.

【図2】本発明の第2の実施例を示す半導体基板の製造
方法の工程順概略断面図である。
FIG. 2 is a schematic cross-sectional view in order of the steps of a method for manufacturing a semiconductor substrate showing a second embodiment of the present invention.

【図3】本発明の第3の実施例を示す半導体基板の製造
方法の工程順概略断面図である。
FIG. 3 is a schematic cross-sectional view in order of the steps of a method for manufacturing a semiconductor substrate showing a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 第1の半導体基板 2 酸化膜 3 第2の半導体基板 4 単結晶半導体層 5 酸化膜 6 酸化膜 1 First semiconductor substrate 2 oxide film 3 Second semiconductor substrate 4 Single crystal semiconductor layer 5 Oxide film 6 oxide film

Claims (10)

【特許請求の範囲】[Claims] 【請求項1】 第1面を有する第1の半導体基板の上記
第1面に酸化膜を形成する第1の工程と、第2面及びこ
の第2面の裏面である第3面とを有する第2の半導体基
板の上記第2面に単結晶の半導体層を形成する第2の工
程と、この第2の工程を経て上記第2面に単結晶の半導
体層が形成された上記第2の半導体基板と上記第1の工
程を経て酸化膜が形成された上記第1の半導体基板の上
記第1面とを貼り合わせる第3の工程と、この第3の工
程により貼り合わされた上記第2の半導体基板をその第
3面側から上記単結晶の半導体層が露出するまで研摩す
る第4の工程と、を有する半導体基板の製造方法。
1. A first step of forming an oxide film on the first surface of a first semiconductor substrate having a first surface, a second surface, and a third surface which is a back surface of the second surface. A second step of forming a single crystal semiconductor layer on the second surface of the second semiconductor substrate, and the second step of forming a single crystal semiconductor layer on the second surface through the second step. A third step of bonding the semiconductor substrate and the first surface of the first semiconductor substrate having the oxide film formed through the first step, and the second step of bonding by the third step. And a fourth step of polishing the semiconductor substrate from the third surface side thereof until the single crystal semiconductor layer is exposed.
【請求項2】 上記第2の工程はエピタキシャル成長法
により単結晶の半導体層を形成することを特徴とする請
求項第1項記載の半導体基板の製造方法。
2. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the second step, a single crystal semiconductor layer is formed by an epitaxial growth method.
【請求項3】 上記第2の半導体基板およびその第2面
に形成する単結晶の半導体層はシリコン材料で構成され
ることを特徴とする請求項第1項記載の半導体基板の製
造方法。
3. The method of manufacturing a semiconductor substrate according to claim 1, wherein the second semiconductor substrate and the single crystal semiconductor layer formed on the second surface of the second semiconductor substrate are made of a silicon material.
【請求項4】 上記第2の半導体基板の上記第2面に所
定パターンの酸化膜を形成する第5の工程を上記第2の
工程の前に有する請求項第1項記載の半導体基板の製造
方法。
4. The manufacturing of a semiconductor substrate according to claim 1, further comprising a fifth step of forming an oxide film having a predetermined pattern on the second surface of the second semiconductor substrate before the second step. Method.
【請求項5】 第2の工程は、上記第5の工程の後、上
記第2の半導体基板の上記第2面の酸化膜が形成されて
いない基板表面上に単結晶の半導体層を形成することを
特徴とする請求項第4項記載の半導体基板の製造方法。
5. In a second step, after the fifth step, a single-crystal semiconductor layer is formed on the surface of the second semiconductor substrate on which the oxide film of the second surface is not formed. The method of manufacturing a semiconductor substrate according to claim 4, wherein
【請求項6】 上記第2の工程はエピタキシャル成長法
により単結晶の半導体層を形成することを特徴とする請
求項第5項記載の半導体基板の製造方法。
6. The method of manufacturing a semiconductor substrate according to claim 5, wherein in the second step, a single crystal semiconductor layer is formed by an epitaxial growth method.
【請求項7】 上記第3の工程は熱処理を含むことを特
徴とする請求項第1項記載の半導体基板の製造方法。
7. The method of manufacturing a semiconductor substrate according to claim 1, wherein the third step includes heat treatment.
【請求項8】 上記熱処理は水蒸気雰囲気中で行うこと
を特徴とする請求項第7項記載の半導体基板の製造方
法。
8. The method of manufacturing a semiconductor substrate according to claim 7, wherein the heat treatment is performed in a steam atmosphere.
【請求項9】 上記熱処理は1000乃至1200℃の
温度範囲で行うことを特徴とする請求項第7項記載の半
導体基板の製造方法。
9. The method of manufacturing a semiconductor substrate according to claim 7, wherein the heat treatment is performed in a temperature range of 1000 to 1200 ° C.
【請求項10】 上記第4の工程は機械的研摩工程と、
それに続く溶液研摩工程とを含むことを特徴とする請求
項第1項記載の半導体基板の製造方法。
10. The fourth step comprises a mechanical polishing step,
The method of manufacturing a semiconductor substrate according to claim 1, further comprising a solution polishing step that follows.
JP27674291A 1990-09-28 1991-09-27 Manufacture of semiconductor substrate Withdrawn JPH056883A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27674291A JPH056883A (en) 1990-09-28 1991-09-27 Manufacture of semiconductor substrate

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP26066990 1990-09-28
JP2-260669 1990-09-28
JP27674291A JPH056883A (en) 1990-09-28 1991-09-27 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH056883A true JPH056883A (en) 1993-01-14

Family

ID=26544699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27674291A Withdrawn JPH056883A (en) 1990-09-28 1991-09-27 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPH056883A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0917193A1 (en) * 1997-11-10 1999-05-19 Nec Corporation Laminated SOI substrate and producing method thereof
WO2000033045A1 (en) * 1998-11-27 2000-06-08 Commissariat A L'energie Atomique Micromachined structure with deformable membrane and method for making same
JP2000331899A (en) * 1999-05-21 2000-11-30 Shin Etsu Handotai Co Ltd Method for forming soi wafer and soi wafer
US6427748B1 (en) 1998-07-27 2002-08-06 Canon Kabushiki Kaisha Sample processing apparatus and method
US6489654B2 (en) 1998-04-17 2002-12-03 Nec Corporation Silicon-on-insulator (SOI) substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0917193A1 (en) * 1997-11-10 1999-05-19 Nec Corporation Laminated SOI substrate and producing method thereof
US6323109B1 (en) 1997-11-10 2001-11-27 Nec Corporation Laminated SOI substrate and producing method thereof
US6489654B2 (en) 1998-04-17 2002-12-03 Nec Corporation Silicon-on-insulator (SOI) substrate
US6427748B1 (en) 1998-07-27 2002-08-06 Canon Kabushiki Kaisha Sample processing apparatus and method
US6609553B2 (en) 1998-07-27 2003-08-26 Canon Kabushiki Kaisha Sample processing apparatus and method
US6773534B2 (en) 1998-07-27 2004-08-10 Canon Kabushiki Kaisha Sample processing apparatus and method
WO2000033045A1 (en) * 1998-11-27 2000-06-08 Commissariat A L'energie Atomique Micromachined structure with deformable membrane and method for making same
JP2000331899A (en) * 1999-05-21 2000-11-30 Shin Etsu Handotai Co Ltd Method for forming soi wafer and soi wafer

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