JP2608443B2 - Method for manufacturing semiconductor wafer - Google Patents

Method for manufacturing semiconductor wafer

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Publication number
JP2608443B2
JP2608443B2 JP2286188A JP2286188A JP2608443B2 JP 2608443 B2 JP2608443 B2 JP 2608443B2 JP 2286188 A JP2286188 A JP 2286188A JP 2286188 A JP2286188 A JP 2286188A JP 2608443 B2 JP2608443 B2 JP 2608443B2
Authority
JP
Japan
Prior art keywords
wafer
film
silicon
silicon carbide
silicon substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2286188A
Other languages
Japanese (ja)
Other versions
JPH01199457A (en
Inventor
俊二 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
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Filing date
Publication date
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Priority to JP2286188A priority Critical patent/JP2608443B2/en
Publication of JPH01199457A publication Critical patent/JPH01199457A/en
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Anticipated expiration legal-status Critical
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Links

Description

【発明の詳細な説明】 〔概要〕 三次元集積回路装置を組み込むのに好適な多層構造を
有する半導体ウエハの製造方法に関し、 極めて簡単な手段で、大面積の多層構造を有し、且
つ、特性良好な半導体ウエハを容易に得られるようにす
ることを目的とし、 表面に絶縁膜が形成されている第一のウエハ及びシリ
コン基板表面に炭化珪素膜と絶縁膜とが順に形成されて
いる第二のウエハを該絶縁膜どうしが対向するよう貼り
合わせる工程と、次いで、前記第二のウエハに於ける前
記シリコン基板を除去して前記炭化珪素膜を表出させる
工程と、次いで、前記炭化珪素膜の表面に前記第二のウ
エハと同じ構造をもつ第三のウエハの絶縁膜側を対向し
て貼り合わせてから前記第三のウエハに於けるシリコン
基板を除去することで絶縁膜を介する炭化珪素膜の多層
構造を作成する工程とが含まれるよう構成する。
DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a semiconductor wafer having a multilayer structure suitable for incorporating a three-dimensional integrated circuit device. A first wafer having an insulating film formed on its surface and a second having a silicon carbide film and an insulating film formed in order on a silicon substrate surface for the purpose of easily obtaining a good semiconductor wafer. Bonding the wafers so that the insulating films face each other, and then removing the silicon substrate in the second wafer to expose the silicon carbide film, and then the silicon carbide film A third wafer having the same structure as the second wafer is bonded to the surface of the third wafer so as to face the insulating film, and then the silicon substrate in the third wafer is removed to form a silicon carbide layer through the insulating film. And forming a multilayer structure of the base film.

〔産業上の利用分野〕[Industrial applications]

本発明は、三次元集積回路装置を組み込むのに好適な
多層構造を有する半導体ウエハの製造方法に関する。
The present invention relates to a method for manufacturing a semiconductor wafer having a multilayer structure suitable for incorporating a three-dimensional integrated circuit device.

〔従来の技術〕[Conventional technology]

従来、単結晶半導体層と絶縁層とを交互に積層した半
導体ウエハを作成し、そのウエハに於ける各単結晶半導
体層に集積回路装置を組み込んで三次元集積回路装置と
する研究・開発が行われてきた。
Conventionally, research and development have been carried out by creating a semiconductor wafer in which single-crystal semiconductor layers and insulating layers are alternately stacked, and incorporating an integrated circuit device into each single-crystal semiconductor layer in the wafer to form a three-dimensional integrated circuit device. I have been.

その場合に用いられる半導体ウエハとしては、絶縁膜
上に多結晶シリコン層を形成し、その多結晶シリコン層
をレーザ・アニールに依って溶融して再結晶化すること
で単結晶層とし、これを繰り返すことで多層にした構造
のものが知られている。
The semiconductor wafer used in this case is to form a polycrystalline silicon layer on an insulating film, and then melt and recrystallize the polycrystalline silicon layer by laser annealing to form a single crystal layer. A structure having a multilayer structure by repeating is known.

〔発明が解決しようとする課題〕[Problems to be solved by the invention]

前記従来の技術に依った場合、ウエハ全面に亙り、良
質の単結晶層を形成することは甚だ困難であって、未だ
に実用の域に達していない。
According to the conventional technique, it is extremely difficult to form a high-quality single crystal layer over the entire surface of the wafer, and it has not yet reached a practical level.

本発明は、極めて簡単な手段で、大面積の多層構造を
有し、且つ、特性良好な半導体ウエハを容易に得られる
ようにする。
The present invention makes it possible to easily obtain a semiconductor wafer having a large-area multilayer structure and excellent characteristics by extremely simple means.

〔課題を解決するための手段〕[Means for solving the problem]

本発明に依る半導体ウエハの製造方法に於いては、表
面に絶縁膜(例えば二酸化シリコン膜2)が形成されて
いる第一のウエハ及びシリコン基板(例えばシリコン基
板4)表面に炭化珪素膜(例えば炭化珪素膜5)と絶縁
膜(例えば二酸化シリコン膜6)とが順に形成されてい
る第二のウエハを該絶縁膜どうしが対向するよう貼り合
わせる工程と、次いで、前記第二のウエハに於ける前記
シリコン基板を除去して前記炭化珪素膜を表出させる工
程と、次いで、前記炭化珪素膜の表面に前記第二のウエ
ハと同じ構造をもつ第三のウエハの絶縁膜側を対向して
貼り合わせてから前記第三のウエハに於けるシリコン基
板を除去することで絶縁膜を介する炭化珪素膜の多層構
造を作成する工程とが含まれている。
In the method for manufacturing a semiconductor wafer according to the present invention, a silicon carbide film (for example, a silicon wafer (for example, silicon dioxide film 2)) is formed on the surface of a first wafer having an insulating film (for example, silicon dioxide film 2) formed thereon. A step of bonding a second wafer on which a silicon carbide film 5) and an insulating film (for example, a silicon dioxide film 6) are sequentially formed so that the insulating films face each other; and then, in the second wafer, Removing the silicon substrate to expose the silicon carbide film, and then attaching an insulating film side of a third wafer having the same structure as that of the second wafer to a surface of the silicon carbide film so as to face each other. And removing the silicon substrate from the third wafer to form a multilayer structure of a silicon carbide film via an insulating film.

〔作用〕[Action]

前記手段を採ることに依り、大面積で且つ特性良好な
多層構造の半導体ウエハを完成された技術を適用して容
易に作成することができ、また、炭化珪素はシリコンに
比較してエネルギ・バンド・ギャップが広いので、耐熱
性良好な半導体装置を製造することができる。
By adopting the above-mentioned means, a semiconductor wafer having a multilayer structure having a large area and good characteristics can be easily formed by applying the completed technology, and silicon carbide has an energy band compared to silicon. -Since the gap is wide, a semiconductor device having good heat resistance can be manufactured.

〔実施例〕〔Example〕

第1図乃至第5図は本発明の一実施例を解説する為の
工程要所に於けるウエハの要部切断側面図を表し、以
下、これ等の図を参照しつつ説明する。
FIGS. 1 to 5 show cutaway side views of a main part of a wafer at important points in a process for explaining an embodiment of the present invention, and will be described with reference to these drawings.

第1図参照 (1) 化学気相成長(chemical vapor deposition:
CVD)法を適用することに依り、表面が平坦であって、
厚さが例えば600〔μm〕であるセラミック基板1に二
酸化シリコン(SiO2)膜2を厚さ例えば4000〔Å〕程度
に成長させる。
See Fig. 1. (1) Chemical vapor deposition:
By applying the CVD method, the surface is flat,
On a ceramic substrate 1 having a thickness of, for example, 600 [μm], a silicon dioxide (SiO 2 ) film 2 is grown to a thickness of, for example, about 4000 [Å].

尚、セラミック基板1はシリコン・エッチング液でエ
ッチングされ難く、且つ、耐熱性が高い材料の基板に代
替することができ、例えば、全面を窒化シリコン(Si3N
4)膜で被覆したシリコン基板であっても良い。
Incidentally, the ceramic substrate 1 is hardly etched with a silicon etch solution, and can be replaced with a substrate of high heat resistant material, for example, the whole surface of silicon nitride (Si 3 N
4 ) A silicon substrate coated with a film may be used.

(2) 引き続きCVD法を適用することに依り、硼素・
燐・珪酸ガラス(boron phosp harus silicate gla
ss:BPSG)膜3を厚さ例えば1000〔Å〕程度に成長させ
る。
(2) By continuing to apply the CVD method, boron
Phosphorus silicate glass (boron phosp harus silicate gla
ss: BPSG) The film 3 is grown to a thickness of, for example, about 1000 [Å].

前記のようにして作成したウエハを第一のウエハと呼
ぶことにする。
The wafer prepared as described above is referred to as a first wafer.

第2図参照 (3) 源圧気相エピタキシャル成長(low pressure
vapor phase epitaxy:low pressure VPE)法を適
用することに依り、シリコン基板4上に厚さ例えば2000
〔Å〕程度の炭化珪素(silicon carbide:SiC)膜5を
成長させる。
See Fig. 2. (3) Low pressure gas phase epitaxial growth (low pressure)
By applying a vapor phase epitaxy (low pressure VPE) method, a thickness of, for example, 2000
[Å] A silicon carbide (SiC) film 5 of a degree is grown.

(4) 引き続きCVD法を適用することに依り、厚さ例
えば4000〔Å〕程度のSiO2膜6と厚さ例えば1000〔Å〕
程度のBPSG膜7を順に成長させる。
(4) By continuously applying the CVD method, an SiO 2 film 6 having a thickness of, for example, about 4000 [Å] and a thickness of, for example, 1000 [Å] are obtained.
BPSG films 7 are sequentially grown.

前記のようにして作成したウエハを第二のウエハと呼
ぶことにする。
The wafer prepared as described above is referred to as a second wafer.

第3図参照 (5) 第一のウエハ表面、即ち、BPSG膜3の表面と、
第二のウエハ表面、即ち、BPSG膜7の表面とを衝合し、
熱処理を行ってBPSG膜3及び7の溶融結合を行って第一
のウエハと第2のウエハを貼り合わせる。
See FIG. 3. (5) The first wafer surface, that is, the surface of the BPSG film 3,
Abut the second wafer surface, that is, the surface of the BPSG film 7;
The first wafer and the second wafer are bonded by performing a heat treatment to perform a fusion bonding of the BPSG films 3 and 7.

この場合の熱処理温度は、BPSG膜3及び7に含有され
ている不純物の濃度に依っても異なるが、400〔℃〕〜1
000〔℃〕の範囲で適宜に選択して実施する。
The heat treatment temperature in this case varies depending on the concentration of the impurities contained in the BPSG films 3 and 7;
The temperature is appropriately selected within the range of 000 [° C.].

ここで重要なことは、BPSG膜3及び7は熱処理されて
いる間に、含有していた燐(P)及び硼素(B)の一部
をSiO2膜2及び6中に放出することであり、それに依っ
て融点は高くなってしまい、前記熱処理では低い温度で
容易に溶融されたが、貼り合わせ加工した後は、その時
よりも更に高い温度にしないと溶融しない。これは、更
に多層の貼り合わせ加工を行う場合、或いは、後に半導
体装置を作り込む為の諸熱処理を行う上で大変有利なこ
とである。
What is important here is that the BPSG films 3 and 7 release part of the phosphorus (P) and boron (B) contained therein into the SiO 2 films 2 and 6 during the heat treatment. Due to this, the melting point becomes high, and it was easily melted at a low temperature by the heat treatment, but after the lamination process, it did not melt unless the temperature was further increased than at that time. This is very advantageous when performing a multi-layer bonding process or performing various heat treatments for fabricating a semiconductor device later.

第4図参照 (6) KOH或いはHF+HNO3など、シリコン・エッチン
グ液中に浸漬し、シリコン基板4を除去し、SiC膜5を
表出させる。
See FIG. 4. (6) The silicon substrate 4 is removed by immersion in a silicon etching solution such as KOH or HF + HNO 3 to expose the SiC film 5.

この場合、セラミック基板1はエッチングされずに残
ることは云うまでもない。
In this case, it goes without saying that the ceramic substrate 1 remains without being etched.

第5図参照 (7) この後、SiC膜5の表面に前記説明した第二の
ウエハと同じ構造をもつ第三のウエハのSiO2膜6側を対
向して貼り合わせ、第三のウエハに於けるシリコン基板
4を除去することで、図示のように、BPSG膜7及びSiO2
膜6を介してSiC膜5が多層に形成される。このような
工程を繰り返すことで、必要とされる層数の多層構造を
有する半導体ウエハが得られる。
See FIG. 5 (7) Thereafter, the SiO 2 film 6 side of a third wafer having the same structure as that of the above-described second wafer is bonded to the surface of the SiC film 5 so as to face each other, and is bonded to the third wafer. By removing the silicon substrate 4 in the BPSG film 7 and the SiO 2
The SiC film 5 is formed in multiple layers via the film 6. By repeating such steps, a semiconductor wafer having a required number of layers and a multilayer structure can be obtained.

尚、第二層目のSiC膜5を形成する工程に入る前に第
一層目のSiC膜5に所要の加工を施したり、或いは、諸
素子やその一部を作り込むなどは任意であり、また、必
要とされる多層構造が完成された後、例えば温度1000
〔℃〕〜1150〔℃〕程度の熱処理を行えば、BPSG膜3及
び7中の硼素及び燐は更にSiO2膜2及び6中に拡散して
平均化されて融点は高くなるので、後の工程の為には好
ましい状態となる。
Before the step of forming the second-layer SiC film 5, it is optional to perform necessary processing on the first-layer SiC film 5 or to form various elements and parts thereof. Also, after the required multilayer structure is completed, for example, at a temperature of 1000
If a heat treatment of about [° C.] to about 1150 ° C. is performed, boron and phosphorus in the BPSG films 3 and 7 are further diffused into the SiO 2 films 2 and 6 and averaged to increase the melting point. It is in a favorable state for the process.

第6図乃至第10図は他の実施例を解説する為の工程要
所に於けるウエハの要部切断側面図を表し、以下、これ
等の図を参照しつつ説明する。
FIGS. 6 to 10 show side views of essential parts of a wafer at process steps for explaining another embodiment, which will be described below with reference to these figures.

第6図参照 (1) CVD法を適用することに依り、さきの実施例で
採用されたものと同じセラミック基板1にSiO2膜2を厚
さ例えば1000〔Å〕程度に成長させる。
See FIG. 6. (1) By applying the CVD method, an SiO 2 film 2 is grown to a thickness of, for example, about 1000 [Å] on the same ceramic substrate 1 as that employed in the previous embodiment.

尚、基板1の構成材料がセラミックに限定されるもの
ではないことは前記した通りであり、また、このウエハ
を第一のウエハとすることも前記実施例と同じである。
It is to be noted that the constituent material of the substrate 1 is not limited to ceramic as described above, and that this wafer is used as the first wafer in the same manner as in the above embodiment.

第7図参照 (2) 源圧VPE法を適用することに依り、シリコン基
板4上に厚さ例えば2000〔Å〕程度のSiC膜5を成長さ
せる。
See FIG. 7 (2) By applying the source pressure VPE method, a SiC film 5 having a thickness of, for example, about 2000 [Å] is grown on the silicon substrate 4.

(3) 引き続きCVD法を適用することに依り、厚さ例
えば1000〔Å〕程度のSiO2膜6を成長させる。
(3) The SiO 2 film 6 having a thickness of, for example, about 1000 [Å] is grown by continuously applying the CVD method.

このようにして作成したウエハが第二のウエハである
ことは勿論である。
Of course, the wafer created in this way is the second wafer.

第8図参照 (4) 第一のウエハ表面、即ち、SiO2膜2の表面と、
第二のウエハ表面、即ち、SiO2膜6の表面に親水性処理
を施してから衝合し、乾燥窒素(N2)雰囲気中にて、温
度を例えば1000〔℃〕程度とし、時間を例えば30〔分〕
程度とする熱処理を行うことで第一のウエハと第2のウ
エハを貼り合わせる。
See FIG. 8 (4) The surface of the first wafer, that is, the surface of the SiO 2 film 2,
The surface of the second wafer, that is, the surface of the SiO 2 film 6 is subjected to a hydrophilic treatment and then abutted. In a dry nitrogen (N 2 ) atmosphere, the temperature is set to, for example, about 1000 ° C., and the time is set to, for example, Half an hour〕
The first wafer and the second wafer are bonded to each other by performing a heat treatment to a degree.

このようにして貼り合わせた第一のウエハと第二のウ
エハとの結合は大変強力であり、剥離することはない。
The bonding between the first wafer and the second wafer thus bonded is very strong and does not peel off.

第9図参照 (5) KOH或いはHF+HNO3など、シリコン・エッチン
グ液中に浸漬し、シリコン基板4を除去し、SiC膜5を
表出させる。
See FIG. 9 (5) The silicon substrate 4 is removed by immersion in a silicon etching solution such as KOH or HF + HNO 3 to expose the SiC film 5.

第10図参照 (7) この後、SiC膜5の表面に前記説明した第二の
ウエハと同じ構造をもつ第三のウエハのSiO2膜6側を対
向して貼り合わせ、第三のウエハに於けるシリコン基板
4を除去することで、図示のように、SiO2膜6を介して
SiC膜5が多層に形成される。このような工程を繰り返
すことで、必要とされる層数の多層構造を有する半導体
ウエハが得られる。
See FIG. 10 (7) Thereafter, the SiO 2 film 6 side of the third wafer having the same structure as the above-described second wafer is bonded to the surface of the SiC film 5 so as to face each other, and the third wafer is bonded to the third wafer. by removing in the silicon substrate 4, as shown, through the SiO 2 film 6
The SiC film 5 is formed in multiple layers. By repeating such steps, a semiconductor wafer having a required number of layers and a multilayer structure can be obtained.

〔発明の効果〕〔The invention's effect〕

本発明に依る半導体ウエハの製造方法に於いては、表
面に絶縁膜が形成されている第一のウエハ及びシリコン
基板表面に炭化珪素膜と絶縁膜とが順に形成されている
第二のウエハを貼り合わせ、前記第二のウエハに於ける
前記シリコン基板を除去して前記炭化珪素膜を表出さ
せ、その炭化珪素膜の表面に前記第二のウエハと同じ構
造をもつ第三のウエハの絶縁膜側を対向して貼り合わせ
てから前記第三のウエハに於けるシリコン基板を除去
し、これを繰り返すことで絶縁膜を介する炭化珪素膜の
多層構造を得るようにしている。
In the method of manufacturing a semiconductor wafer according to the present invention, a first wafer having an insulating film formed on a surface thereof and a second wafer having a silicon carbide film and an insulating film formed in order on a silicon substrate surface are formed. Affixing, removing the silicon substrate in the second wafer to expose the silicon carbide film, and insulating the third wafer having the same structure as the second wafer on the surface of the silicon carbide film After laminating the film sides facing each other, the silicon substrate in the third wafer is removed, and this is repeated to obtain a multilayer structure of a silicon carbide film via an insulating film.

前記構成を採ることに依り、大面積で且つ特性良好な
多層構造の半導体ウエハを完成された技術を適用して容
易に作成することができ、また、炭化珪素はシリコンに
比較してエネルギ・バンド・ギャップが広いので、耐熱
性良好な半導体装置を製造することができる。
By adopting the above-described structure, a semiconductor wafer having a large area and a multilayer structure having good characteristics can be easily formed by applying the completed technology, and silicon carbide has an energy band compared to silicon. -Since the gap is wide, a semiconductor device having good heat resistance can be manufactured.

【図面の簡単な説明】[Brief description of the drawings]

第1図乃至第5図は本発明一実施例を説明する為の工程
要所に於けるウエハの要部切断側面図、第6図乃至第10
図は他の実施例を説明する為の工程要所に於けるウエハ
の要部切断側面図をそれぞれ表している。 図に於いて、1はセラミック基板、2はSiO2膜、3はBP
SG膜、4はシリコン基板、5はSiC膜、6はSiO2膜、7
はBPSG膜をそれぞれ示している。
FIGS. 1 to 5 are cutaway side views of a main part of a wafer in important parts of a process for explaining an embodiment of the present invention, and FIGS.
The drawings respectively show a cross-sectional side view of a main part of a wafer at a process point for explaining another embodiment. In the figure, 1 is a ceramic substrate, 2 is a SiO 2 film, 3 is BP
SG film, 4 is a silicon substrate, 5 is a SiC film, 6 is a SiO 2 film, 7
Indicates a BPSG film, respectively.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】表面に絶縁膜が形成されている第一のウエ
ハ及びシリコン基板表面に炭化珪素膜と絶縁膜とが順に
形成されている第二のウエハを該絶縁膜どうしが対向す
るよう貼り合わせる工程と、 次いで、前記第二のウエハに於ける前記シリコン基板を
除去して前記炭化珪素膜を表出させる工程と、 次いで、前記炭化珪素膜の表面に前記第二のウエハと同
じ構造をもつ第三のウエハの絶縁膜側を対向して貼り合
わせてから前記第三のウエハに於けるシリコン基板を除
去することで絶縁膜を介する炭化珪素膜の多層構造を作
成する工程と が含まれてなることを特徴とする半導体ウエハの製造方
法。
1. A first wafer having an insulating film formed on a surface thereof and a second wafer having a silicon carbide film and an insulating film formed on a silicon substrate surface in this order so that the insulating films face each other. Combining, then, removing the silicon substrate in the second wafer to expose the silicon carbide film, and then forming the same structure as the second wafer on the surface of the silicon carbide film. Forming a multilayer structure of a silicon carbide film with an insulating film interposed therebetween by removing the silicon substrate in the third wafer after bonding the insulating film side of the third wafer so as to face each other. A method for manufacturing a semiconductor wafer, comprising:
JP2286188A 1988-02-04 1988-02-04 Method for manufacturing semiconductor wafer Expired - Lifetime JP2608443B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2286188A JP2608443B2 (en) 1988-02-04 1988-02-04 Method for manufacturing semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2286188A JP2608443B2 (en) 1988-02-04 1988-02-04 Method for manufacturing semiconductor wafer

Publications (2)

Publication Number Publication Date
JPH01199457A JPH01199457A (en) 1989-08-10
JP2608443B2 true JP2608443B2 (en) 1997-05-07

Family

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Country Status (1)

Country Link
JP (1) JP2608443B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04365377A (en) * 1991-06-13 1992-12-17 Agency Of Ind Science & Technol Semiconductor device

Also Published As

Publication number Publication date
JPH01199457A (en) 1989-08-10

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