JPH0341719A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To obtain a high-quality III-V compound semiconductor layer without cracks and defects on an Si substrate by laminating an insulating film and a thin Si layer on a substrate, and growing a III-V compound semiconductor on said laminated layers. CONSTITUTION:A BPSG film 2 is formed on the main surface of an Si substrate 1 by a plasma CVD method. Then, a substrate 6 is otherwise prepared by laminating a BPSG film 5 on the surface of a second substrate 4 made of molybdenum by a plasma CVD method in addition to the substrate 3. Thereafter, both substrates (3 and 6) are bonded at a specified temperature by using the BPSG films 2 and 5. The Si substrate 1 is made to be the thin layer by mechanical chemical etching method. The Si substrate on the molybdenum substrate 4 is set in an MBE apparatus. A GaAs film 8 is grown by so-called two-stage growing method. Since most of thermal stress is alleviated with the Si layer 1, the high-quality GaAs is obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor substrate, particularly silicon (
81) This relates to a method for manufacturing an m-v group compound semiconductor substrate for obtaining a single crystal of a -V group compound semiconductor such as GaAs on a substrate.

[Conventional technology]

Compound semiconductors such as GaAs and InP are being utilized for high performance, high functionality, and high performance devices by taking advantage of their excellent characteristics. However, compound semiconductors are generally expensive,
There are problems such as difficulty in obtaining a high-quality substrate crystal with a large area. In an attempt to overcome these problems, we have developed a product that is inexpensive, high quality, and lightweight.

Attempts have been made to use a large silicon substrate as a substrate, stack compound semiconductors on the silicon substrate, and manufacture devices using the compound semiconductor layers. Although several methods for manufacturing compound semiconductor substrates using such silicon substrates have been proposed in the past, they are still inferior to bulk crystals in terms of crystal quality.

The reason for this is that the thermal expansion coefficient and lattice constant of the ■-■ group semiconductor are different from those of silicon. In particular, thermal stress based on the difference in thermal expansion coefficients of 10'dyn/- or more is the main cause of defects and cracks.

That is, when cooling is started after growing a GaAs layer on a Si substrate at a growth temperature T, the thermal expansion coefficient α of the 81 substrate is
The stress σT1 based on the difference between si and the thermal expansion coefficient αo1^ of GaAa, that is, σT=(αGAB−α5t)−(T,−T)−E/(
1-y) occurs. This stress is unavoidable as long as Sl and GaAs are in close contact with each other, and is alleviated by introducing cracks and defects into the GaAs layer, which is thinner than the 81 substrate.

In order to solve this problem, a method for manufacturing a 2-V group compound semiconductor substrate has been proposed in which a layer for reducing the difference in thermal expansion coefficient is inserted between the 1-V group semiconductor layer and the substrate.

For example, there is a method in which a low melting point material layer is interposed between the ■-V group semiconductor and a substrate such as Si or glass. Unexamined Japanese Patent Publication 1986
According to 2669, there is a structure in which Sn + Gar In is interposed between the solar cell layer and a substrate made of St, glass, metal, etc., or a structure in which Ge single crystal is used as a substitute for the solar cell layer, and shows a method for growing ■-v crystals.

Another method is to laminate and integrate a plurality of semiconductor substrates of different types. Japanese Patent Publication No. 61-1822
15, InP is placed on a St substrate and GaAs is placed on top of it.
A method is shown in which they are placed next to each other, their mirror surfaces are brought into close contact with each other, and heat treated to integrate them.

Furthermore, in JP-A No. 61-219182, a highly concentrated impurity layer is formed on a silicon substrate, Si is formed on the layer, and crystals are further grown, and then the S1 substrate is chemically etched. A large area can be achieved by stopping etching with a highly concentrated impurity layer.

A method for obtaining lightweight compound semiconductors is shown.

[Problem to be solved by the invention]

However, in the method of JP-A-62-2669 mentioned above, since the solar cell layer is produced and then attached to the substrate, its area is limited to the size of the ■-■ group substrate (4 inches or less in diameter). Ensemble. In addition, in the method of pasting the Go layer, Go is S
Since a crystal with a large total area compared to t cannot usually be obtained, there is a problem similar to that described above.

Furthermore, in the method of JP-A-61-182215, the difference in thermal expansion coefficient between adjacent materials is 2×lO″″6 de g −
Since it is non-Z and the bonding temperature is at most 200°C, it has the advantage of greatly easing thermal distortion, but its size is limited to the size of ■-V group compound semiconductors. Ga
Since IInP, which is more expensive than Aa, is used in the middle, it is not economical.

Furthermore, in the method of JP-A-61-219182, since the compound semiconductor is grown on a thick silicon substrate,
It has no effect of reducing thermal strain and has no effect on improving the quality of compound semiconductors.

The present invention has been made in view of the above points, and its purpose is to provide high quality m-v without cracks or defects on the 81 board.
An object of the present invention is to provide a method for manufacturing a semiconductor substrate that allows growth of a group compound semiconductor layer.

[Means to solve the problem]

In order to achieve the above object, the present invention forms a substrate by adhering a first substrate made of 31 to a second substrate with an insulating film interposed, and then a thin layer of this first Si substrate. The main feature is that after the thinning of the 81 layer, an m-v group compound semiconductor is grown on the thinned 81 layer.

[Effect]

In the present invention, by growing a ■-V group compound semiconductor on a laminated insulating film and a thin St layer on a substrate, a high-quality product without cracks or defects can be formed on the substrate. −
A V group compound semiconductor layer can be obtained.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1(d) to 1(d) are cross-sectional views showing the manufacturing process of a semiconductor substrate according to a first embodiment of the present invention.

First, an Sl substrate 1 whose main semiconductor surface is an (ioo) plane is prepared. Next, plasma CVD is applied onto the main surface of this Sl substrate 1.
A 5BPSG film 2 is formed by method D to produce a first substrate 3. Next, apart from this substrate 3, a second substrate made of molybdenum is installed.
Prepare a substrate 6 with a pBPSG film 5 laminated on the surface of the substrate 4 by plasma CVD method (Fig. Adhesion is achieved by temperature (Fig. 1(b)). However, 7 in the figure indicates npsai after adhesion.

Next, the Si substrate 1 is etched to a thickness of 1 μm using a mechanical chemical etching method. ! (Fig. 1 (C)).

The 81 substrate on the molybdenum substrate 4 produced in this way was set in an MBE apparatus, and the so-called two-step growth method (consisting of low-temperature growth at about 350°C and high-temperature growth at about 600°C) was performed.
A GaAs film 8 was grown to a thickness of about 3 μm.

FIG. 1(d) shows the structure of the semiconductor substrate thus obtained.

The stress in the GaAs layer 8 thus obtained is such that the amount of shift in the peak wavelength of photoluminescence is 2 x 1
It was estimated to be 0' dyn/-. Conventional GaA
It can be seen that this decreases compared to s/Si (approximately 2 x 10' dyn/cJ). From etching with molten KOH, the niche e-bit density (EPD) is approximately 2X105
It is estimated that 8
A film of much higher quality was obtained than that of GaAs on a single substrate. In the conventional method, GaAs is grown when the Si substrate is thick.
Because the thermal stress was growing on the thin GaAs sub-substrate
This was alleviated by introducing defects into the layer.

In contrast, in the present invention, most of the thermal stress is alleviated by the thin Si substrate, one SiSt layer, one GaAs layer 8, and the other is thinner than molybdenum, which has a coefficient of thermal expansion close to that of GaAa. This is probably why high quality GaAs was obtained.

FIGS. 2(a) to (41) are cross-sectional views showing the manufacturing process of a semiconductor substrate according to a second embodiment of the present invention.

First, an 81 substrate 9 whose main semiconductor surface is a (100) plane is prepared. Next, on the main surface of this Si substrate 9, an ion implantation method (implantation energy: 40 eV, implantation amount: I
0"cm""2, annealing temperature: 1100° C., annealing time: 3 layers m), the p + boron doped layer 10 is set so that the impurity concentration at a depth of 1 μm from the surface is 1020CWL""3 or more. (Fig. 2(a)).

Next, plasma C is applied onto this p+ boron doped layer 10.
After forming one PSG film and one film tube by the VD method, psGMl 4 was deposited on the surface of a second substrate 13 made of sapphire (thermal expansion coefficient 6.5 x 10-6°C-1) separately from the substrate 12.
Prepare the substrate 15 laminated by the plasma CVD method (FIG. 2(b)'), and bond both (12 and 15) using the PSG film 1 film tube 14 (FIG. 2(C)). However, 16 in the figure indicates psag after adhesion.

Next, a portion of the substrate 12 other than the p-middle layer 10 (Si substrate 9)
Remove it by etching and make it a thin layer. This method is
A thin layer was formed by mechanical polishing to a film thickness of about 10 μm, and then an alkaline mixed solution with a composition ratio of 17 ml of ethylenediamine, 3 g of pitecatechol, and 8 ml of water was poured into a thin layer with a thickness of about 10 μm.
The one heated to 0°C was used. This mixture is p-,
The etching rate for one layer of n'''' or n''s is more than 500 times higher than that of p+ with a boron concentration of 1020 crn''''3 or more, and the etching rate is more than 500 times higher than that of p+ with a boron concentration of 1020 crn''3 or more. (FIG. 2(d)).

St on the sapphire substrate 13 produced in this way
The substrate was set in an MOCVD apparatus, and a GaAs film 11 of about 5 μm was grown by a so-called two-step growth method (consisting of low-temperature growth at about 400° C. and high-temperature growth at about 700° C.).

FIG. 2(,) shows the structure of the semiconductor substrate thus obtained.

The stress in the GaAs layer 1T obtained in this way is such that the shift amount of the peak wavelength of photoluminescence is 108
It was estimated to be dyn/-. Conventional GaAs/S
It can be seen that this decreases compared to i (approximately 2X 10'dyn/cII). From etching with molten KOJI, the niche pit density (EPD) is approximately 1×105α″
S is estimated to be 2 and obtained with this 1! G on the board
A film of much higher quality than aAs was obtained. In the conventional method, GaA3 was grown on a thick Si substrate, so the thermal stress was alleviated by introducing defects into the GaAs layer as thin as the 81 substrate.
The first layer 10 is thinner than the GaAs layer 1T and sapphire whose coefficient of thermal expansion is close to that of GaAs, and most of the thermal stress is p+.
Since the st layer 10 is relaxed, high quality GaAs
It is thought that this was obtained.

3(a) to 3(f) are cross-sectional views showing the manufacturing process of a semiconductor substrate according to a third embodiment of the present invention.

First, a Si substrate 18 whose main semiconductor surface is an (ioo) plane is prepared. Next, on the main surface of the Si substrate 1B, an ion implantation method (implantation energy: 40 eV % implantation amount:
A p+ boron doped layer 19 is formed so that the impurity concentration at a depth of 1 μm from the surface is 1020 cm''3 or more (annealing temperature: 1100° C., annealing time: 30=). Figure 3 (&
)).

Next, on this p+ boron doped layer 19, a plasma C
After forming 9 PSG films 20 by the VD method, a PSG film was formed on the surface of a second substrate 22 made of alumina single crystal (thermal expansion coefficient 4.6×10″″6°C-1) separately from the substrate 21. Prepare a substrate 24 on which 23 is laminated by plasma CVD method (Fig. 3(b)), and PSG both (21 and 24).
Bonding is performed using films 20 and 23 (FIG. 3(C)).

However, 25 in the figure indicates the PSG film after adhesion.

Next, a portion of the substrate 21 other than the p-layer 19 (the Si substrate 18
) is removed by etching to make it a thin layer. In this method, first, a film thickness of about 10 μm is made into a thin layer by mechanical polishing, and then 17 ml of ethylenediamine. 1 1 of an alkaline mixture with a composition ratio of 3 g of pitecatechol and 8 ml of water.
The one heated to 00°C was used. This mixture is p-
, n- or n''81 layer, the etching rate is
50 to 10 with a boron concentration of 1020 cm-3 or more
Since it is larger than 0 times and has selectivity, a structure having a p+Si layer 19 of 1 μm with excellent film thickness uniformity can be obtained (FIG. 3(d)).

Next, this substrate was heated with humidified oxygen at 1000°C (wet 02
) Oxidize in atmosphere for about 12 hours. Under these oxidation conditions,
A 5io2 film 26 with a thickness of 1 μm is formed (Fig. 3(e)
)). As is well known, when 81 is oxidized, the film becomes about twice as thick.
In this example, a Si layer of approximately 0.5 μm is required to form a Si layer of 0.5 μm in thickness.
There are 9 left. Here, p+s shown in FIG. 3(d)
Step of obtaining the i-layer 19 and 810 shown in FIG.
By changing the conditions of the process for obtaining the two-layer film 26, the structure shown in FIG.

Next, after removing the SIO film 26 by etching, the S1 substrate on the alumina single crystal substrate 22 is set in an MOCVD apparatus, and the so-called two-step growth method (low-temperature growth at about 350°C and high-temperature growth at about 600°C) is performed. (consisting of growth) YoFi
It was grown to a thickness of 75 μm on two InP films. FIG. 3(f) shows the structure of the semiconductor substrate thus obtained. At this time,
By providing a step of oxidizing a part of the p+Si layer 19 and removing the 5i02 film 26 when forming the nP film 27, the flatness of the Sp"S 3 layer 19 is good, and the p+33 The concentration of layer 19 can be controlled.

The stress in InPIJ2T obtained in this way is such that the shift amount of the peak wavelength of photoluminescence is 108 d.
It was estimated to be less than yn/-. Conventional InP/S
t (approximately 10'dyn/d). From etching with H3PO4 + HBr, the etch bit density (EPD) is estimated to be about 1×105×2″2, which is the InP on the Sl substrate obtained in 1.
A film of much higher quality was obtained compared to the conventional method. In the conventional method, InP was grown on a thick Si substrate, so the thermal stress was alleviated by introducing defects into the llxP layer, which is thinner than the 81 substrate. It is considered that high quality InP was obtained because the layer 2γ and the thermal expansion coefficient were thinner than alumina, which is close to InP, and most of the thermal stress was relaxed in the p+si layer 19.

In addition to this example, a ceramic substrate, a metal substrate, a glass substrate, a semiconductor substrate, etc. were used as the second substrate, and similar results were obtained.

〔Effect of the invention〕

As explained above, according to the present invention, a first substrate made of SL is bonded to a second substrate with an insulating film interposed to form a substrate, and the first Si substrate is thinned. after,
When the ■-V group compound semiconductor is grown on this thinned St layer, the stress caused by the difference in thermal expansion coefficient is absorbed by the Si substrate, so that heat is generated in the ■-V group compound semiconductor layer. A high quality m-v group compound semiconductor layer free of defects such as dislocations caused by stress can be obtained. Since glass, metal, ceramics, single crystal substrates, etc. can be used for the casing and the second substrate, it is possible to obtain an inexpensive, large-area m-V group compound semiconductor substrate, which is highly effective. There is.

[Brief explanation of drawings]

FIGS. 1(&) to (d) are sectional views showing the manufacturing process of a semiconductor substrate according to the first embodiment of the present invention, and FIGS. 2(,) to (,
) is a cross-sectional view showing the manufacturing process of a semiconductor substrate according to the second embodiment of the present invention, and FIGS. 3(a) to (f) are cross-sectional views showing the manufacturing process of the semiconductor substrate according to the third example of the present invention. It is. 1...Sl substrate, 2,5. γ...BPSG film,
3...first substrate, 4...molybdenum substrate, 6
・・◆・Substrate, 8...Ga As M % 9
...Si substrate, 10...p+ boron doped layer,
11, 14, 16...PSGi, number 12...
First substrate, 13-... Sapphire substrate, 15se*
s substrate, 17 e...* GaAs film, 18...
Si substrate, 1 layer, 20.23, 25...first substrate, 22...substrate, 26...InP film. 9...p+ boron doe...PSG film, 21...alumina substrate, 24...3102 film, 27...

Claims (3)

[Claims] (1) A first step of bonding a first substrate made of silicon to a second substrate with an insulating film interposed therebetween to form a substrate, and a second step of thinning the first substrate. and a third step of growing a III-V compound semiconductor on the thinned silicon layer. (2) In claim 1, in the first step, a highly concentrated impurity doped layer is formed on the main surface of the first substrate made of silicon, and an insulating film is interposed on the highly concentrated impurity doped layer and bonded. A method for manufacturing a semiconductor substrate, the second step including a step of selectively removing a silicon portion other than the heavily doped layer. (3) The method of manufacturing a semiconductor substrate according to claim 1, wherein the second step includes a step of oxidizing a part of the silicon layer and removing the oxidized layer.