JPH05226463A - Manufacture of joined dielectric isolation wafer - Google Patents

Manufacture of joined dielectric isolation wafer

Info

Publication number
JPH05226463A
JPH05226463A JP2414492A JP2414492A JPH05226463A JP H05226463 A JPH05226463 A JP H05226463A JP 2414492 A JP2414492 A JP 2414492A JP 2414492 A JP2414492 A JP 2414492A JP H05226463 A JPH05226463 A JP H05226463A
Authority
JP
Japan
Prior art keywords
wafer
temperature polysilicon
polysilicon film
high temperature
polysilicon layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2414492A
Other languages
Japanese (ja)
Inventor
Shinsuke Sakai
慎介 酒井
Takanori Ohata
孝紀 大圃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Silicon Corp
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Silicon Corp, Mitsubishi Materials Corp filed Critical Mitsubishi Materials Silicon Corp
Priority to JP2414492A priority Critical patent/JPH05226463A/en
Publication of JPH05226463A publication Critical patent/JPH05226463A/en
Pending legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To eliminate level differences generated on the polished surface of a high temperature polysilicon film with a low temperature polysilicon film and to enhance a jointed surface in adhesive strength by a method wherein a polysilicon film is formed on a mirror-polished high temperature polysilicon layer through a low temperature CVD method. CONSTITUTION:An oxide film 12 is formed on the surface 11a of a silicon wafer 11 where a dielectric isolating groove has been formed, and a polysilicon layer 13 is successively provided thereon through a high temaperature CVD method and subjected to cutting work and mirror-polishing work. A polysilicon film 15 is formed on the high temperature polysilicon layer 14 through a low temperature CVD method and subjected to mirror-polishing work. The low temperature polysilicon film 16 is jointed on the surface 17a of a support silicon wafer 17 together. By this setup, level differences generated in a jointed surface between the silicon wafers 17 and 11 can be removed, and the wafers 11 and 17 can be enhanced in pasting strength. Therefore, air bubbles generated in a jointed surface can be lessened.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、貼り合わせ面の段差を
低減させ、該貼り合わせ面の貼り合わせ強度を向上させ
ることのできる貼り合わせ誘電体分離ウェーハの製造方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bonded dielectric separated wafer which can reduce the step difference of the bonded surface and improve the bonding strength of the bonded surface.

【0002】[0002]

【従来の技術】従来、シリコンウェーハの表面に、誘電
体分離用溝を形成した後に酸化膜絶縁膜を成膜し、この
絶縁膜上に高温CVDによりポリシリコンをウェーハの
厚さに相当する厚さまで堆積させた後シリコンウェーハ
側から研削と研磨により島状のシリコン単結晶を作る、
いわゆる誘電体分離ウェーハが知られている。
2. Description of the Related Art Conventionally, an oxide insulating film is formed after forming a dielectric isolation groove on a surface of a silicon wafer, and polysilicon is formed on this insulating film by high temperature CVD to a thickness corresponding to the thickness of the wafer. After depositing up to this point, an island-shaped silicon single crystal is made by grinding and polishing from the silicon wafer side.
So-called dielectric separated wafers are known.

【0003】この誘電体分離ウェーハは、通常、図2に
示す様な方法により製造されている。まず、図2(a)
に示すシリコンウェーハ1の表面1aを所定形状の溝に
加工し、この加工された面2に熱酸化膜3を形成する
(同図(b))。次に、高温CVD(Chemical Vapor
Deposition:化学気相成長)法により、常圧、120
0℃の条件の下で酸化膜3上にポリシリコン層4を厚く
堆積させた後(同図(c))、シリコンウェーハ1に研
削加工、鏡面研磨加工を施し、ポリシリコン4に埋め込
まれた島状単結晶7とする(同図(d))。ここで得ら
れた島状単結晶7を有するウェーハを、誘電体分離ウェ
ーハ7と称している。
This dielectric-divided wafer is usually manufactured by the method shown in FIG. First, FIG. 2 (a)
The surface 1a of the silicon wafer 1 shown in FIG. 2 is processed into a groove having a predetermined shape, and the thermal oxide film 3 is formed on the processed surface 2 (FIG. 2B). Next, high temperature CVD (Chemical Vapor)
Deposition: chemical vapor deposition), atmospheric pressure, 120
After thickly depositing the polysilicon layer 4 on the oxide film 3 under the condition of 0 ° C. ((c) in the same figure), the silicon wafer 1 was subjected to grinding processing and mirror polishing processing and embedded in the polysilicon 4. The island-shaped single crystal 7 is used (FIG. 7 (d)). The wafer having the island-shaped single crystal 7 obtained here is referred to as a dielectric isolation wafer 7.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記の
誘電体分離ウェーハでは、高温CVDを長時間行い、更
に、このため単結晶の品質を劣化させるので、CVDを
必要最小限にして支持ウェーハと貼り合わせる方法が提
案されている。しかし、この方法においても、ポリシリ
コン層4の厚さを溝深さの3倍とし、ポリシリコン膜の
凹凸を研削により除去し、貼り合わせのために鏡面研磨
加工を施す際に、この研磨面に溝上部とシリコン表面の
CVD成長形態が異なり結晶粒度や方位の差が研磨速度
の差となり20〜100nm程度の段差が生じるために
表面が平滑にならないという欠点があった。したがっ
て、ポリシリコン面と支持ウェーハを相互に貼り合わせ
る場合に、貼り合わせ面に気泡が入り易く、この貼り合
わせ面の貼り合わせ強度が弱く、貼り合わせ誘電体分離
ウェーハ7の信頼性を低下させる原因となっていた。
However, in the above-described dielectric-isolated wafer, high temperature CVD is performed for a long time, which further deteriorates the quality of the single crystal. A method of matching is proposed. However, also in this method, the thickness of the polysilicon layer 4 is set to be three times the groove depth, the irregularities of the polysilicon film are removed by grinding, and the polishing surface is used when mirror polishing is performed for bonding. In addition, there is a drawback that the surface is not smooth because the difference between the crystal grain size and the orientation is different in the CVD growth mode between the upper part of the groove and the silicon surface and the difference in polishing rate causes a step difference of about 20 to 100 nm. Therefore, when the polysilicon surface and the supporting wafer are bonded to each other, bubbles are likely to enter the bonding surface, the bonding strength of this bonding surface is weak, and the reliability of the bonded dielectric isolation wafer 7 is reduced. It was.

【0005】本発明は、上記の事情に鑑みてなされたも
ので、貼り合わせ面の段差を低減させ、該貼り合わせ面
の貼り合わせ強度を向上させることのできる誘電体分離
ウェーハの製造方法を提供することにある。
The present invention has been made in view of the above circumstances, and provides a method for manufacturing a dielectric-divided wafer, which can reduce the step of the bonding surface and improve the bonding strength of the bonding surface. To do.

【0006】[0006]

【課題を解決するための手段】上記課題を解決するため
に、本発明は次の様な貼り合わせ誘電体分離ウェーハの
製造方法を採用した。すなわち、誘電体分離島を有する
シリコンウェーハを支持ウェーハに貼り合わせる誘電体
分離ウェーハの製造方法であって、所定形状の誘電体分
離用溝を形成したシリコンウェーハの表面に、酸化膜、
高温CVD法によるポリシリコン層を順次成膜し、次い
で該高温ポリシリコン層に研削加工、鏡面研磨加工を順
次施し、この高温ポリシリコン層の上に低温CVD法に
よるポリシリコン膜を成膜し、該低温ポリシリコン膜に
鏡面研磨加工を施し、次いで該低温ポリシリコン膜と支
持体シリコンウェーハの表面を相互に貼り合わせること
を特徴としている。
In order to solve the above problems, the present invention adopts the following method for manufacturing a bonded dielectric separated wafer. That is, a method for manufacturing a dielectric isolation wafer in which a silicon wafer having a dielectric isolation island is attached to a support wafer, the surface of the silicon wafer having a dielectric isolation groove of a predetermined shape, an oxide film,
A polysilicon layer is sequentially formed by the high temperature CVD method, and then the high temperature polysilicon layer is sequentially subjected to grinding processing and mirror polishing processing, and a polysilicon film is formed on the high temperature polysilicon layer by the low temperature CVD method. The low-temperature polysilicon film is mirror-polished, and then the low-temperature polysilicon film and the surface of the support silicon wafer are bonded to each other.

【0007】[0007]

【作用】本発明の貼り合わせ誘電体分離ウェーハの製造
方法では、鏡面研磨加工を施した高温ポリシリコン層の
上に低温CVD法によるポリシリコン膜を成膜すること
により、該低温ポリシリコン膜が前記高温ポリシリコン
層研磨表面に発生する段差を解消し、貼り合わせ面の貼
り合わせ強度を向上させる。
In the method for manufacturing a bonded dielectric separated wafer according to the present invention, a low temperature polysilicon film is formed by forming a polysilicon film by a low temperature CVD method on a high temperature polysilicon layer that has been mirror-polished. The step generated on the polished surface of the high temperature polysilicon layer is eliminated, and the bonding strength of the bonding surface is improved.

【0008】[0008]

【実施例】以下、本発明の貼り合わせ誘電体分離ウェー
ハの製造方法の一実施例について図1を参照して説明す
る。まず、同図(a)のシリコンウェーハ11の表面1
1aに所定の溝加工を施した後、この加工された面に熱
酸化膜12を形成する(同図(b))。次に、高温CV
D法により、トリクロロシラン、常圧、1200℃の条
件の下で酸化膜12上に高温ポリシリコン層13を溝深
さの3倍堆積し(同図(c))、その後この高温ポリシ
リコン層13に研削加工、鏡面研磨加工を順次施し、シ
リコン単結晶から3ミクロンの厚みの高温ポリシリコン
膜14とする(同図(d))。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a bonded dielectric separated wafer of the present invention will be described below with reference to FIG. First, the surface 1 of the silicon wafer 11 shown in FIG.
After performing a predetermined groove processing on 1a, a thermal oxide film 12 is formed on the processed surface (FIG. 2B). Next, high temperature CV
By the method D, a high temperature polysilicon layer 13 was deposited on the oxide film 12 at a depth of 3 times the groove depth under the conditions of trichlorosilane, atmospheric pressure and 1200 ° C. (FIG. 3C), and then this high temperature polysilicon layer was formed. Grinding and mirror polishing are sequentially performed on 13 to form a high temperature polysilicon film 14 having a thickness of 3 μm from a silicon single crystal (FIG. 3D).

【0009】次に、低温CVD法により、1Torr、6
00℃の条件の下で高温ポリシリコン膜14上に低温ポ
リシリコン膜15を2ミクロン成膜し(同図(e))、
その後この低温ポリシリコン膜15を、鏡面研磨加工を
施し、1ミクロンの厚みの低温ポリシリコン膜16とす
る(同図(f))。
Next, by a low temperature CVD method, 1 Torr, 6
Under the condition of 00 ° C., a low-temperature polysilicon film 15 having a thickness of 2 μm is formed on the high-temperature polysilicon film 14 (FIG. 8E).
Then, the low temperature polysilicon film 15 is subjected to mirror polishing to form a low temperature polysilicon film 16 having a thickness of 1 micron (FIG. 6 (f)).

【0010】次に、この低温ポリシリコン膜16の上に
同図(g)のシリコンウェーハ17の表面17aをアル
カリ洗浄し表面を親水化させた後密着させ、その後これ
らのシリコンウェーハ11,17を例えば1000℃で
2時間熱処理することでこれらのシリコンウェーハ1
1,17を相互に貼り合わせる(同図(h))。その
後、シリコンウェーハ11に研削加工、鏡面研磨加工を
順次施し、所定の形状の誘電体分離島を持つ誘電体分離
ウェーハ18とする(同図(i))。
Next, the surface 17a of the silicon wafer 17 shown in FIG. 1 (g) is washed with an alkali on the low-temperature polysilicon film 16 to make the surface hydrophilic, and then adhered thereto. For example, heat treatment at 1000 ° C. for 2 hours allows these silicon wafers 1
1, 17 are attached to each other ((h) in the figure). Thereafter, the silicon wafer 11 is sequentially subjected to grinding processing and mirror polishing processing to obtain a dielectric isolation wafer 18 having dielectric isolation islands of a predetermined shape ((i) in the figure).

【0011】この誘電体分離ウェーハ18の製造方法で
は、鏡面研磨加工を施した高温ポリシリコン層14の上
に低温ポリシリコン膜15を成膜することにより、該低
温ポリシリコン膜15が高温ポリシリコン膜14の表面
に発生する段差を解消し、貼り合わせ面の貼り合わせ強
度を向上させる。
In the method of manufacturing the dielectric-isolated wafer 18, the low-temperature polysilicon film 15 is formed on the high-temperature polysilicon layer 14 that has been mirror-polished, so that the low-temperature polysilicon film 15 becomes high-temperature polysilicon. The step generated on the surface of the film 14 is eliminated, and the bonding strength of the bonding surface is improved.

【0012】以上説明した様に、上記一実施例の誘電体
分離ウェーハ18の製造方法によれば、鏡面研磨加工を
施した所定の厚みの高温ポリシリコン層14上に低温ポ
リシリコン膜15を成膜することとしたので、シリコン
ウェーハ17とシリコンウェーハ11との貼り合わせ面
の段差を解消することができ、この貼り合わせ面の貼り
合わせ強度を向上させることができる。したがって、従
来問題とされていたこの貼り合わせ面の気泡を大幅に減
少させることができる。
As described above, according to the method for manufacturing the dielectric separated wafer 18 of the above-described embodiment, the low temperature polysilicon film 15 is formed on the high temperature polysilicon layer 14 having a predetermined thickness which has been mirror-polished. Since the film is formed, the step on the bonding surface between the silicon wafer 17 and the silicon wafer 11 can be eliminated, and the bonding strength of this bonding surface can be improved. Therefore, it is possible to greatly reduce the bubbles on the bonding surface, which has been a problem in the past.

【0013】[0013]

【発明の効果】以上説明した様に、本発明の貼り合わせ
誘電体分離ウェーハの製造方法によれば、誘電体分離島
を有するシリコンウェーハを支持ウェーハに貼り合わせ
る誘電体分離ウェーハの製造方法であって、誘電体分離
用溝を形成したシリコンウェーハの表面に、酸化膜、高
温CVD法によるポリシリコン層を順次成膜し、次いで
該高温ポリシリコン層に研削加工、鏡面研磨加工を順次
施し、この高温ポリシリコン層の上に低温CVD法によ
るポリシリコン膜を成膜し、該低温ポリシリコン膜に鏡
面研磨加工を施し、次いで該低温ポリシリコン膜と支持
体シリコンウェーハの表面を相互に貼り合わせることと
したので、シリコンウェーハの低温ポリシリコン膜との
貼り合わせ面の段差を解消することができ、この貼り合
わせ面の貼り合わせ強度を向上させることができる。し
たがって、従来実用上の障害とされていたこの貼り合わ
せ面の気泡を大幅に減少させることができる。
As described above, the method for manufacturing a bonded dielectric separated wafer according to the present invention is a method for manufacturing a dielectric separated wafer in which a silicon wafer having dielectric separated islands is bonded to a supporting wafer. Then, an oxide film and a polysilicon layer by a high temperature CVD method are sequentially formed on the surface of the silicon wafer on which the dielectric isolation groove is formed, and then the high temperature polysilicon layer is sequentially subjected to grinding processing and mirror polishing processing. Forming a polysilicon film by the low temperature CVD method on the high temperature polysilicon layer, subjecting the low temperature polysilicon film to mirror polishing, and then bonding the low temperature polysilicon film and the surface of the support silicon wafer to each other. Therefore, it is possible to eliminate the step on the bonding surface of the silicon wafer with the low-temperature polysilicon film. It is possible to improve the strength. Therefore, it is possible to greatly reduce the air bubbles on the bonding surface, which has hitherto been a practical obstacle.

【0014】以上により、貼り合わせ面の段差を解消す
ることができ、この貼り合わせ面の貼り合わせ強度を向
上させることのできる貼り合わせ誘電体分離ウェーハの
製造方法を提供することが可能になる。
As described above, it is possible to provide a method for manufacturing a bonded dielectric separated wafer which can eliminate the step on the bonded surface and improve the bonding strength of the bonded surface.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の貼り合わせ誘電体分離ウェーハの製造
方法の一実施例を示す過程図である。
FIG. 1 is a process drawing showing an embodiment of a method for manufacturing a bonded dielectric separated wafer of the present invention.

【図2】従来の誘電体分離ウェーハの製造方法を示す過
程図である。
FIG. 2 is a process diagram showing a conventional method for manufacturing a dielectric isolation wafer.

【符号の説明】[Explanation of symbols]

11 シリコンウェーハ 11a 表面 12 酸化膜 13 高温ポリシリコン層 14 高温ポリシリコン層 15 低温ポリシリコン膜 16 低温ポリシリコン膜 17 シリコンウェーハ 18 誘電体分離ウェーハ 11 Silicon Wafer 11a Surface 12 Oxide Film 13 High Temperature Polysilicon Layer 14 High Temperature Polysilicon Layer 15 Low Temperature Polysilicon Film 16 Low Temperature Polysilicon Film 17 Silicon Wafer 18 Dielectric Separation Wafer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 誘電体分離島を有するシリコンウェーハ
を支持ウェーハに貼り合わせる誘電体分離ウェーハの製
造方法であって、 誘電体分離用溝を形成したシリコンウェーハの表面に、
酸化膜、高温CVD法によるポリシリコン層を順次成膜
し、次いで該高温ポリシリコン層に研削加工、鏡面研磨
加工を順次施し、この高温ポリシリコン層の上に低温C
VD法によるポリシリコン膜を成膜し、該低温ポリシリ
コン膜に鏡面研磨加工を施し、次いで該低温ポリシリコ
ン膜と支持体シリコンウェーハの表面を相互に貼り合わ
せることを特徴とする貼り合わせ誘電体分離ウェーハの
製造方法。
1. A method for manufacturing a dielectric isolation wafer, which comprises bonding a silicon wafer having dielectric isolation islands to a support wafer, the method comprising: forming a dielectric isolation groove on a surface of the silicon wafer;
An oxide film and a polysilicon layer by a high temperature CVD method are sequentially formed, and then the high temperature polysilicon layer is sequentially subjected to grinding and mirror polishing, and a low temperature C is formed on the high temperature polysilicon layer.
A laminated dielectric characterized in that a polysilicon film is formed by the VD method, the low-temperature polysilicon film is mirror-polished, and then the low-temperature polysilicon film and the surface of a support silicon wafer are bonded to each other. Method for manufacturing separated wafer.
JP2414492A 1992-02-10 1992-02-10 Manufacture of joined dielectric isolation wafer Pending JPH05226463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2414492A JPH05226463A (en) 1992-02-10 1992-02-10 Manufacture of joined dielectric isolation wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2414492A JPH05226463A (en) 1992-02-10 1992-02-10 Manufacture of joined dielectric isolation wafer

Publications (1)

Publication Number Publication Date
JPH05226463A true JPH05226463A (en) 1993-09-03

Family

ID=12130138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2414492A Pending JPH05226463A (en) 1992-02-10 1992-02-10 Manufacture of joined dielectric isolation wafer

Country Status (1)

Country Link
JP (1) JPH05226463A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060344A (en) * 1997-08-20 2000-05-09 Denso Corporation Method for producing a semiconductor substrate
JP2015050429A (en) * 2013-09-04 2015-03-16 信越半導体株式会社 Soi wafer manufacturing method, soi wafer and semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03265153A (en) * 1990-03-14 1991-11-26 Hitachi Ltd Dielectric isolation substrate, manufacture thereof and semiconductor integrated circuit device using same substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03265153A (en) * 1990-03-14 1991-11-26 Hitachi Ltd Dielectric isolation substrate, manufacture thereof and semiconductor integrated circuit device using same substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6060344A (en) * 1997-08-20 2000-05-09 Denso Corporation Method for producing a semiconductor substrate
JP2015050429A (en) * 2013-09-04 2015-03-16 信越半導体株式会社 Soi wafer manufacturing method, soi wafer and semiconductor device

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