JPH11214368A - Wafer planarizing method and its device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the problem that only an active layer becomes thin in an outer circumferential part of a wafer, when compared to other central parts in a planarization method of a wafer through a PACE method, which is adopted for improving uniformity of the thickness of an SOI active layer of an SOI wafer. SOLUTION: When the thickness of a single-crystalline silicon layer provided to a wafer surface is made as specified, a recess 11 the depth of which is corresponding to a required wafer thickness is provided to a stage 10 whereon a treatment wafer is mounted or a ring 20 the thickness of which corresponds to a required wafer thickness is arranged in an outer circumference of a treatment wafer 4. Thereby, it is possible to prevent thinning of the layer in the circumferential edge part of a wafer and to obtain highly accurate planarity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a wafer flattening method and apparatus for obtaining a required wafer flatness by locally plasma etching a wafer surface such as a silicon wafer. When the thickness of the single-crystal silicon layer is set to a predetermined thickness, a recess having a depth corresponding to the required wafer thickness is provided on a stage on which a wafer to be processed is mounted, or a ring having the same thickness is arranged, thereby forming a peripheral portion of the wafer. The present invention relates to a wafer flattening method and a wafer flattening method for preventing the layer thickness from becoming thinner and obtaining a high-precision flatness.

[0002]

2. Description of the Related Art On an oxide film insulating layer formed on a silicon wafer, a single crystal silicon layer of higher quality, that is, SOI (Silicon On Insulato) is used.
r) An SOI wafer having a structure in which an active layer is formed uniformly makes it easy to separate elements, so that high integration, low power consumption, and high speed of devices can be expected, and practical use of some of them is progressing. In.

The thickness of the SOI active layer of an SOI wafer is
It depends on the element structure.
1 μm or less, 0.5 to 0.5 μm for Bi-CMOS
1.0 μm, 1 to 5 μm for bipolar, and several μm or more for high power and sensors.

Various methods for manufacturing SOI wafers have been proposed. Typical SOI wafers include a bonded SOI substrate and a SIMOX (Separa).
Tion by Implanted Oxygen)
There is a wafer.

[0005] As shown in FIG.
An oxide film 2 is formed by thermally oxidizing a bond wafer 1 serving as an OI active layer, and is bonded to a base wafer 3 having no oxide film at room temperature. Then, a bonding anneal is performed in an oxidizing atmosphere to increase the bonding strength. The bonded SOI wafer 4 is manufactured by thinning the wafer 1 by grinding and polishing.

Since the bonded bond wafer 1 is thinned by grinding and polishing, it can be obtained stably when the SOI active layer is relatively thick, but it is difficult to control the thickness to 0.1 μm or less. It has been said that there is.

[0007]

In the SOI wafer obtained by the bonding method, the SOI active layer on the surface is thinned to 1 to 5 μm by the conventional grinding and polishing method. There is a need for a method for improving the uniformity of the film thickness.

In recent years, as a method of locally etching a thick portion of a silicon layer, PACE using plasma is used.
(Plasma assisted chemical
Etching) method is proposed (Japanese Patent Laid-Open No. 5-16007).
4, JP-A-9-252100).

More specifically, the thickness unevenness of the surface obtained by the conventional grinding and polishing method is obtained by utilizing interference fringes of visible light.
Since high-speed measurement is possible by combination with a two-dimensional CCD, as shown in FIG.
The thickness distribution of the SOI active layer of the I-wafer 4 is input to a computer, and the moving speed of the wafer 4 is adjusted in accordance with the size of the thickness unevenness, for example, with respect to the head nozzle 5 in which the plasma is confined in a low vacuum. The diameter of the head nozzle is appropriately selected from the precision and productivity. Conversely, the head nozzle 5 can be moved on the wafer 4.

In the PACE method, SF ₆ is used as a reaction gas for silicon, and the etching rate is very high for general plasma etching, the degree of vacuum for plasma generation is high, and the high frequency power is extremely high. The feature is that the crystal is not damaged because it is very small.

Although the thickness uniformity of the SOI active layer is greatly improved by the PACE technique, there is a problem that the thickness of the active layer at the peripheral portion of the SOI wafer tends to be smaller than that at other central portions. Newly generated.

According to the present invention, there is provided a method for planarizing a wafer by a PACE method used for improving the uniformity of the thickness of an SOI active layer of an SOI wafer. It is an object of the present invention to provide a method and an apparatus for planarizing a wafer which can solve the problem of thinning as compared with the prior art.

[0013]

Means for Solving the Problems The inventors of the present invention have made various studies on the tendency of the active layer to become thinner at the peripheral portion of the SOI wafer as compared with other central portions in the wafer flattening method by the PACE method. As a result, the inventors have found that the reason why the etching rate at the wafer peripheral portion is high is that the plasma is hard to separate from the wafer peripheral portion, and that the plasma is generated when the distance between the head nozzle and the wafer edge is smaller than the distance between the stage and the stage.

The inventors further examined the above findings, and found that a recess was formed in the stage by the thickness of the wafer or that the wafer outer periphery was equivalent to the thickness so that the wafer surface and the stage could be arranged in a plane. By arranging the ring, it was found that the etching rate can be made equal to the etching rate at the center even at the wafer edge, and the present invention was completed.

That is, the present invention provides a wafer flattening method for obtaining a required wafer flatness by etching a wafer surface relatively moving with respect to a head nozzle with plasma generated by introducing a reaction gas into a nozzle. At
For example, assuming that the thickness of the wafer is d and the etching amount is r, the depth of the recess is D, so that the wafer surface and the stage surface can be flush with each other on the stage on which the wafer to be processed is mounted and relatively moved with respect to the head nozzle. Etching by providing at least a recess having a depth corresponding to the required wafer thickness after processing such that d ≧ D ≧ dr, or a ring having a thickness corresponding to the required wafer thickness on the outer periphery of the wafer to be processed And etching the wafer.

Further, the present invention has a stage on which a wafer to be processed is mounted and relatively moved with respect to a head nozzle, wherein plasma generated by introducing a reaction gas into the nozzle is used.
In a wafer flattening apparatus that obtains a required wafer flatness by etching a wafer surface that moves relative to a head nozzle, a stage is provided with a recess having a depth corresponding to a required wafer thickness, or a required wafer is placed on the stage. A wafer flattening device comprising a ring having a thickness corresponding to the thickness and having an inner diameter larger than an outer diameter of a wafer to be processed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a method of planarizing a wafer includes any of the above-mentioned known PACE methods described with reference to FIG. The plasma head nozzle and reaction gas to be used are also appropriately selected according to the type of wafer to be processed, such as a silicon substrate, various crystal substrates, and glass, and both the head nozzle and the stage are movable and fixed. Can be adopted.

The reaction gas includes SF ₆ , Cl ₂ or the like for a silicon wafer, and C for a quartz or glass wafer.
F ₄ , C ₂ F ₆ , C ₃ F _{8 and the} like can be used.

In the present invention, the characteristic stage 1
As shown in FIGS. 1A and 1B, the recess 11 having a shape similar to the outer shape of the wafer to be processed and having a recess having a required depth is a recess 11 for a notch wafer. Due to such restrictions, a wafer fixing system is not required. In the case of an orientation flat (OF) wafer, a flat portion may be provided so that the shape of the recess matches the shape of the OF wafer.

As described above, the wafer fixing system is unnecessary, but in order to further stably fix the wafer, the recess 11 is used.
, A slide-type wafer fixing system can be attached from a part of the outer peripheral portion.

The depth of the recess 11 is smaller than that of the conventional method when the wafer surface and the stage surface are flat before the etching, and when the wafer surface and the stage surface are flat after the etching is completed. This is effective in reducing the edge exclusion area. That is, if the recess depth D is the wafer thickness d and the etching amount r, d
≧ D ≧ dr is desirable.

Further, in the present invention, as shown in FIG. 1C, the above-described recess is provided by mounting and fixing the ring 20 on which the wafer 4 to be processed is housed in the inner peripheral portion on the stage 10. The same operation and effect as the configuration, that is, the etching rate at the wafer edge can be made equal to the etching rate at the center.

In the ring for a notch wafer, the rotation of the wafer is regulated by providing a notch in the inner peripheral portion in a shape similar to the outer shape of the wafer to be processed, and the wafer can be fixed by providing a flat portion for the OF wafer. Becomes Further, the thickness T of the ring 20 is desirably d ≧ T ≧ dr similarly to the depth of the recess 11. The ring material is
The same material is desirable so that the same etching rate as that of the wafer can be obtained, and the same material as silicon, quartz, SiC, and the stage can be adopted.

[0024]

EXAMPLE 1 Using a stage provided with a recess according to the present invention shown in FIGS. 1A and 1B, local plasma etching of an SOI wafer was performed using a plasma head nozzle having an outer diameter of 25 mm as shown in FIG. Average thickness of SOI active layer 100 nm
Then, the wafer was flattened with the device fabrication allowable range of ± 10 nm.

The recess depth of the stage is 73 μm when the thickness d of the wafer is 730 μm and the etching amount r is 3 μm.
Two types, 0 μm and 727 μm, were set. The etching conditions were SF ₆ = 15 sccm, pressure 2.9 Torr.
r, RF Power = 90W.

For comparison, local plasma etching was similarly performed using a conventional stage having a flat surface without a recess to flatten the wafer.

FIG. 2 shows the distribution of the thickness of the Si active layer after the plasma etching in the stage with the recess according to the present invention (plotted by black circles), and the Si active layer after the plasma etching using the conventional stage without the recess. The thickness distribution (plotted with white circles) is shown. On a traditional stage,
Whereas the edge exclusion area is 10 mm, the use of the recessed stage can reduce the edge exclusion area to 5 mm or less.

Example 2 Using a stage on which a ring according to the present invention is mounted as shown in FIG. 1C, local plasma etching of an SOI wafer is performed using a plasma head nozzle having an outer diameter of 25 mm as shown in FIG. Wafer flattening was performed in the same manner as in Example 1 except that the device fabrication allowable range was ± 10 nm with respect to the average layer thickness of 100 nm.

When flattening was performed under the same etching conditions as in Example 1 by setting the ring width to 40 mm and the thickness to 73 μm and 727 μm, the distribution of the Si active layer thickness equivalent to FIG. 2 was obtained. And the edge exclusion area could be reduced to 5 mm or less.

Example 3 A quartz wafer was used instead of the SOI wafer.
When C ₂ F ₆ was used as the reaction gas and the same flattening was performed on the stage where the recess was provided and the stage where the ring was placed, the etching rate was made uniform as in the case of the silicon wafer, and the edge exclusion area was removed. Was reduced.

[0031]

According to the present invention, in the method of flattening a wafer by the PACE method, only the outer peripheral portion of the SOI wafer has S
The problem that the thickness of the OI active layer becomes thinner than the other central part can be solved, the uniformity of the thickness distribution of the SOI active layer and the TTV of the wafer can be controlled with high accuracy, and the device fabrication area can be enlarged.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a stage according to the present invention, wherein A is a front explanatory view, B is a plan explanatory view, and C is a longitudinal sectional explanatory view of a main part of another stage according to the present invention.

FIG. 2 is a graph showing a relationship between a diameter direction of an SOI wafer and a thickness distribution of an SOI active layer.

FIG. 3 is a flowchart showing a manufacturing process of an SOI wafer.

4A and 4B are explanatory diagrams showing a wafer flattening method by the PACE method, wherein A is a perspective explanatory diagram of the wafer, and B is a longitudinal sectional description of a plasma head nozzle.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bond wafer 2 Oxide film 3 Base wafer 4 SOI wafer 5 Head nozzle 10 Stage 11 Recess 12 Notch 20 Ring

Claims (5)

[Claims] In a wafer flattening method for obtaining a required wafer flatness by etching a wafer surface moving relative to a head nozzle with plasma generated by introducing a reactive gas into a nozzle, A stage on which a wafer is placed and moves relatively to a head nozzle is provided with a recess having a depth corresponding to at least a required wafer thickness after processing so that the wafer surface and the stage surface can be flush with each other. Method. 2. A wafer flattening method for obtaining a required wafer flatness by etching a wafer surface moving relative to a head nozzle with plasma generated by introducing a reaction gas into a nozzle. On the stage where the wafer is mounted and moves relative to the head nozzle, a ring is placed on the outer periphery of the wafer with at least a ring having a thickness corresponding to the required wafer thickness after processing so that the wafer surface and the stage surface can be flush with each other. Flattening method. 3. A depth D of a recess provided in a stage or a thickness T of a ring according to claim 1.
However, if the thickness of the wafer is d and the amount of etching is r,
A method of planarizing a wafer, wherein d ≧ D (T) ≧ dr. 4. A stage on which a wafer to be processed is placed and relatively moved with respect to a head nozzle, and the surface of the wafer which is relatively moved with the head nozzle is etched by plasma generated by introducing a reaction gas into the nozzle. A wafer flattening device for obtaining a required wafer flatness, wherein a stage is provided with a recess having a depth corresponding to a required wafer thickness. 5. A stage for mounting a wafer to be processed and moving relative to a head nozzle, and etching a surface of the wafer moving relative to the head nozzle with plasma generated by introducing a reaction gas into the nozzle. A wafer flattening device for obtaining a required wafer flatness, wherein a ring having a thickness corresponding to a required wafer thickness and an inner diameter larger than an outer diameter of a wafer to be processed is provided on a stage.