JP2009253133A - Method of planarizing semiconductor wafer, local plasma treatment apparatus, and method of manufacturing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of planarizing a semiconductor wafer, a local plasma treatment apparatus, and a method of manufacturing a semiconductor wafer which can shorten the treatment time. <P>SOLUTION: In the method of planarizing a semiconductor wafer, an etching gas is excited by plasmas to produce a gas containing neutral active species and then the produced gas is locally supplied to the principal plane of the semiconductor wafer to locally etch the semiconductor wafer to planarize the semiconductor wafer. In the method, the in-plane surface of the semiconductor wafer is divided into a plurality of regions having a different profile of an etch rate, and a position to perform local etching is determined in each region so as to suppress a difference in profile of the etch rate among the plurality of regions. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer flattening method, a local plasma processing apparatus, and a semiconductor wafer manufacturing method that require high flatness.

A semiconductor wafer such as a silicon wafer is required to have a uniform thickness and a flat surface shape in order to form a fine circuit pattern on the surface. Here, as a technique for planarizing a semiconductor wafer, mechanical or mechanical chemical polishing methods such as grinding and CMP (Chemical Mechanical Polishing) are known, but there is a limit to the flatness obtained. .
Therefore, in recent years, a technique has been proposed in which the surface to be processed is subjected to local plasma etching to achieve planarization (see Patent Document 1).
In the technique disclosed in Patent Document 1, the flatness of a semiconductor wafer is obtained in advance, and the removal amount at each portion is calculated based on the value. Then, the surface side of the semiconductor wafer is plasma-etched with a removal amount corresponding to the variation in thickness to obtain high flatness. However, in this technique, it is necessary to relatively scan (move) the nozzle to a position beyond the peripheral edge of the semiconductor wafer in order to etch the peripheral edge of the semiconductor wafer (FIGS. 4 and 10 of Patent Document 1). See). For this reason, the relative movement distance of the nozzle becomes long, which may increase the processing time and decrease the productivity.

  Here, the profile of the etching rate changes depending on the position in the surface of the semiconductor wafer. For example, the etching rate differs between the central portion and the peripheral portion of the semiconductor wafer. Therefore, if the central part and the peripheral part of the semiconductor wafer are etched under the same conditions, the flatness may be deteriorated.

Therefore, a flattening technique that takes into account the difference in the etching rate profile has been proposed (see Patent Documents 2 and 3).
However, even in these techniques, the nozzle is relatively scanned (moved) to a position beyond the peripheral edge of the semiconductor wafer in order to etch the peripheral edge of the semiconductor wafer (FIG. 1, Patent Document 3 of Patent Document 2). (See FIG. 8). For this reason, the relative movement distance of the nozzle becomes long, which may increase the processing time and decrease the productivity.

In addition, the profile of the etching rate is affected not only by the position within the surface of the semiconductor wafer but also by, for example, the concentration of neutral active species, the flow of gas containing the neutral active species, and temperature. Therefore, there is a possibility that the flatness cannot be improved only by the technique disclosed in Patent Document 2. Further, as in the technique disclosed in Patent Document 3, if the etching conditions are changed between the central portion and the peripheral portion while zigzag scanning the nozzle in the radial direction of the semiconductor wafer, the arithmetic processing may be difficult. there were.
JP 2001-244240 A JP 11-214368 A JP 2002-252210 A

  The present invention provides a method for planarizing a semiconductor wafer, a local plasma processing apparatus, and a method for manufacturing a semiconductor wafer that can reduce processing time.

  According to one aspect of the present invention, an etching gas is excited by plasma to generate a gas containing neutral active species, and the gas is locally supplied to the main surface of the semiconductor wafer to perform local etching. A method for planarizing a semiconductor wafer, wherein the surface of the semiconductor wafer is divided into a plurality of regions having different etching rate profiles, and the difference in the etching rate profile between the plurality of regions is suppressed. Thus, there is provided a method for planarizing a semiconductor wafer, wherein a position for performing the local etching is determined in each of the plurality of regions.

  According to another aspect of the present invention, the relative position of the plasma generating means for exciting the etching gas with plasma, the mounting table for mounting the semiconductor wafer, the plasma generating means, and the mounting table described above. Control means for controlling the etching rate profile, wherein the control means suppresses a difference in the etching rate profile between the plurality of regions of the semiconductor wafer divided into a plurality of regions having different etching rate profiles. Thus, a local plasma processing apparatus characterized by controlling a relative position between the plasma generating means and the mounting table is provided.

  Furthermore, according to another aspect of the present invention, a semiconductor wafer is cut out from an ingot of single crystal silicon, and a chamfered surface is formed on a peripheral edge of the semiconductor wafer to form a main surface of the semiconductor wafer. There is provided a method for producing a semiconductor wafer, comprising: polishing, etching the semiconductor wafer, and planarizing the semiconductor wafer by using the semiconductor wafer planarization method.

  ADVANTAGE OF THE INVENTION According to this invention, the planarization method of the semiconductor wafer which can suppress processing time, a local plasma processing apparatus, and the manufacturing method of a semiconductor wafer are provided.

  Hereinafter, embodiments of the present invention will be illustrated with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and detailed description is abbreviate | omitted suitably.

FIG. 1 is a flowchart for illustrating a method for manufacturing a semiconductor wafer W according to an embodiment of the present invention.
First, slicing is performed by cutting a semiconductor wafer W having a predetermined thickness from a single crystal silicon ingot using a cutting tool such as a blade or a wire (step S1).
Next, a chamfering process is performed on the peripheral edge of the cut-out semiconductor wafer W to form a chamfered surface (step S2).

Next, a polishing process for polishing the surface of the semiconductor wafer W is performed (step S3).
This polishing process is performed in order to remove the unevenness on the main surface of the semiconductor wafer W generated by the above-described slicing and to flatten the surface. For example, lapping of the main surface is performed using a known polishing apparatus or the like.

Next, the semiconductor wafer W is etched to remove the processing damage caused by the chamfering process and the polishing process (step S4).
This etching process can be, for example, a wet etching process, specifically an acid etching process or an alkali etching process. In the acid etching process, for example, the semiconductor wafer W is immersed in a mixed solution of nitric acid (HNO ₃ ) and hydrogen fluoride (HF), and the silicon (Si) of the semiconductor wafer W is oxidized with nitric acid to form silicon oxide (SiO 2). ₂ ) is formed, and this is dissolved and removed with hydrogen fluoride. The alkali etching treatment includes, for example, a method in which the surface of the semiconductor wafer W is etched by immersing the semiconductor wafer W in an alkaline solution such as potassium hydroxide (KOH) or sodium hydroxide (NaOH).

Further, this etching process can be a dry etching process. For example, a neutral active species is generated by exciting and activating a predetermined etching gas (SF ₄ , NF _3, etc.) with plasma or the like, and among these, a neutral active species that causes little damage to the semiconductor wafer W is used. For example, an etching process is performed.

  Next, the shape of the unevenness on the front and back surfaces of the semiconductor wafer W is measured by flatness measuring means. Then, the in-plane thickness variation (in-plane thickness distribution) is calculated from the obtained unevenness values, and the calculation result is stored as in-plane distribution data (step S5).

  Based on the in-plane distribution data (thickness and coordinates), processing conditions for local plasma etching described later are determined. In this case, for example, the relationship between the amount of neutral active species and ions supplied, the supply time, and the etching amount and the etching amount are examined in advance, and the moving speed of the mounting table 4 is controlled based on the relationship to perform planarization. Can be.

  Examples of the flatness measuring means include those equipped with a non-contact type laser measuring device that is disposed so as to face the front surface and the back surface of the semiconductor wafer W and that can measure irregularities by laser light. can do. Further, the flatness measuring means stores moving means capable of moving the laser measuring apparatus along the front and back surfaces of the semiconductor wafer W, and controls the operation of these and stores measured unevenness data. It is also possible to provide a control means capable of performing the above.

Next, using the planarization method according to the present embodiment, a high planarization process is performed in which the main surface of the semiconductor wafer W is locally subjected to plasma etching (step S6).
For example, a predetermined etching gas is turned into plasma by introducing a microwave or the like to generate neutral active species, ions, etc., on the main surface of the semiconductor wafer W by the neutral active species with little damage to the semiconductor wafer W. It is possible to exemplify the local removal of the protrusions.

Further, the neutral active species and ions can be locally supplied toward the convex portion on the main surface of the semiconductor wafer W, and the etching process can be performed by chemical reaction and physical impact.
In this case, by controlling the amount of ions and the collision energy of ions with respect to the neutral active species, it is possible to perform an optimal etching process in accordance with the shape of the convex portion on the main surface of the semiconductor wafer W. For example, if many neutral active species that can be isotropically etched by a chemical reaction are used, a portion where the height of the convex portion is low and the area is relatively large (a gentle convex portion) is efficiently It can be flattened well. In addition, if the amount of ions that can be anisotropically etched by physical impact is increased or the collision energy is increased, the portion where the height of the convex portion is high and the area is relatively small (the sharp convex portion Part) can be flattened efficiently and accurately. Here, if the amount of ions and the collision energy of ions are too large, the semiconductor wafer W may be damaged. Therefore, it is preferable to use a treatment mainly composed of neutral active species.
Next, mirror finishing is performed on the semiconductor wafer W as necessary (step S7). In addition, what is necessary is just to perform suitably the process and process after a high planarization process as needed.
Further, in step S6, at least one of local etching at a peripheral portion, which will be described later, and local etching at a central portion can be performed. This is because depending on the case, it may be sufficient to perform either of the flattening processing.

Next, the planarization method according to this embodiment will be further illustrated.
FIG. 2 is a schematic diagram for illustrating the profile of the etching rate E immediately below the nozzle N. FIG. In the graph, the vertical axis represents the etching rate E, and the horizontal axis represents the distance X from the center of the nozzle N.
As shown in FIG. 2, the etching rate E becomes maximum immediately below the center of the nozzle N and decreases as the distance from the center of the nozzle N increases. This change in the etching rate E is a curve approximating a Gaussian distribution.

  Here, the profile of the etching rate E changes depending on the position in the plane of the semiconductor wafer W. For example, in the central portion of the semiconductor wafer W, the main surface of the semiconductor wafer W exists around the nozzle N as a center. Therefore, the injected gas containing neutral active species can spread evenly along the main surface of the semiconductor wafer W. As a result, the profile of the etching rate E also exhibits a symmetrical shape as illustrated in FIG. On the other hand, at the peripheral edge of the semiconductor wafer W, the main surface of the semiconductor wafer W exists only in one direction centered directly below the nozzle N. Therefore, the flow of the gas containing the neutral active species that is injected is affected by the shape of the semiconductor wafer W.

FIG. 3 is a schematic diagram for illustrating the profile of the etching rate E at the peripheral edge of the semiconductor wafer W. In the graph, the vertical axis represents the etching rate E, and the horizontal axis represents the distance X from the center of the nozzle N.
At the peripheral edge of the semiconductor wafer W, the main surface of the semiconductor wafer W exists only in one direction centered directly below the nozzle N. Therefore, the flow of the gas containing neutral active species is not symmetric, and the profile of the etching rate E is deformed as illustrated in FIG. In addition, since the gas containing the neutral active species flows around the back surface side of the semiconductor wafer W at the peripheral portion, the profile of the etching rate E may be deformed due to this influence. Moreover, since the semiconductor wafer W which is an etching object does not exist outside the peripheral portion, the amount of neutral active species per unit area increases. From the above, the etching rate E at the peripheral portion is likely to be higher than that at the central portion. Therefore, if the peripheral portion and the central portion are processed under the same conditions, the flatness may be deteriorated.

  In order to reduce the influence of the in-plane position of the semiconductor wafer W, in the techniques disclosed in Patent Documents 1 to 3, the nozzle N is relatively scanned to a position beyond the peripheral edge of the semiconductor wafer W ( Move).

  FIG. 4 is a schematic diagram for illustrating the state of scanning (moving) of the nozzle N according to the comparative example. In this comparative example, the nozzle N is scanned in a zigzag manner in the radial direction of the semiconductor wafer W. In order to reduce the influence of the in-plane position of the semiconductor wafer W, the nozzle N is relatively scanned (moved) to a position beyond the peripheral edge of the semiconductor wafer W. In this case, since the nozzle N is overstroked from the peripheral edge of the semiconductor wafer W, extra time is consumed accordingly. Even if the etching rate of the peripheral portion is suppressed by adjusting the scanning (moving) speed and the amount of neutral active species without overstroke of the nozzle N, extra time is spent on the processing. Therefore, in any case, there is a risk of increasing the processing time and reducing the productivity.

  Further, even when the nozzle N is scanned (moved) in a spiral manner as in the technique disclosed in FIG. 10 of Patent Document 1, the start or end of scanning (moving) is performed outside the peripheral portion of the semiconductor wafer W. It is necessary to. Therefore, even in this case, the scanning distance becomes long, and extra time is consumed. As a result, processing time may increase and productivity may decrease.

FIG. 5 is a schematic diagram for illustrating the state of scanning (moving) of the nozzle N according to the present embodiment. 5A illustrates the case where the peripheral portion is processed after processing the central portion, and FIG. 5B illustrates the case where the central portion is processed after processing the peripheral portion.
In the present embodiment, the surface of the semiconductor wafer W is divided into a plurality of regions based on the etching rate E profile. An optimum scanning (moving) method and etching conditions are selected for each divided region. That is, the position where the local etching is performed is relatively scanned (moved) so that the difference in the etching rate profile for each of the divided regions is suppressed. In addition, an optimum etching condition is selected in accordance with the etching rate for each divided region.

  For example, as shown in FIG. 5, the nozzle N is scanned (moved) zigzag in the radial direction of the semiconductor wafer W in the central portion where the profile of the etching rate E is symmetric. Further, at the peripheral portion where the profile of the etching rate E is asymmetric, the position where the local etching is performed is relatively scanned (moved) along the peripheral portion of the semiconductor wafer W. In addition, as described above, the etching rate E at the peripheral portion tends to be high, and therefore the etching conditions are set such that the etching rate E can be suppressed as compared with the central portion.

  In this case, since it is not necessary to overstroke the nozzle N as in the comparative example, the scanning (movement) distance does not increase unnecessarily. In addition, since the optimum etching conditions can be selected for each region, useless processing time is not consumed. Further, since the regions are divided according to the profile of the etching rate E, the etching conditions can be made almost the same in each region. Therefore, it is possible to simplify the calculation process and improve the calculation speed.

  In addition, since optimum conditions can be selected for each region, flatness can be improved. For example, if the central portion is scanned (moved) in a spiral shape, the neutral active species tends to stay near the central portion of the semiconductor wafer W, and the flatness may be deteriorated. Therefore, the nozzle N is scanned (moved) in a zigzag manner in the radial direction of the semiconductor wafer W in the central portion, thereby suppressing the retention of neutral active species and improving the flatness. On the other hand, at the peripheral edge where one direction is open, there is little retention of neutral active species, so scanning (movement) along the peripheral edge can be performed.

  The peripheral portion may be processed after the central portion is processed as shown in FIG. 5A, or the central portion is processed after the peripheral portion is processed as shown in FIG. 5B. Also good.

  FIG. 6 is a schematic diagram for illustrating the state of scanning (moving) of the nozzle N according to the present embodiment. 6A illustrates a case where the peripheral portion is processed after processing the central portion, and FIG. 6B illustrates a case where the central portion is processed after processing the peripheral portion.

  In the present embodiment, the nozzle N is scanned (moved) in a “Z shape” in the radial direction of the semiconductor wafer W in the central portion where the profile of the etching rate E is symmetrical. Further, the nozzle N is scanned (moved) along the peripheral edge of the semiconductor wafer W at the peripheral edge where the profile of the etching rate E is asymmetric. In addition, as described above, the etching rate E at the peripheral portion tends to be high, and therefore the etching conditions are set such that the etching rate E can be suppressed as compared with the central portion.

In this case, as illustrated in FIGS. 5 and 6, the nozzle N may be scanned (moved) along a trajectory including a linear reciprocating movement when placed in the center. Note that the linear trajectory may include a curved trajectory, for example.
In addition, the effective etching region (the actual etching range) in the peripheral portion and the effective etching region (the actual etching range) in the central portion do not overlap. This is because the flatness may deteriorate if the effective etching regions overlap.

Next, the scanning position of the nozzle N at the peripheral edge will be further illustrated.
FIG. 7 is a schematic diagram for illustrating the position of the nozzle N at the peripheral edge. In the figure, 2E1 is the maximum value of the etching rate, and E1 is half the value. Further, 2X1 is the half width (full width at half maximum) of the etching rate profile, and X1 is the half width at half maximum.
The closer the position of the nozzle N is to the peripheral edge (end face) W1 of the semiconductor wafer W, the greater the deformation of the etching rate E profile. In this case, if the deformation of the etching rate E profile becomes too large, the flatness may be deteriorated. Therefore, it is preferable to set the position of the nozzle N that can suppress the influence on the flatness.

  In this case, according to the knowledge obtained by the present inventor, it is preferable that the center position of the nozzle N is on the inner side from the peripheral edge (end face) W1 of the semiconductor wafer W by a half-value half width X1 or more. That is, it is preferable that the supply center of the gas containing the neutral active species is relatively moved from the periphery of the semiconductor wafer W to the inside of the half-width at half maximum or more of the etching rate profile. By doing so, the influence of the deformation of the etching rate E profile on the flatness can be suppressed.

Depending on the type of the semiconductor wafer W, it may be necessary to further increase the flatness at the peripheral edge.
FIG. 8 is a schematic diagram for illustrating the improvement of the flatness at the peripheral edge. 8A illustrates the case where the peripheral portion is processed after processing the central portion, and FIG. 8B illustrates the case where the central portion is processed after processing the peripheral portion.
In the case illustrated in FIGS. 8A and 8B, the ring-shaped member 200 is provided so as to surround the periphery of the semiconductor wafer W. If the ring-shaped member 200 is provided, deformation of the profile of the etching rate E can be suppressed, so that the flatness at the peripheral edge can be improved.

FIG. 9 is a schematic diagram for illustrating the suppression of profile deformation.
As shown in FIG. 9, if the ring-shaped member 200 is provided so as to surround the periphery of the semiconductor wafer W, the condition immediately below the center of the nozzle N can be made symmetric with respect to the nozzle center axis. Therefore, since the deformation of the etching rate E profile can be suppressed, the flatness at the peripheral edge can be improved.

  In this case, the ring-shaped member 200 is preferably made of a material that consumes neutral active species to the same extent as the semiconductor wafer W. By doing so, the symmetry of the profile of the etching rate E can be enhanced. Examples of such materials include silicon, quartz, polycarbonate, and SiC.

  Further, the surface of the ring-shaped member 200 and the surface of the semiconductor wafer W do not necessarily have to be the same height, and there may be a step. However, if the surface of the ring-shaped member 200 and the surface of the semiconductor wafer W have the same height, the gas flow on the main surface of the semiconductor wafer W can be made smooth. Further, the inner peripheral surface of the ring-shaped member 200 and the peripheral edge of the semiconductor wafer W may be brought into close contact with each other, or a certain amount of gap may be provided.

Next, the local plasma processing apparatus according to the embodiment of the present invention is illustrated.
According to the local plasma processing apparatus illustrated below, the main surface of the semiconductor wafer W described above can be locally subjected to plasma etching processing to perform high planarization processing (step 6).

FIG. 10 is a schematic diagram for illustrating the local plasma processing apparatus according to the first embodiment of the present invention.
As shown in FIG. 10, the local plasma processing apparatus 1 is mainly provided with a plasma generating means 2, a decompression chamber 3, a mounting table 4, a control means (not shown), and the like.
The plasma generating means 2 is provided with an introduction waveguide 7, a discharge tube 8, a waveguide 9, a cooling block 10, a gas introduction tube 11, and the like. Note that the cooling block 10 is not necessarily required, and may be provided as appropriate.

  A discharge tube 8 is provided on the ceiling plate of the decompression chamber 3 so as to be substantially perpendicular to the ceiling plate. The discharge tube 8 is provided so that one end protrudes toward the outside of the decompression chamber 3, and the end surface is closed so as to be airtight. The other end is provided so as to protrude toward the mounting surface 4a (the surface on which the semiconductor wafer W is mounted and held) of the mounting table 4 inside the decompression chamber 3, and the end surface is opened. In the present embodiment, the discharge tube 8 functions as the nozzle N described above. For convenience of illustration, the size of the discharge tube 8 is drawn large, but the opening of the discharge tube 8 is made smaller than the size of the portion to be etched (uneven region), and scanning (moving) is performed repeatedly. The portion to be etched is flattened.

  The opening size of the discharge tube 8 is preferably 10 mm or more and 60 mm or less. This is because if the diameter is less than 10 millimeters, the inactivation ratio of the neutral active species supplied from the discharge tube 8 increases and the etching rate decreases. Further, if the diameter exceeds 60 mm, local etching cannot be performed and a problem occurs in flattening.

  A gas introduction tube 11 is provided in the vicinity of the protruding end of the discharge tube 8 outside the decompression chamber 3, and a gas supply means (not shown) is connected to the gas introduction tube 11. An etching gas G 1 can be introduced into the discharge tube 8 through the gas introduction tube 11.

  The discharge tube 8 is inserted so as to be substantially orthogonal to the annular introduction waveguide 7. A waveguide 9 is connected to the introduction waveguide 7, and a microwave generation means (not shown) is connected to the waveguide 9. The introduction waveguide 7 is provided with an annular slot 7 a for radiating the microwave M propagating from a direction substantially orthogonal to the axial direction of the discharge tube 8 toward the inside of the discharge tube 8. Yes. The inside of the discharge tube 8 is also a plasma generation chamber C for generating the plasma P1, but a portion facing the slit 7a is a substantially central region of the plasma generation chamber C.

The cooling block 10 serving as a cooling means is provided so as to surround the outer peripheral surface of the discharge tube 8 around the insertion portion between the discharge tube 8 and the introduction waveguide 7. The cooling block 10 is cooled by circulating cooling water. A gap (for example, about 1 mm) is formed between the cooling block 10 and the discharge tube 8.
An exhaust port 14 is provided on the side wall of the decompression chamber 3, and one end of an exhaust pipe 14 a is connected to the exhaust port 14. An exhaust means EX is connected to the other end of the exhaust pipe 14a.
A mounting table 4 is provided inside the decompression chamber 3. The upper surface of the mounting table 4 is a mounting surface 4a for mounting and holding the semiconductor wafer W. The mounting table 4 is provided with holding means (not shown) (for example, an electrostatic chuck) for holding the semiconductor wafer W. Further, a temperature control means (not shown) (for example, a heater) for controlling the temperature of the semiconductor wafer W may be provided as appropriate. In this case, for example, in order to promote the sublimation of the reaction product by the neutral active species, the semiconductor wafer W may be heated by flowing a heated nitrogen gas or the like from the vicinity of the mounting surface 4a.

The mounting table 4 includes a first table 4b for moving the horizontal plane in the X-axis direction, a second table 4c for moving in the Y-axis direction orthogonal to the X-axis direction, and a vertical direction. And a vertical moving part 4d for moving in the (Z-axis direction). These can be individually controlled in position, and the mounted semiconductor wafer W can be moved to a desired position. It is also possible to provide means for moving and adjusting the rotational direction (θ direction) position of the semiconductor wafer W in the horizontal plane. A ring-shaped member 200 is provided on the mounting surface 4 a of the mounting table 4 so as to surround the periphery of the semiconductor wafer W.
Control means (not shown) controls the relative positions of the plasma generating means 2 (discharge tube 8) and the mounting table 4. That is, the control means (not shown) includes the plasma generating means 2 (discharge tube 8) and the mounting table so that the deformation of the etching rate profile for each region of the semiconductor wafer divided into a plurality of regions by the etching rate profile is suppressed. 4 is controlled. The pressure in the decompression chamber 3, the generation of plasma, the introduction of the etching gas G1, the temperature, and the like are also controlled.

  Here, if the material of the main part is exemplified, the discharge tube 8 can be made of a dielectric material such as alumina and quartz, and the decompression chamber 3 and the like can be made of a metal material such as stainless steel. In this case, the surface of the decompression chamber 3 or the like is preferably coated with a fluorine resin or covered with a fluorine resin member.

Next, the operation of the local plasma processing apparatus 1 will be illustrated.
First, a semiconductor wafer W, which is an object to be processed, is carried into the decompression chamber 3 by a transfer device (not shown) and placed on the placement surface 4 a of the placement table 4. After the transfer device is retracted from the decompression chamber 3, the door (not shown) is closed and the decompression chamber 3 is hermetically sealed. The loaded semiconductor wafer W is held on the mounting surface 4a by an electrostatic chuck (not shown).

  Next, based on the calculation result (in-plane distribution data) of the above-described flatness measurement (step S5), the table 4b, the table 4c, and the table 4b of the mounting table 4 are arranged so that the portion to be flattened is directly under the discharge tube 8. The vertical moving unit 4d is moved.

  At this time, as described above, the in-plane surface of the semiconductor wafer W is divided into a plurality of regions according to the profile of the etching rate E, and an optimum moving method is taken for each of the divided regions. For example, in the central portion where the profile of the etching rate E is symmetric, the relative positions of the discharge tube 8 and the semiconductor wafer W can be moved in a zigzag manner in the radial direction of the semiconductor wafer W. Further, in the peripheral portion where the profile of the etching rate E is asymmetric, the relative positions of the discharge tube 8 and the semiconductor wafer W can be moved along the peripheral edge of the semiconductor wafer W. Further, as described above, the etching rate E at the peripheral portion tends to be high, and therefore the etching conditions are set such that the etching rate E is suppressed as compared with the central portion.

  Control of the relative positions of the plasma generating means 2 and the mounting table 4 is performed by a control means (not shown). The etching conditions can be controlled by controlling the pressure in the decompression chamber 3, the generation of plasma, the introduction of the etching gas G1, the temperature, and the like.

  Next, the inside of the decompression chamber 3 is decompressed to a predetermined pressure by the exhaust means EX. At this time, the pressure in the decompression chamber 3 is adjusted by control means (not shown). Further, the inside of the discharge tube 8 communicating with the decompression chamber 3 is also decompressed.

Next, a predetermined amount of etching gas G1 (for example, SF ₄ or the like) is introduced into the discharge tube 8 through the gas introduction tube 11 from a gas supply means (not shown). A microwave M having a predetermined power is radiated to the waveguide 9 from a microwave generating means (not shown). Then, the microwave M propagating through the waveguide 9 and the introduction waveguide 7 is introduced into the plasma generation chamber C in the discharge tube 8 from the annular slot 7a. Further, cooling water is supplied into the cooling block 10 to cool the discharge tube 8.

  Plasma P1 is generated by the introduced microwave M, and the etching gas G1 is excited and activated to generate neutral active species, ions, and electrons. The generated neutral active species, ions, and electrons descend in the discharge tube 8 and are supplied into the decompression chamber 3. At this time, when ions and electrons collide with the inner wall of the discharge tube 8, they lose their charge and fall as neutral gas or neutral active species. Therefore, ions and electrons are not released from the discharge tube 8, but neutral active species, neutral gas that does not contribute to etching, and the remaining etching gas G 1 are released from the discharge tube 8. And as what contributes to the etching, the neutral active species reaches the decompression chamber 3, and a predetermined portion of the semiconductor wafer W is locally etched. Here, “◯” in the figure represents a neutral active species, “+” represents an ion, and “−” represents an electron.

  In addition, the amount of ions relative to the neutral active species can be adjusted. For example, the amount of neutral active species in the discharge tube 8 can be controlled by changing the output of the microwave M or the pressure in the discharge tube 8 to change the ratio of ions. By doing so, ions can also reach the surface of the semiconductor wafer W. In this case, as described above, it is possible to perform optimum etching in accordance with the shape of the convex portion on the semiconductor wafer W.

  Further, chemical etching by neutral active species can be controlled by controlling the temperature of the semiconductor wafer W by a temperature control means (not shown) provided on the mounting table 4. This is because etching by neutral active species proceeds by a chemical reaction, and generally, the reaction is accelerated as the temperature rises.

  After the flattening of one place is completed, the next flattened place comes directly under the discharge tube 8 based on the calculation result (in-plane distribution data) of the flatness measurement (step S5) described above. The table 4b, the table 4c, and the vertical moving unit 4d of the mounting table 4 are moved. At this time, as described above, an optimum scanning (moving) method is taken for each divided area. When the planarization in one area is completed, the other areas are planarized.

  When the processing on the entire surface of the semiconductor wafer W is completed by the above procedure, the semiconductor wafer W is unloaded from the decompression chamber 3 by a transfer device (not shown). Thereafter, if necessary, another semiconductor wafer W is carried into the decompression chamber 3 and the above-described flattening process is repeated.

FIG. 11 is a schematic diagram for illustrating a local plasma processing apparatus according to the second embodiment of the present invention.
In addition, the same code | symbol is attached | subjected to the part similar to what was illustrated in FIG. 10, and description is abbreviate | omitted suitably.
As shown in FIG. 11A, the local plasma processing apparatus 110 mainly includes an atmospheric pressure plasma generation means 25, a chamber 31, a mounting table 4, a control means (not shown), and the like.

  An atmospheric pressure plasma generating means 25 is provided on the ceiling plate of the chamber 31 so as to be substantially perpendicular to the ceiling plate. The atmospheric pressure plasma generation means 25 is provided so that the jet outlet 25e protrudes toward the mounting surface 4a (the surface on which the semiconductor wafer W is mounted and held) of the mounting table 4 inside the chamber 31. The gas introduction pipe 11 is connected to the introduction port 25d outside the chamber 31 and in the vicinity of the protruding end of the atmospheric pressure plasma generation means 25, and the gas introduction pipe 11 is connected to a gas supply means (not shown). Then, the etching gas G1 can be introduced into the atmospheric pressure plasma generating means 25 through the gas introduction pipe 11.

  For the convenience of illustration, the size of the atmospheric pressure plasma generation means 25 is drawn large, but the nozzle 25e is made smaller than the size of the portion to be etched (uneven region), and repeated scanning (movement) is performed. Thus, the portion to be etched is flattened.

  The opening size of the jet outlet 25e is preferably 10 mm or more and 60 mm or less. This is because if the diameter is less than 10 mm, the ratio of deactivation of the neutral active species supplied from the atmospheric pressure plasma generating means 25 increases and the etching rate decreases. Further, if the diameter exceeds 60 mm, local etching cannot be performed and a problem occurs in flattening.

  A control means (not shown) controls the relative positions of the atmospheric pressure plasma generation means 25 and the mounting table 4. That is, the control means (not shown) includes the atmospheric pressure plasma generation means 25, the mounting table 4 and the mounting table 4 so that the difference in the etching rate profile for each region of the semiconductor wafer W divided into a plurality of parts by the etching rate profile is suppressed. Control the relative position of. Further, the generation of plasma, the introduction of the etching gas G1, the temperature, and the like are controlled.

Next, the outline of the atmospheric pressure plasma generating means 25 will be exemplified.
FIG. 11B is a schematic diagram for illustrating a schematic configuration of the atmospheric pressure plasma generating means 25.
As shown in FIG. 11B, electrodes 25b and 25c are provided on the outer peripheral surface of a discharge tube 25a made of a dielectric material such as alumina or quartz so as to face each other. A high frequency power supply 24 is connected to one electrode 25c through a capacitor 23. The other electrode 25b is grounded. When high frequency power is applied to the electrode 25c, plasma P4 is generated, and this plasma P4 excites and activates the etching gas G1 supplied from the inlet 25d to generate neutral active species, ions, and electrons.

  In addition, a variable power supply 50 is electrically connected to a portion on which the semiconductor wafer W is placed (table 4b in the case of FIG. 5A). The variable power supply 50 controls the amount of ions incident on the semiconductor wafer W by controlling the applied voltage.

Next, the operation of the local plasma processing apparatus 110 will be illustrated.
In addition, about the part similar to the local plasma processing apparatus 1 mentioned above, description is abbreviate | omitted suitably. As in the case of the local plasma processing apparatus 1, after the semiconductor wafer W is loaded, mounted / held, and moved for processing, the above-described atmospheric pressure plasma generation means 25 performs etching gas G 1 (for example, SF _4). Etc.) are excited and activated to generate neutral active species, ions and electrons.

The generated neutral active species locally etch a predetermined portion of the semiconductor wafer W. Further, physical etching is performed by ions. At this time, the amount of incident ions is controlled by the variable power source 50.
Here, “◯” in the figure represents a neutral active species, “+” represents an ion, and “−” represents an electron.

Further, chemical etching by neutral active species can be controlled by controlling the temperature of the semiconductor wafer W by a temperature control means (not shown) provided on the mounting table 4.
As described above, if the neutral active species, ions, and electrons are generated by the atmospheric pressure plasma, a reduced pressure environment is not necessary, and the configuration of the local plasma processing apparatus itself can be simplified.

  The movement of the relative position between the atmospheric pressure plasma generation means 25 and the semiconductor wafer W is the same as that described with reference to FIG.

  Then, after the flattening of one place is completed, the place to be flattened next is the atmospheric pressure plasma generating means 25 based on the calculation result (in-plane distribution data) of the flatness measurement (step S5) described above. The table 4b, the table 4c, and the vertical moving unit 4d of the mounting table 4 are moved so as to come directly below. At this time, as described above, an optimum scanning (moving) method is taken for each divided area. When the planarization in one area is completed, the other areas are planarized.

  When the processing on the entire surface of the semiconductor wafer W is completed by the above procedure, the semiconductor wafer W is unloaded from the decompression chamber 31 by a transfer device (not shown). Thereafter, if necessary, another semiconductor wafer W is carried into the decompression chamber 31 and the above-described flattening process is repeated.

The embodiment of the present invention has been illustrated above. However, the present invention is not limited to these descriptions.
As long as the features of the present invention are provided, those skilled in the art appropriately modified the design of the above-described embodiments are also included in the scope of the present invention.
For example, the shape, size, material, arrangement, and the like of each element provided in the semiconductor wafer flattening device 1 and the semiconductor wafer flattening device 110 are not limited to those illustrated, but can be changed as appropriate.

Further, the plasma generation method is not limited to that described above, and various methods capable of generating high-density plasma can be appropriately selected.
Moreover, each element with which each embodiment mentioned above is combined can be combined as much as possible, and what combined these is also included in the scope of the present invention as long as the characteristics of the present invention are included.

It is a flowchart for demonstrating about the manufacturing method of the semiconductor wafer which concerns on embodiment of this invention. It is a schematic diagram for illustrating the profile of the etching rate directly under the nozzle. It is a schematic diagram for illustrating the profile of the etching rate in the peripheral part of a semiconductor wafer. It is a schematic diagram for demonstrating the mode of the scanning of the nozzle which concerns on a comparative example. It is a schematic diagram for illustrating a mode of scanning of a nozzle concerning this embodiment. It is a schematic diagram for illustrating a mode of scanning of a nozzle concerning this embodiment. It is a mimetic diagram for illustrating the position of the nozzle in a peripheral part. It is a schematic diagram for demonstrating about the improvement of the flatness in a peripheral part. It is a schematic diagram for illustrating about suppression of a deformation | transformation of a profile. It is a schematic diagram for demonstrating about the local plasma processing apparatus which concerns on the 1st Embodiment of this invention. It is a schematic diagram for demonstrating about the local plasma processing apparatus which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,110 Local plasma processing apparatus, 2 Plasma generating means, 3 Depressurization chamber, 4 Mounting stand, 4a Mounting surface, 25 Atmospheric pressure plasma generating means, 31 chamber, 50 Variable power supply, G1 etching gas, M microwave, P1 plasma , W Semiconductor wafer

Claims (12)

An etching gas is excited by plasma to generate a gas containing neutral active species,
A method for planarizing a semiconductor wafer in which the gas is locally supplied to the main surface of the semiconductor wafer to perform local etching,
Divide the surface of the semiconductor wafer into multiple regions with different etching rate profiles,
Planarizing a semiconductor wafer, wherein a position at which the local etching is performed in each of the plurality of regions is determined so that a difference in a profile of the etching rate between the plurality of regions is suppressed. Method.   2. The method for planarizing a semiconductor wafer according to claim 1, wherein a position where the local etching is performed is relatively moved along the periphery of the semiconductor wafer at the periphery of the semiconductor wafer.   3. The gas supply center of the peripheral edge of the semiconductor wafer relatively moves inward from the peripheral edge of the semiconductor wafer by a half-width or more at half maximum of the etching rate profile. For flattening semiconductor wafers.   The central portion of the semiconductor wafer is moved relative to a position where the local etching is performed along a locus formed by a combination of a plurality of straight lines having different directions. A method for planarizing a semiconductor wafer as described in 1. above.   5. The semiconductor wafer flattening method according to claim 4, wherein the trajectory formed by a combination of the plurality of straight lines is a zigzag pattern.   The method for planarizing a semiconductor wafer according to claim 1, wherein an effective etching region in the peripheral edge portion and an effective etching region in the central portion do not overlap each other.   The planarization of a semiconductor wafer according to claim 1, wherein at least one of the local etching at the peripheral portion and the local etching at the central portion is performed. Method.   The method for planarizing a semiconductor wafer according to claim 1, wherein a ring-shaped member is provided so as to surround a periphery of the semiconductor wafer. Plasma generating means for exciting an etching gas with plasma;
A mounting table for mounting a semiconductor wafer;
Control means for controlling the relative position of the plasma generating means and the mounting table;
With
The control means is configured to suppress the difference in the etching rate profile between the plurality of regions of the semiconductor wafer divided into a plurality of regions having different etching rate profiles. A local plasma processing apparatus, characterized by controlling a relative position of the mounting table.   The local plasma processing apparatus according to claim 9, wherein the plasma generating unit is capable of generating plasma under atmospheric pressure.   The local plasma processing apparatus according to claim 9 or 10, wherein the mounting table is provided with a ring-shaped member so as to surround a periphery of the semiconductor wafer. A semiconductor wafer is cut out from a single crystal silicon ingot,
On the periphery of the semiconductor wafer, chamfering is performed to form a chamfered surface,
Polishing the main surface of the semiconductor wafer,
Etching the semiconductor wafer;
A method for producing a semiconductor wafer, comprising: planarizing the semiconductor wafer using the method for planarizing a semiconductor wafer according to claim 1.

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