JP2002016049A - Method of processing semiconductor wafer and plasma etching apparatus - Google Patents
Method of processing semiconductor wafer and plasma etching apparatusInfo
- Publication number
- JP2002016049A JP2002016049A JP2000196937A JP2000196937A JP2002016049A JP 2002016049 A JP2002016049 A JP 2002016049A JP 2000196937 A JP2000196937 A JP 2000196937A JP 2000196937 A JP2000196937 A JP 2000196937A JP 2002016049 A JP2002016049 A JP 2002016049A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- semiconductor wafer
- polishing
- plasma etching
- peripheral portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001020 plasma etching Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 37
- 230000002093 peripheral effect Effects 0.000 claims abstract description 81
- 238000005498 polishing Methods 0.000 claims abstract description 67
- 239000004744 fabric Substances 0.000 claims abstract description 14
- 239000007789 gas Substances 0.000 claims description 21
- 239000002994 raw material Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- 230000001678 irradiating effect Effects 0.000 claims description 9
- 238000003672 processing method Methods 0.000 claims description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 166
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 230000000052 comparative effect Effects 0.000 description 7
- 238000006073 displacement reaction Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000009826 distribution Methods 0.000 description 5
- 238000007517 polishing process Methods 0.000 description 4
- 230000007717 exclusion Effects 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 101150000715 DA18 gene Proteins 0.000 description 1
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008570 general process Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32366—Localised processing
- H01J37/32376—Scanning across large workpieces
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Plasma & Fusion (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体ウエーハの
加工方法及びプラズマエッチング装置、具体的には、半
導体ウエーハの製造工程において、ウエーハ表面全体を
高精度に平坦化する技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer processing method and a plasma etching apparatus, and more particularly, to a technique for flattening the entire surface of a wafer with high precision in a semiconductor wafer manufacturing process.
【０００２】[0002]
【従来の技術】従来、例えば半導体シリコンウエーハの
製造は、図６に一般的な工程の流れを示したように、単
結晶製造装置によって製造された単結晶棒をスライスし
て薄円板状のウエーハを得るスライス工程Ａと、該スラ
イス工程Ａで得られたウエーハの割れや欠けを防ぐため
にその外周エッジ部を面取りする面取り工程Ｂと、面取
りされたウエーハをラッピングしてこれを平坦化するラ
ッピング工程Ｃと、面取りおよびラッピングされたウエ
ーハ表面に残留する加工歪を除去するエッチング工程Ｄ
と、エッチングされたウエーハの表面を研磨布に摺接さ
せて粗研磨する一次鏡面研磨工程Ｅと、一次鏡面研磨さ
れたウエーハの該表面を仕上げ鏡面研磨する仕上げ鏡面
研磨工程Ｆと、仕上鏡面研磨されたウエーハを洗浄して
ウエーハに付着した研磨剤や異物を除去する最終洗浄工
程Ｇから成る。2. Description of the Related Art Conventionally, for example, in the production of a semiconductor silicon wafer, as shown in a general process flow in FIG. 6, a single crystal rod produced by a single crystal production apparatus is sliced to form a thin disk. A slicing step A for obtaining a wafer, a chamfering step B for chamfering an outer peripheral edge portion of the wafer obtained in the slicing step A to prevent cracking or chipping, and lapping for lapping the chamfered wafer and flattening the same. Step C and etching step D for removing processing strain remaining on the chamfered and wrapped wafer surface
A primary mirror polishing step E in which the surface of the etched wafer is brought into sliding contact with a polishing cloth for rough polishing; a finish mirror polishing step F in which the surface of the primary mirror-polished wafer is finish mirror-polished; And a final cleaning step G of cleaning the cleaned wafer to remove abrasives and foreign substances attached to the wafer.
【０００３】前記のような工程を経て得られる鏡面研磨
ウエーハは、中央部分では比較的高い平坦度が達成され
るものの、図７に示されるようにウエーハ外周端部から
５ｍｍ前後の位置からいわゆる周辺ダレが生じる場合が
多い。周辺ダレが生じる原因の１つとしては、一次鏡面
研磨工程Ｅでウエーハを研磨する際、周辺部分の研磨圧
が中央部分より高く、周辺部分が過剰に研磨されてしま
うことにある。[0003] Although the mirror-polished wafer obtained through the above-described process achieves a relatively high flatness at the central portion, as shown in FIG. Sagging often occurs. One of the causes of the peripheral sag is that when the wafer is polished in the primary mirror polishing step E, the peripheral portion has a higher polishing pressure than the central portion, and the peripheral portion is excessively polished.
【０００４】近年、半導体デバイスの高集積化が進み、
回路自体の最小線幅は０．１３μｍ以下のレベルとな
り、リソグラフィプロセスで回路を半導体ウエーハ表面
に形成する際にその焦点深度を確保する目的から、基板
となる半導体ウエーハの表面基準のサイトフラットネス
ＳＦＱＲは、０．１３μｍ以下（サイトサイズ：２５×
３６ｍｍ２）のレベルが要求されている。また、コスト
の観点から１枚の半導体ウエーハからの半導体デバイス
の収率を上げるために、平坦度の保証エリアは、従来外
周端部から３ｍｍ内側領域であったものが、２ｍｍ又は
１ｍｍ内側領域へと拡大している。ここでＳＦＱＲ（Ｓ
ｉｔｅ Ｆｒｏｎｔ ｌｅａｓｔ−ｓＱｕａｒｅｓ Ｒ
ａｎｇｅ）とは、平坦度に関して表面基準の平均平面を
サイト毎に算出し、その面に対する凹凸の最大範囲を表
した値である。In recent years, high integration of semiconductor devices has progressed,
The minimum line width of the circuit itself is 0.13 μm or less, and the site flatness SFQR based on the surface of the semiconductor wafer serving as a substrate is used to secure the depth of focus when the circuit is formed on the surface of the semiconductor wafer by a lithography process. Is 0.13 μm or less (site size: 25 ×
A level of 36 mm 2 ) is required. Further, in order to increase the yield of semiconductor devices from one semiconductor wafer from the viewpoint of cost, the flatness guaranteed area is conventionally 3 mm inward from the outer peripheral edge, but is now reduced to 2 mm or 1 mm inward. It is expanding. Here, SFQR (S
item Front least-sQuares R
The term “ange” is a value that represents the average plane of the surface reference with respect to the flatness, calculated for each site, and represents the maximum range of unevenness with respect to the surface.
【０００５】一方、上記のように近年の最先端の半導体
デバイスの高集積化に対応すべく、ウエーハ全面にわた
って高度な平坦度とすることが要求されている。そのた
め、ウエーハ製造工程中、研磨工程後にプラズマエッチ
ング工程が追加されることがある。このようにすれば、
ウエーハの平坦度（ＴＴＶ：Ｔｏｔａｌ Ｔｈｉｃｋｎ
ｅｓｓ Ｖａｒｉａｔｉｏｎ、すなわちウエーハ全面に
おける最大厚と最小厚の差）を一層向上させることが可
能である。On the other hand, in order to cope with the recent high integration of the most advanced semiconductor devices as described above, it is required to have a high degree of flatness over the entire surface of the wafer. Therefore, during the wafer manufacturing process, a plasma etching process may be added after the polishing process. If you do this,
Wafer flatness (TTV: Total Thickn)
ess Variation, that is, the difference between the maximum thickness and the minimum thickness over the entire surface of the wafer) can be further improved.
【０００６】このプラズマエッチング工程の一実施形態
として、例えば、ＰＡＣＥ（Ｐｌａｓｍａ Ａｓｓｉｓ
ｔｅｄ Ｃｈｅｍｉｃａｌ Ｅｔｃｈｉｎｇ：プラズマ
補助化学エッチング）と呼ばれる技術が開発されている
（例えば、特開平５−１６００７４号公報、特開平６−
５５７１号公報、特開平７−２８８２４９号公報参
照）。As one embodiment of the plasma etching step, for example, PACE (Plasma Assist)
A technique called ted Chemical Etching (plasma-assisted chemical etching) has been developed (for example, Japanese Patent Application Laid-Open Nos. Hei 5-160074 and Hei 6-1994).
5571, and JP-A-7-288249).
【０００７】これはプラズマによりウエーハ表面を部分
的にエッチングしながらウエーハの厚さを均一化する方
法であり、ウエーハの厚さ分布を光学干渉法や静電容量
法で測定した後、その厚さ分布に応じてウエーハ表面に
プラズマを照射するノズルの相対的な移動速度を制御す
ることによりプラズマによるエッチング除去量を制御
し、ウエーハ全面を高平坦度化する技術である。This is a method of making the thickness of a wafer uniform while partially etching the surface of the wafer with plasma. After measuring the thickness distribution of the wafer by an optical interference method or a capacitance method, the thickness is measured. This is a technique for controlling the relative movement speed of a nozzle for irradiating plasma to the wafer surface in accordance with the distribution, thereby controlling the amount of etching removed by the plasma, and making the entire surface of the wafer highly flat.
【０００８】プラズマエッチングの具体的な操作として
は、図１に示すように高周波電極１と接地電極２との間
にシリコンウエーハ等の原料ウエーハＷを置き、高周波
電極１に高周波を印加してノズル３内のＳＦ６等の原料
ガスをプラズマ化して原料ウエーハＷの表面に照射す
る。これによりウエーハ表面のうちノズル３下に位置す
る領域を局所的にエッチングすることができる。したが
って、予め測定した原料ウエーハＷの厚さ分布に応じて
ノズル３あるいは原料ウエーハＷの移動速度を制御しな
がらウエーハＷの表面全体を走査することにより半導体
ウエーハ表面全体を高平坦化することができる。なお、
上記のように原料ガスを高周波電極でプラズマ化する方
法のほか、ノズルにマイクロ波を当ててノズル内の原料
ガスをプラズマ化し、これを原料ウエーハに照射する方
法もある。As a specific operation of plasma etching, a raw material wafer W such as a silicon wafer is placed between a high-frequency electrode 1 and a ground electrode 2 as shown in FIG. The raw material gas such as SF 6 in 3 is turned into plasma and irradiated on the surface of the raw material wafer W. Thereby, a region located below the nozzle 3 on the wafer surface can be locally etched. Therefore, the entire surface of the semiconductor wafer can be highly planarized by scanning the entire surface of the wafer W while controlling the moving speed of the nozzle 3 or the raw wafer W according to the thickness distribution of the raw wafer W measured in advance. . In addition,
In addition to the method of converting the raw material gas into plasma with the high-frequency electrode as described above, there is also a method of applying microwave to the nozzle to convert the raw material gas in the nozzle into plasma and irradiating the raw material wafer with the plasma.
【０００９】しかし、プラズマエッチングを行う場合、
原料ウエーハの形状が凹凸があればあるほどノズルの速
度制御は複雑になり、ノズルの走向距離あるいは加速減
速頻度が増大する。そのため加工時間が長く、不安定な
ものとなり、生産性が低下してしまう。また、ウエーハ
のＴＴＶが悪い場合にも、プラズマエッチングによる除
去量が増え、加工時間が長くなってしまうという問題が
ある。また、前述のように半導体ウエーハには周辺ダレ
が生じている場合が多い上、プラズマエッチングではウ
エーハの周辺部分が過剰にエッチングされる傾向がある
ので、周辺部分まで高い平坦性を達成することは困難で
あるという問題もある。However, when performing plasma etching,
The more irregular the shape of the raw material wafer, the more complicated the speed control of the nozzle, and the greater the traveling distance of the nozzle or the frequency of acceleration / deceleration. Therefore, the processing time is long and unstable, and the productivity is reduced. Also, when the TTV of the wafer is poor, there is a problem that the removal amount by plasma etching increases and the processing time becomes longer. In addition, as described above, the semiconductor wafer often has peripheral sag, and the plasma etching tends to excessively etch the peripheral portion of the wafer. Therefore, it is difficult to achieve high flatness up to the peripheral portion. There is also the problem of difficulty.
【００１０】このような問題に対し、特開平１１−２６
０７７１号公報では、原料ウエーハを凹形状として表面
の凹凸を少なくし、これをプラズマエッチングする技術
を開示している。この技術により、ウエーハ全面にわた
って高い平坦度を達成している。To solve such a problem, Japanese Patent Application Laid-Open No. H11-26
Japanese Patent Application Laid-Open No. 0771 discloses a technique in which a material wafer is formed into a concave shape to reduce surface irregularities, and plasma etching is performed. This technique achieves high flatness over the entire surface of the wafer.
【００１１】[0011]
【発明が解決しようとする課題】従来、ＰＡＣＥで使用
されているノズルの径は少なくとも３ｍｍ〜数十ｍｍま
で様々であるが、小径のノズルを用いてプラズマエッチ
ングを行った場合、加工精度が上がるものの、ウエーハ
全面を走査するのに時間がかかりスループットが低下す
る問題がある。一方、ノズルの径が大きいものほど局所
エッチング領域が大きくなり、スループットを向上させ
ることができるが、ノズル径より小さい範囲のうねり成
分を修正することはできないので、エッチング後に達成
される平坦度が低下し、近年要求されているＳＦＱＲｍ
ａｘ≦０．１３μｍまで達成することは困難である。Conventionally, the diameter of a nozzle used in PACE varies from at least 3 mm to several tens of mm, but when plasma etching is performed using a small-diameter nozzle, processing accuracy is increased. However, there is a problem that it takes time to scan the entire surface of the wafer and the throughput is reduced. On the other hand, the larger the nozzle diameter, the larger the local etching area, which can improve the throughput. However, since the swell component in a range smaller than the nozzle diameter cannot be corrected, the flatness achieved after etching is reduced. The SFQRm required in recent years
It is difficult to achieve ax ≦ 0.13 μm.
【００１２】また、ウエーハ全面をプラズマエッチング
すると、表面が粗くなりヘイズレベルが悪化し、表面の
微小な欠陥密度を検出する際のパーティクル測定が困難
で保証できないという理由から、プラズマエッチング後
に再度研磨代が微少の研磨が必要になり、コストアップ
につながるという問題もある。Further, when plasma etching is performed on the entire surface of the wafer, the surface is roughened, the haze level is deteriorated, and it is difficult to measure particles when detecting minute defect density on the surface. However, there is also a problem that minute polishing is required, which leads to an increase in cost.
【００１３】本発明は上記問題点に鑑みてなされたもの
で、ウエーハ表面全体にわたって高精度に平坦化するこ
とができるとともに、高いスループットで処理すること
ができる半導体ウエーハの加工方法、及びそのような半
導体ウエーハの加工に使用できるプラズマエッチング装
置を提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and a semiconductor wafer processing method capable of flattening the entire surface of a wafer with high precision and processing at a high throughput. It is an object of the present invention to provide a plasma etching apparatus that can be used for processing a semiconductor wafer.
【００１４】[0014]
【課題を解決するための手段】前記目的を達成するた
め、本発明によれば、半導体ウエーハの表面を所定の研
磨圧で研磨布に摺接させて研磨し、該研磨した表面をプ
ラズマエッチングする半導体ウエーハの加工方法におい
て、前記半導体ウエーハの周辺部分の研磨圧を中央部分
より小さくして研磨することにより周辺部分が盛り上が
った形状とし、該周辺部分のみをプラズマエッチングす
ることを特徴とする半導体ウエーハの加工方法が提供さ
れる（請求項１）。According to the present invention, in order to attain the above object, the surface of a semiconductor wafer is polished by being brought into sliding contact with a polishing cloth at a predetermined polishing pressure, and the polished surface is subjected to plasma etching. In the method of processing a semiconductor wafer, the peripheral portion of the semiconductor wafer is polished at a polishing pressure lower than that of a central portion so that the peripheral portion is raised, and only the peripheral portion is plasma-etched. Is provided (claim 1).
【００１５】このように半導体ウエーハを研磨する際、
ウエーハの周辺部分の研磨圧を中央部分より小さくして
周辺部分が盛り上がった形状とし、この盛り上がった周
辺部分のみをプラズマエッチングすれば、ウエーハ全面
にわたって高平坦度を達成することができる上、エッチ
ング時間を大幅に短縮してスループットを向上させるこ
とができる。また、ウエーハ中央部分のヘイズレベルを
悪化させるようなこともなく、プラズマエッチング後の
鏡面研磨も省略することも可能である。When polishing a semiconductor wafer as described above,
If the polishing pressure of the peripheral portion of the wafer is made smaller than that of the central portion so that the peripheral portion is raised, and only the raised peripheral portion is plasma-etched, high flatness can be achieved over the entire surface of the wafer, and the etching time can be increased. Can be greatly shortened and the throughput can be improved. Also, the mirror polishing after the plasma etching can be omitted without deteriorating the haze level in the central portion of the wafer.
【００１６】前記半導体ウエーハのプラズマエッチング
する周辺部分は、該ウエーハの外周端部から５ｍｍ以内
の領域であることが好ましい（請求項２）。前記したよ
うに従来の方法では半導体ウエーハを研磨布に摺接させ
て研磨するとウエーハの中央部分では高平坦度を達成で
きるが、ウエーハ周辺５ｍｍ領域で高平坦度を達成する
ことは困難である。そこで、ウエーハ外周端部から５ｍ
ｍ以内の領域を盛り上がった形状としてこの領域だけを
プラズマエッチングすれば、ウエーハ全面をより効率的
に平坦化でき、エッチング時間を大幅に短縮してスルー
プットを向上させることができるとともに、中央部分の
品質を劣化させることもない。It is preferable that a peripheral portion of the semiconductor wafer to be subjected to plasma etching is a region within 5 mm from an outer peripheral end of the wafer. As described above, in the conventional method, when a semiconductor wafer is slid against a polishing cloth and polished, high flatness can be achieved in the central portion of the wafer, but it is difficult to achieve high flatness in a 5 mm region around the wafer. Therefore, 5m from the outer edge of the wafer
By plasma-etching only the area within the area within m, the entire surface of the wafer can be more efficiently flattened, the etching time can be significantly reduced, and the throughput can be improved. Does not deteriorate.
【００１７】この場合、プラズマエッチングを、径が１
ｍｍ〜２ｍｍの範囲内にあるノズルからプラズマ化した
原料ガスを照射して行うことが好ましい（請求項３）。
このような小径のノズルからプラズマを照射してエッチ
ングを行えば、ウエーハ周辺部分の狭い領域だけを好適
にエッチングすることができる。In this case, the plasma etching is performed with a diameter of 1
It is preferable to perform the irradiation by irradiating a plasma-converted raw material gas from a nozzle having a diameter within a range of 2 mm to 2 mm.
When etching is performed by irradiating plasma from such a small-diameter nozzle, only a narrow region around the wafer can be suitably etched.
【００１８】本発明のプラズマエッチングに用いる原料
ガスは、塩素系、水素系、またはフッ素系のガスとする
ことができる（請求項４）。これらの原料ガスを用いる
ことで、シリコンをはじめとする半導体ウエーハを好適
にエッチングすることができる。The source gas used for the plasma etching of the present invention may be a chlorine-based, hydrogen-based, or fluorine-based gas. By using these source gases, a semiconductor wafer including silicon can be suitably etched.
【００１９】さらに本発明によれば、プラズマ化した原
料ガスをノズルを通じて半導体ウエーハの表面に照射し
てエッチングするプラズマエッチング装置において、前
記ノズルの径が１ｍｍ〜２ｍｍの範囲内にあることを特
徴とするプラズマエッチング装置が提供される（請求項
５）。このような従来に無い小径のノズルを具備するプ
ラズマエッチング装置を用いれば、半導体ウエーハの周
辺部分の狭い領域だけを局所的にエッチングすることが
でき、前記本発明に係る加工方法に好適に使用できる。Further, according to the present invention, in a plasma etching apparatus for performing etching by irradiating a surface of a semiconductor wafer with a source gas converted into plasma through a nozzle, the diameter of the nozzle is within a range of 1 mm to 2 mm. A plasma etching apparatus is provided (claim 5). By using such a plasma etching apparatus having an unprecedented small-diameter nozzle, it is possible to locally etch only a narrow region in the peripheral portion of the semiconductor wafer, which can be suitably used in the processing method according to the present invention. .
【００２０】[0020]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながらさらに具体的に説明するが、本発
明はこれらに限定されるものではない。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described more specifically with reference to the drawings, but the present invention is not limited thereto.
【００２１】まず、研磨されるまでの半導体ウエーハの
製造工程を説明すると、チョクラルスキー法（ＣＺ
法）、浮遊帯域溶融法（ＦＺ法）等によりシリコン等の
原料融液から成長させた半導体インゴットをスライスし
てウエーハとする。次いで、得られたウエーハの粗面取
りとラッピングを行った後、ウエーハ表面の加工歪等を
除去するため、エッチングが行われる。なお、ラッピン
グに代えて平面研削を行う場合もある。First, the steps of manufacturing a semiconductor wafer before polishing will be described. Czochralski method (CZ)
Method), a semiconductor ingot grown from a raw material melt such as silicon by a floating zone melting method (FZ method) or the like is sliced into a wafer. Next, after the obtained wafer is subjected to rough chamfering and lapping, etching is performed to remove a processing distortion or the like on the wafer surface. In some cases, surface grinding may be performed instead of lapping.
【００２２】このような工程を経たウエーハは、表面を
より平坦化及び鏡面化するために表面研磨が施される
が、本発明では、研磨工程でウエーハ周辺部分が盛り上
がった形状とする。The wafer that has undergone such a process is subjected to surface polishing in order to make the surface more flat and mirror-finished. In the present invention, the peripheral portion of the wafer is formed in a raised shape in the polishing process.
【００２３】従来の一般的な研磨方法によりウエーハ裏
面全体を保持板で保持して研磨布に摺接させて研磨する
と、ウエーハ周辺部分が過剰に研磨されて周辺ダレが発
生する場合が多い。そこで、本発明では、半導体ウエー
ハの周辺部分の研磨圧を中央部分より小さくして研磨す
ることにより周辺部分の研磨代を少なくして周辺部分が
盛り上がった形状とする。When the entire back surface of the wafer is held by a holding plate and slid against a polishing cloth by a conventional general polishing method and polished, the peripheral portion of the wafer is excessively polished and peripheral sagging often occurs. Therefore, in the present invention, the peripheral portion of the semiconductor wafer is polished with a lower polishing pressure than that of the central portion, thereby reducing the margin for polishing of the peripheral portion and forming the peripheral portion in a raised shape.
【００２４】周辺部分の研磨圧を小さくする方法は特に
限定されないが、ウエーハの背面（裏面）にウエーハ中
央部分より周辺部分で薄い背面コート膜を形成し、背面
コート膜を介してウエーハ背面を従来の保持板で保持し
てウエーハ表面を研磨する方法やウエーハ周辺部分の押
圧力を中央部分から独立に制御できる研磨ヘッド（保持
板）を用いて研磨する方法などが考えられる。背面部分
の研磨剤のまわり込みや周辺部分を盛り上げる量などを
気にしなければ簡単な方法として、図３で示されるよう
にウエーハＷより小径の保持板６でウエーハＷを保持
し、定盤７上に貼り付けた研磨布８に研磨剤を供給する
とともに、所定の研磨圧（押圧）でウエーハＷを研磨布
８に摺接させて研磨すればよい。このようにウエーハを
保持して研磨を行えば、保持板の保持面からはみ出すウ
エーハ周辺部分の研磨圧は中央部分より小さくなるた
め、その分研磨代も少なくなる。一方、保持板６の保持
面に当接するウエーハＷの中央部分の厚さはほぼ均一と
なって高い平坦度が達成され、研磨後は周辺部分が盛り
上がった形状のウエーハを得ることができる。The method of reducing the polishing pressure in the peripheral portion is not particularly limited, but a thin back coat film is formed on the back surface (rear surface) of the wafer at the peripheral portion from the central portion of the wafer, and the back surface of the wafer is conventionally interposed via the back coat film. And a method of polishing using a polishing head (holding plate) that can control the pressing force at the peripheral portion of the wafer independently of the central portion by holding the wafer with the holding plate. As shown in FIG. 3, as a simple method, the wafer W is held by the holding plate 6 having a smaller diameter than the wafer W, and The polishing agent may be supplied to the polishing cloth 8 attached thereon, and the wafer W may be slid in contact with the polishing cloth 8 at a predetermined polishing pressure (pressing pressure) for polishing. If the wafer is polished while holding the wafer in this manner, the polishing pressure at the peripheral portion of the wafer that protrudes from the holding surface of the holding plate becomes smaller than that at the central portion, so that the polishing allowance is reduced accordingly. On the other hand, the thickness of the central portion of the wafer W that is in contact with the holding surface of the holding plate 6 is substantially uniform, achieving a high flatness, and a wafer having a raised peripheral portion after polishing can be obtained.
【００２５】上記のように研磨して周辺部分が盛り上が
った形状としたウエーハは、次いでその盛り上がった周
辺部分のみを局所的にプラズマエッチングする。従来の
プラズマエッチングでは、予めウエーハ全面の各位置に
おける厚さを光学干渉法で測定し、ウエーハ全体が均一
な厚さとなるようにウエーハ全面を走査して測定値に応
じたエッチングを行っていたが、本発明では周辺の盛り
上がった部分だけをプラズマエッチングする。After the wafer is polished as described above and has a raised peripheral portion, only the raised peripheral portion is locally etched by plasma. In conventional plasma etching, the thickness at each position on the entire surface of the wafer was measured in advance by an optical interference method, and the entire surface of the wafer was scanned so as to have a uniform thickness, and etching was performed according to the measured value. According to the present invention, only the peripheral raised portion is plasma-etched.
【００２６】プラズマエッチングする領域に関しては、
上記のように周辺部分の盛り上がった部分だけを測定値
に応じてエッチングすればよいが、研磨布により研磨す
る際、前記したように小径の保持板等でウエーハを保持
して研磨することで、ウエーハ外周端部から５ｍｍより
ウエーハの内側では優れた平坦度を達成することができ
るので、ウエーハの外周端部から５ｍｍ以内の領域をプ
ラズマエッチングすれば、ウエーハ全面で高い平坦度を
達成することができる。Regarding the region to be plasma etched,
As described above, only the raised portion of the peripheral portion may be etched according to the measured value, but when polishing with a polishing cloth, by holding and polishing the wafer with a small-diameter holding plate or the like as described above, Since excellent flatness can be achieved inside the wafer from 5 mm from the outer peripheral edge of the wafer, high flatness can be achieved over the entire surface of the wafer by plasma etching a region within 5 mm from the outer peripheral edge of the wafer. it can.
【００２７】また、プラズマエッチングに使用するノズ
ルに関しては、従来のもののうち、比較的小径の３ｍｍ
〜５ｍｍ程度の径を有するものを使用することも一応可
能だが、ウエーハ周辺５ｍｍの幅に対してこのような大
きさのノズルを用いたのでは、結局高精度なエッチング
加工が困難である。したがって本発明では、径が１ｍｍ
〜２ｍｍの範囲内にあるノズルからプラズマ化した原料
ガスを照射してプラズマエッチングを行うことで、狭い
面積単位で非常に高精度にエッチングすることができる
上、周辺部分だけのエッチングであるので高いスループ
ットでウエーハを加工することができる。すなわち、本
発明でプラズマエッチングを行う場合、従来のノズル径
より細い、１ｍｍ〜２ｍｍの範囲内の径を有するノズル
を具備したプラズマエッチング装置を用いることで、ウ
エーハ周辺部分のみをより好適にエッチングすることが
できる。また、ノズルの形状については特に限定するも
のではない。上記のように直径が１〜２ｍｍである小径
の円形ノズルの他にも１辺が１〜２ｍｍの長方形のノズ
ル等でもよい。ウエーハ周辺部の外周に沿った形状にす
ることによって効率的に処理することもできる。With respect to the nozzle used for plasma etching, a relatively small nozzle of 3 mm is used.
Although it is possible to use a nozzle having a diameter of about 5 mm, it is difficult to use a nozzle having such a size with respect to the width of 5 mm around the wafer. Therefore, in the present invention, the diameter is 1 mm
By performing plasma etching by irradiating a source gas that has been turned into plasma from a nozzle within a range of up to 2 mm, it is possible to perform etching with very high accuracy in a small area unit, and it is high because only the peripheral portion is etched. Wafers can be processed at a high throughput. That is, when plasma etching is performed in the present invention, by using a plasma etching apparatus having a nozzle having a diameter in the range of 1 mm to 2 mm, which is thinner than the conventional nozzle diameter, only the peripheral portion of the wafer is more preferably etched. be able to. The shape of the nozzle is not particularly limited. In addition to the small-diameter circular nozzle having a diameter of 1 to 2 mm as described above, a rectangular nozzle having a side of 1 to 2 mm may be used. Efficient treatment can be achieved by forming the shape along the outer periphery of the wafer peripheral portion.
【００２８】なお、原料ガスをプラズマ化する方法とし
ては特に限定されず、ノズルと一体となった高周波電極
に高周波を印加する方式、あるいはマイクロ波をノズル
に当てる方式等のいずれの方式も採用することができ
る。図２は、本発明にかかる装置を用いてウエーハの周
辺部分のみをプラズマエッチングする場合の一例の概略
を示している。研磨により周辺部分が盛り上がった形状
の原料ウエーハＷを回転テーブル４上に静電チャックで
固定して回転させるとともに、照射口の径が１〜２ｍｍ
のノズル５にマイクロ波を当てて原料ガスをプラズマ化
し、これをウエーハＷの周辺部分だけに照射させること
で容易にウエーハ周辺部分のみをエッチングすることが
できる。The method for converting the raw material gas into plasma is not particularly limited, and any method such as a method of applying a high frequency to a high-frequency electrode integrated with the nozzle or a method of applying a microwave to the nozzle is employed. be able to. FIG. 2 schematically shows an example of a case where only the peripheral portion of a wafer is subjected to plasma etching using the apparatus according to the present invention. The raw material wafer W whose peripheral portion is raised by polishing is fixed on the rotating table 4 by an electrostatic chuck and rotated, and the diameter of the irradiation port is 1 to 2 mm.
The raw material gas is turned into plasma by irradiating the nozzle 5 with a microwave, and this is irradiated only to the peripheral portion of the wafer W, so that only the peripheral portion of the wafer W can be easily etched.
【００２９】本発明でプラズマエッチングする際に使用
する原料ガスとしては、従来使用しているものを限定す
ることなく使用できるが、具体的には、ＣＣｌ４等の塩
素系、Ｈ２等の水素系、またはＳＦ６等のフッ素系のガ
スを使用でき、特に、シリコンウエーハを加工する場合
には、ＳＦ６を好適に使用できる。As the raw material gas used for plasma etching in the present invention, any conventionally used gas can be used without limitation, and specifically, a chlorine-based gas such as CCl 4 or a hydrogen gas such as H 2 may be used. Or a fluorine-based gas such as SF 6 can be used. Particularly, when processing a silicon wafer, SF 6 can be suitably used.
【００３０】本発明によれば、原料ウエーハを高いスル
ープットで加工し、周辺部分まで非常に優れた平坦度の
鏡面ウエーハを提供することができるので、ウエーハの
生産性及び良品率を著しく向上させることができる。ま
た、このようなウエーハを用いることで表面全体に回路
を形成させることができ、半導体デバイスの生産性及び
歩留りを著しく向上させることができる。また、周辺部
分だけをプラズマエッチングするので、研磨面全体のヘ
イズレベルはほとんど低下せず、プラズマエッチング後
にヘイズを除去するための鏡面研磨等を行う必要も無
い。According to the present invention, a raw wafer can be processed at a high throughput and a mirror-finished wafer having a very excellent flatness can be provided up to the peripheral portion, so that the productivity and the yield rate of the wafer can be significantly improved. Can be. Further, by using such a wafer, a circuit can be formed on the entire surface, and the productivity and yield of semiconductor devices can be significantly improved. Further, since only the peripheral portion is plasma-etched, the haze level of the entire polished surface hardly decreases, and there is no need to perform mirror polishing or the like for removing haze after plasma etching.
【００３１】[0031]
【実施例】以下、実施例及び比較例を示して本発明をよ
り具体的に説明するが、本発明はこれらに限定されるも
のではない。 （実施例１）インゴットをスライスして得たシリコンウ
エーハ（径：２００ｍｍ）をウエーハ周辺部分の研磨圧
力が調節できる研磨ヘッド（保持板）を用い吸着保持
し、ウエーハ周辺部（特に外周端部から３ｍｍ）を中心
部より弱い圧力で保持し、ウエーハ表面を研磨布に摺接
させて研磨を行うことで鏡面研磨ウエーハ（ＳＦＱＲｍ
ａｘ：０．２０μｍ）を得た。ＳＦＱＲｍａｘとは、ウ
エーハ上の全サイトのＳＦＱＲの中の最大値を表してい
る。この鏡面研磨ウエーハの外周端部から１２ｍｍ以内
の領域の厚さを測定し、測定値に基づいてプラズマエッ
チングした。なお、厚さ測定を周辺部分のみとした結
果、測定にかかる時間も、ウエーハ全面を測定する場合
に比べ短縮することができた。EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples, but the present invention is not limited to these examples. (Example 1) A silicon wafer (diameter: 200 mm) obtained by slicing an ingot was suction-held by using a polishing head (holding plate) capable of adjusting a polishing pressure at a peripheral portion of the wafer, and the peripheral portion of the wafer (particularly from the outer peripheral end portion). 3 mm) is held at a pressure lower than that of the central portion, and the wafer surface is slid against a polishing cloth to perform polishing, thereby obtaining a mirror-polished wafer (SFQRm).
ax: 0.20 μm). SFQRmax represents the maximum value among SFQRs of all sites on a wafer. The thickness of a region within 12 mm from the outer peripheral edge of the mirror-polished wafer was measured, and plasma etching was performed based on the measured value. In addition, as a result of measuring the thickness only in the peripheral portion, the time required for the measurement could be shortened as compared with the case where the entire surface of the wafer was measured.
【００３２】プラズマエッチング前（原料形状）と後
（加工後形状）のウエーハ周辺部分の厚さ変位量（除外
領域：周辺２ｍｍ）を静電容量式厚さ測定器を用いて測
定し、結果を図４に示した。The thickness displacement (exclusion area: 2 mm around the periphery) of the peripheral portion of the wafer before (the shape of the raw material) and after (the shape after the processing) the plasma etching is measured using a capacitance type thickness measuring instrument. As shown in FIG.
【００３３】図４に示されているように、プラズマエッ
チング後のウエーハ周辺部分の厚さは、周辺部分の除外
領域に至るまで平坦化されていると同時に、狭い範囲内
での平坦度を示すＳＦＱＲｍａｘも研磨後の０．２０μ
ｍから０．０５μｍに大幅に改善されていることがわか
る。As shown in FIG. 4, the thickness of the peripheral portion of the wafer after the plasma etching is flattened to the exclusion region of the peripheral portion, and at the same time, shows the flatness within a narrow range. SFQRmax is also 0.20μ after polishing
It can be seen that it is greatly improved from m to 0.05 μm.
【００３４】（実施例２）インゴットをスライスして得
たシリコンウエーハ（径：２００ｍｍ）をウエーハ周辺
部分の研磨圧力が調節できる研磨ヘッド（保持板）を用
い吸着保持し、ウエーハ周辺部（特に外周端部から３ｍ
ｍ）を中心部より弱い圧力で保持し、ウエーハ表面を研
磨布に摺接させて研磨を行うことで鏡面研磨ウエーハ
（ＳＦＱＲｍａｘ：０．２０μｍ）を得た。この鏡面研
磨ウエーハの研磨した面のうち、ウエーハ外周端部から
５ｍｍ以内の領域の厚さを測定し、測定値に基づいてプ
ラズマエッチングした。(Example 2) A silicon wafer (diameter: 200 mm) obtained by slicing an ingot is suction-held by using a polishing head (holding plate) capable of adjusting a polishing pressure at a peripheral portion of the wafer, and is held at a peripheral portion of the wafer (particularly at an outer periphery). 3m from end
m) was held at a pressure lower than the center, and the wafer surface was slid against a polishing cloth to perform polishing, thereby obtaining a mirror-polished wafer (SFQRmax: 0.20 μm). Of the polished surface of this mirror-polished wafer, the thickness of a region within 5 mm from the outer peripheral edge of the wafer was measured, and plasma etching was performed based on the measured value.
【００３５】プラズマエッチング前（原料形状）と後
（加工後形状）のウエーハ周辺部分の厚さ分布（除外領
域：周辺２ｍｍ）を静電容量式厚さ測定器を用いて測定
し、結果を図５に示した。なお、エッチング時間は１０
秒であった。また、ウエーハ表面のヘイズレベルをパー
ティクルカウンター（ＬＳ−６０００ ＰＭＴＨＶ＝９
００Ｖ換算）を用いて測定した。The thickness distribution (exclusion area: 2 mm around the periphery) of the peripheral portion of the wafer before (the shape of the raw material) and after (the shape after the processing) the plasma etching was measured using a capacitance type thickness measuring instrument. 5 is shown. The etching time is 10
Seconds. Further, the haze level of the wafer surface was measured by a particle counter (LS-6000 PMTHV = 9).
(In terms of 00 V).
【００３６】（比較例）実施例２と同様にシリコンウエ
ーハの鏡面研磨を行い、鏡面研磨ウエーハ（ＳＦＱＲｍ
ａｘ：０．２０μｍ）を得た。電極径５０ｍｍのプラズ
マエッチング装置を用い、鏡面研磨ウエーハの研磨した
面全体をプラズマエッチングし（エッチング時間：５０
秒）、実施例２と同様にウエーハ周辺部分の厚さ分布と
ヘイズレベルを測定した。Comparative Example A mirror-polished silicon wafer was prepared in the same manner as in Example 2 to obtain a mirror-polished wafer (SFQRm
ax: 0.20 μm). Plasma etching is performed on the entire polished surface of the mirror-polished wafer using a plasma etching apparatus having an electrode diameter of 50 mm (etching time: 50 hours).
Seconds), the thickness distribution and the haze level of the peripheral portion of the wafer were measured as in Example 2.
【００３７】図５は、実施例２のプラズマエッチング前
後、及び比較例の各ウエーハの周辺部分の厚さ変位量を
外周端部から１０ｍｍの位置を基準として示したグラフ
である。この図から、比較例で得られたウエーハは一見
実施例２のウエーハよりも平坦度が改善されているよう
に見えるが、ウエーハ外周端部から約４ｍｍと８ｍｍの
位置に変異点があり、ＳＦＱＲｍａｘは０．１５μｍと
いう大きい値を示している。一方、実施例２で得られた
ウエーハは、外周端部から１０ｍｍ以内の領域での厚さ
変位量が比較例より大きいが変位点がなく、ＳＦＱＲｍ
ａｘは０．０７μｍという小さい値を示し、局所的な領
域の平坦度が大幅に改善されている。FIG. 5 is a graph showing the amount of thickness displacement before and after plasma etching in Example 2 and in the peripheral portion of each wafer of the comparative example with reference to a position 10 mm from the outer peripheral edge. From this figure, it can be seen that the flatness of the wafer obtained in the comparative example is apparently improved compared to the wafer of the second embodiment, but there are mutation points at about 4 mm and 8 mm from the outer peripheral edge of the wafer, and SFQRmax Indicates a large value of 0.15 μm. On the other hand, the wafer obtained in Example 2 has a larger thickness displacement in a region within 10 mm from the outer peripheral end than the comparative example, but has no displacement point, and the SFQRm
ax shows a small value of 0.07 μm, and the flatness of the local region is greatly improved.
【００３８】また、ウエーハ表面のヘイズレベルについ
ては、実施例２では４０ビットという小さい値であった
のに対し、比較例では１０４ビットという高い値を示
し、ヘイズを除去する研磨をしなければ使用できないも
のであった。[0038] Also, the haze level of the wafer surface, while was small value of 40 bits in the second embodiment, a high value of 10 4-bit in the comparative example, unless the abrasive to remove the haze It could not be used.
【００３９】なお、本発明は、上記実施形態に限定され
るものではない。上記実施形態は単なる例示であり、本
発明の特許請求の範囲に記載された技術的思想と実質的
に同一な構成を有し、同様な作用効果を奏するものは、
いかなるものであっても本発明の技術的範囲に包含され
る。The present invention is not limited to the above embodiment. The above embodiment is merely an example, and has substantially the same configuration as the technical idea described in the claims of the present invention, and has the same function and effect,
Anything is included in the technical scope of the present invention.
【００４０】例えば、前記実施の形態ではシリコンウエ
ーハを加工する場合を例に説明したが、本発明が適用で
きる半導体ウエーハはこれに限定されず、ＳＯＩウエー
ハのほか、シリコン以外の材質からなる半導体ウエーハ
に対しても適用できる。また、ウエーハの大きさに関し
ても特に限定されるものではなく、本発明は大口径のウ
エーハほど有効である。また、ウエーハ周辺部分を盛り
上がった形状とする方法は特に限定されず、実施例のよ
うに研磨ヘッドによって周辺部と中心部の加工圧力を別
々に調整する方法以外にも、ウエーハ保持部分がウエー
ハ径よりも小径の研磨ヘッドを使用し研磨する方法や、
ウエーハ裏面に樹脂等の保護膜をコーティングして、そ
の周辺部のみコーティングする厚さを薄くし、ウエーハ
裏面を吸着保持して研磨することなどでもウエーハ周辺
部分が盛り上がった形状に加工することができる。For example, in the above-described embodiment, a case where a silicon wafer is processed has been described as an example. However, the semiconductor wafer to which the present invention can be applied is not limited to this. In addition to an SOI wafer, a semiconductor wafer made of a material other than silicon is used. It can also be applied to The size of the wafer is not particularly limited, and the present invention is more effective for a wafer having a larger diameter. The method of forming the peripheral portion of the wafer into a raised shape is not particularly limited. In addition to the method of separately controlling the processing pressure of the peripheral portion and the central portion by the polishing head as in the embodiment, the wafer holding portion may have a wafer diameter. Polishing method using a smaller diameter polishing head,
By coating the back surface of the wafer with a protective film such as a resin, and coating only the peripheral portion of the wafer, reducing the thickness, and holding the back surface of the wafer by suction and polishing, the wafer peripheral portion can be processed into a raised shape. .
【００４１】また、研磨工程後にプラズマエッチング工
程を追加するが、本発明のプラズマエッチングは、研磨
工程後、つまり仕上げ鏡面研磨工程後に行っても、多段
研磨の１次鏡面研磨後に行っても良い。これらの研磨に
よりウエーハ周辺部分を盛り上がった形状にした後、プ
ラズマエッチングを行うことにより高平坦度なウエーハ
に加工できる。In addition, a plasma etching step is added after the polishing step. The plasma etching of the present invention may be performed after the polishing step, that is, after the finishing mirror polishing step, or after the primary mirror polishing of the multi-step polishing. After the wafer is polished to form a raised portion around the wafer, the wafer can be processed into a highly flat wafer by performing plasma etching.
【００４２】[0042]
【発明の効果】以上説明したように、本発明では、半導
体ウエーハの周辺部分の研磨圧を中央部分より小さくし
て研磨布に摺接させて研磨することにより周辺部分が盛
り上がった形状とし、次いで、研磨した表面を周辺部分
のみをプラズマエッチングすることによりウエーハの周
辺部分まで優れた平坦度を達成することができる。ま
た、従来のようにウエーハ全面を走査してプラズマエッ
チングする必要が無く、ヘイズレベルを改善するための
鏡面研磨も必要無いため、高いスループットでウエーハ
を加工することができる。本発明により得られた鏡面ウ
エーハは、周辺部分も含めた表面全体に回路を形成させ
ることができ、半導体デバイスの生産性及び歩留りを向
上させることができる。As described above, according to the present invention, the polishing pressure at the peripheral portion of the semiconductor wafer is made smaller than that at the central portion, and the peripheral portion is slid into contact with the polishing cloth to be polished, so that the peripheral portion is raised. By performing plasma etching only on the peripheral portion of the polished surface, excellent flatness can be achieved up to the peripheral portion of the wafer. Also, unlike the conventional case, it is not necessary to scan the entire surface of the wafer and perform plasma etching, and it is not necessary to perform mirror polishing for improving the haze level. Therefore, the wafer can be processed with high throughput. With the mirror-finished wafer obtained by the present invention, a circuit can be formed on the entire surface including the peripheral portion, and the productivity and yield of semiconductor devices can be improved.
【図面の簡単な説明】[Brief description of the drawings]
【図１】プラズマエッチングの一例を示す概略図であ
る。FIG. 1 is a schematic view showing an example of plasma etching.
【図２】本発明に係る装置を用いてウエーハの周辺部分
だけをプラズマエッチングする一例の概略図である。FIG. 2 is a schematic view showing an example of plasma etching only a peripheral portion of a wafer using the apparatus according to the present invention.
【図３】ウエーハより小径の保持板でウエーハを保持し
て研磨する概略を示す図である。FIG. 3 is a view schematically showing polishing of a wafer held by a holding plate having a diameter smaller than that of the wafer.
【図４】実施例１のプラズマエッチング前後に測定した
ウエーハの周辺部分の厚さの変位量を示すグラフであ
る。FIG. 4 is a graph showing the amount of displacement of the thickness of a peripheral portion of a wafer measured before and after plasma etching in Example 1.
【図５】実施例２及び比較例で測定したウエーハの周辺
部分の厚さの変位量を示すグラフである。FIG. 5 is a graph showing the amount of displacement of the thickness of the peripheral portion of the wafer measured in Example 2 and Comparative Example.
【図６】従来の半導体ウエーハの一般的な製造工程を示
した流れ図である。FIG. 6 is a flowchart showing a general manufacturing process of a conventional semiconductor wafer.
【図７】従来の研磨工程においてウエーハを研磨布で研
磨した後の周辺部分の厚さの変位量を示すグラフであ
る。FIG. 7 is a graph showing a displacement amount of a thickness of a peripheral portion after a wafer is polished with a polishing cloth in a conventional polishing process.
１…高周波電極、 ２…接地電極、 ３…ノズル、 ４
…回転テーブル、 ５…ノズル、 ６…保持板、 ７…
定盤、 ８…研磨布、 Ｗ…ウエーハ。1: High frequency electrode, 2: Ground electrode, 3: Nozzle, 4
... Rotating table, 5 ... Nozzle, 6 ... Holding plate, 7 ...
Surface plate, 8: polishing cloth, W: wafer.
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5F004 AA11 BA20 BB28 BD07 DA05 DA18 DA24 DB01 FA08 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F004 AA11 BA20 BB28 BD07 DA05 DA18 DA24 DB01 FA08
Claims (5)
研磨布に摺接させて研磨し、該研磨した表面をプラズマ
エッチングする半導体ウエーハの加工方法において、前
記半導体ウエーハの周辺部分の研磨圧を中央部分より小
さくして研磨することにより周辺部分が盛り上がった形
状とし、該周辺部分のみをプラズマエッチングすること
を特徴とする半導体ウエーハの加工方法。In a semiconductor wafer processing method, a surface of a semiconductor wafer is polished by sliding the surface of the semiconductor wafer against a polishing cloth at a predetermined polishing pressure, and the polished surface is plasma-etched. A method for processing a semiconductor wafer, wherein a peripheral portion is raised by polishing smaller than a central portion, and only the peripheral portion is plasma-etched.
グする周辺部分が、該ウエーハの外周端部から５ｍｍ以
内の領域であることを特徴とする請求項１に記載の半導
体ウエーハの加工方法。2. The semiconductor wafer processing method according to claim 1, wherein a peripheral portion of the semiconductor wafer to be subjected to plasma etching is a region within 5 mm from an outer peripheral end of the wafer.
〜２ｍｍの範囲内にあるノズルからプラズマ化した原料
ガスを照射して行うことを特徴とする請求項１または請
求項２に記載の半導体ウエーハの加工方法。3. The plasma etching method according to claim 1, wherein the diameter is 1 mm.
3. The method for processing a semiconductor wafer according to claim 1, wherein the method is carried out by irradiating a plasma-converted raw material gas from a nozzle having a diameter of about 2 mm.
スが、塩素系、水素系、またはフッ素系のガスであるこ
とを特徴とする請求項１ないし請求項３のいずれか１項
に記載の半導体ウエーハの加工方法。4. The semiconductor wafer according to claim 1, wherein a source gas used for the plasma etching is a chlorine-based gas, a hydrogen-based gas, or a fluorine-based gas. Processing method.
て半導体ウエーハの表面に照射してエッチングするプラ
ズマエッチング装置において、前記ノズルの径が１ｍｍ
〜２ｍｍの範囲内にあることを特徴とするプラズマエッ
チング装置。5. A plasma etching apparatus for irradiating a surface of a semiconductor wafer with a plasma of a source gas through a nozzle to perform etching, wherein the diameter of the nozzle is 1 mm.
A plasma etching apparatus characterized by being within a range of 2 mm to 2 mm.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000196937A JP2002016049A (en) | 2000-06-29 | 2000-06-29 | Method of processing semiconductor wafer and plasma etching apparatus |
| PCT/JP2001/005402 WO2002001617A1 (en) | 2000-06-29 | 2001-06-25 | Semiconductor wafer processing method and plasma etching apparatus |
| TW90115795A TW527663B (en) | 2000-06-29 | 2001-06-28 | Processing method of semiconductor wafer and plasma etching apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000196937A JP2002016049A (en) | 2000-06-29 | 2000-06-29 | Method of processing semiconductor wafer and plasma etching apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002016049A true JP2002016049A (en) | 2002-01-18 |
Family
ID=18695355
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000196937A Pending JP2002016049A (en) | 2000-06-29 | 2000-06-29 | Method of processing semiconductor wafer and plasma etching apparatus |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2002016049A (en) |
| TW (1) | TW527663B (en) |
| WO (1) | WO2002001617A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004235478A (en) * | 2003-01-30 | 2004-08-19 | Sumitomo Mitsubishi Silicon Corp | Stacked soi substrate and its manufacturing method |
| JP2009253133A (en) * | 2008-04-09 | 2009-10-29 | Shibaura Mechatronics Corp | Method of planarizing semiconductor wafer, local plasma treatment apparatus, and method of manufacturing semiconductor wafer |
| JP2014150284A (en) * | 2014-04-24 | 2014-08-21 | Shibaura Mechatronics Corp | Local plasma processing apparatus |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7323080B2 (en) | 2004-05-04 | 2008-01-29 | Semes Co., Ltd. | Apparatus for treating substrate |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0750234A (en) * | 1993-08-04 | 1995-02-21 | Komatsu Electron Metals Co Ltd | Semiconductor wafer manufacturing device and method |
| JP3629862B2 (en) * | 1996-12-24 | 2005-03-16 | セイコーエプソン株式会社 | Unnecessary object removal method and apparatus for substrate periphery |
| JP3444183B2 (en) * | 1998-03-13 | 2003-09-08 | 信越半導体株式会社 | Method of manufacturing semiconductor wafer and semiconductor wafer manufactured by this method |
| JPH11302878A (en) * | 1998-04-21 | 1999-11-02 | Speedfam-Ipec Co Ltd | Wafer planatarization method, wafer planatarization system and wafer |
| JP2000031127A (en) * | 1998-07-13 | 2000-01-28 | Sumitomo Metal Ind Ltd | Method and device for flattening wafer |
-
2000
- 2000-06-29 JP JP2000196937A patent/JP2002016049A/en active Pending
-
2001
- 2001-06-25 WO PCT/JP2001/005402 patent/WO2002001617A1/en active Application Filing
- 2001-06-28 TW TW90115795A patent/TW527663B/en active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004235478A (en) * | 2003-01-30 | 2004-08-19 | Sumitomo Mitsubishi Silicon Corp | Stacked soi substrate and its manufacturing method |
| JP2009253133A (en) * | 2008-04-09 | 2009-10-29 | Shibaura Mechatronics Corp | Method of planarizing semiconductor wafer, local plasma treatment apparatus, and method of manufacturing semiconductor wafer |
| JP2014150284A (en) * | 2014-04-24 | 2014-08-21 | Shibaura Mechatronics Corp | Local plasma processing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| TW527663B (en) | 2003-04-11 |
| WO2002001617A1 (en) | 2002-01-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4192482B2 (en) | Silicon wafer manufacturing method | |
| JP3169120B2 (en) | Method for manufacturing semiconductor mirror-surface wafer | |
| US6200908B1 (en) | Process for reducing waviness in semiconductor wafers | |
| KR101002250B1 (en) | Method for manufacturing epitaxial wafer | |
| US20020187595A1 (en) | Methods for silicon-on-insulator (SOI) manufacturing with improved control and site thickness variations and improved bonding interface quality | |
| WO2011077661A1 (en) | Semiconductor wafer, and method for producing same | |
| JP3828176B2 (en) | Manufacturing method of semiconductor wafer | |
| JP3982336B2 (en) | Semiconductor wafer processing method and plasma etching apparatus | |
| JP2002016049A (en) | Method of processing semiconductor wafer and plasma etching apparatus | |
| JP4103808B2 (en) | Wafer grinding method and wafer | |
| JP2003163335A (en) | Method for producing laminated wafer | |
| JP2001085648A (en) | Method for manufacturing bonding wafer and bonding wafer | |
| JP2004022677A (en) | Semiconductor wafer | |
| JP2004063883A (en) | Method for manufacturing semiconductor wafer | |
| JP2003142434A (en) | Method of manufacturing mirror-surface wafer | |
| KR101086966B1 (en) | Grinding Process of Semiconductor Wafer | |
| JP2009027095A (en) | Method of evaluating semiconductor wafer, method of grinding semiconductor wafer, and method of processing semiconductor wafer | |
| JP2002329690A (en) | Semiconductor wafer manufacturing method | |
| JP7078005B2 (en) | Silicon wafer flattening method | |
| JP3444183B2 (en) | Method of manufacturing semiconductor wafer and semiconductor wafer manufactured by this method | |
| JP2002176013A (en) | Method for flattening semiconductor substrate | |
| JP2001044154A (en) | Manufacture of semiconductor wafer | |
| JP3596363B2 (en) | Manufacturing method of semiconductor wafer | |
| JP3959877B2 (en) | Manufacturing method of bonded dielectric isolation wafer | |
| JP3916212B2 (en) | Manufacturing method of semiconductor wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050329 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050527 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20060110 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060307 |