JP2009027095A - Method of evaluating semiconductor wafer, method of grinding semiconductor wafer, and method of processing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of evaluating semiconductor wafers, which is capable of evaluating nanotopography of a surface of a semiconductor wafer with a high precision without mirror surface grinding of the semiconductor wafer. <P>SOLUTION: The method of evaluating semiconductor wafers, which evaluates nanotopography of a surface of a semiconductor wafer before a grinding step, includes: a step S4 of using a surface shape measuring means to measure a surface shape of a region having predetermined dimensions from an outer peripheral end part to the inside of the semiconductor wafer before the grinding step in a free state of not making a force act thereon; a step S5 of obtaining an approximation function representing a curve which gives an end part surface shape of the semiconductor wafer, on the basis of measurement results of the surface shape measuring means; and a step S6 of calculating an amount of warpage of he region having the predetermined dimensions from the outer peripheral end part to the inside of the semiconductor wafer, on the basis of the obtained approximation function and evaluating nanotopography of the semiconductor wafer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer evaluation method, a semiconductor wafer surface grinding method, and a semiconductor wafer processing method.

When manufacturing a semiconductor wafer such as a silicon wafer, a semiconductor ingot pulled up by the Czochralski method or the like is cut and sliced with a wire saw or the like and processed into a thin disk-shaped semiconductor wafer.
Next, the outer peripheral edge of the semiconductor wafer is chamfered, and the front and back surfaces of the semiconductor wafer are ground simultaneously by lapping. Further, after grinding one surface at a time, processing strain remaining on the surface layer of the semiconductor wafer is removed by etching.
Finally, the surface of the semiconductor wafer is mirror-finished by CMP or the like, and contaminants such as abrasives and foreign matters attached by polishing are removed by cleaning.
Further, in addition to these processes, processes such as heat treatment and grinding may be added as necessary, the process order may be changed, and the same process may be performed multiple times.

In recent years, with the high integration of semiconductor devices, the quality of the surface roughness (fine undulation) of a semiconductor wafer is emphasized, and nanotopography is used as a parameter representing such surface roughness.
Conventionally, this nanotopography can be measured with a nanotopography measuring device such as Nanomapper made by ADE, NanoPro made by Raytex, etc., but these devices are optical and measure using surface reflection on the surface of a semiconductor wafer. Therefore, measurement cannot be performed unless the surface of the semiconductor wafer is made close to a mirror surface.
On the other hand, as a method for evaluating the nanotopography of a semiconductor wafer at the initial stage of the manufacturing stage, the inclination of the change in warpage of the semiconductor wafer based on the center in the thickness direction of the semiconductor wafer from the cross-sectional shape of the semiconductor wafer before polishing. There is known a method for obtaining the maximum value of the nanotopography and evaluating the nanotopography based on the obtained maximum value (see, for example, Patent Document 1).
Here, in the method of Patent Document 1, the cross section of the semiconductor wafer is divided into a plurality of data sections along the cutting direction, and the cross-sectional shape of each data section is smoothed by a moving average method or the like, and then warped. The maximum value of the slope of change is obtained.

JP 2006-294774 A

  However, the method of Patent Document 1 has a problem that nanotopography cannot always be evaluated with high accuracy because there is data deleted by moving average.

  An object of the present invention is to provide a semiconductor wafer evaluation method, a semiconductor wafer surface grinding method, and a semiconductor wafer processing capable of evaluating nanotopography of a semiconductor wafer surface with high accuracy without performing mirror polishing of the semiconductor wafer. It is to provide a method.

The method for evaluating a semiconductor wafer according to the present invention includes:
A semiconductor wafer evaluation method for evaluating nanotopography of a semiconductor wafer surface of a semiconductor wafer before a polishing step,
Using a surface shape measuring means, in a free state in which no force is applied, a procedure for measuring the surface shape of a region of a constant dimension inside from the outer peripheral edge of the semiconductor wafer after the grinding step;
A procedure for obtaining an approximate function representing a curve that gives an end surface shape of the semiconductor wafer based on a measurement result by the surface shape measuring means;
Based on the obtained approximate function, a warping amount of a region having a fixed dimension inside from the end of the semiconductor wafer is calculated, and a procedure for evaluating nanotopography of the semiconductor wafer is performed.

Here, as the surface shape measurement means, a laser displacement meter, a stylus shape measurement device, a capacitance type shape measurement device, or the like can be employed.
Semiconductor wafers are ground after double-sided rough grinding such as lapping, double-sided grinding, surface grinding, double-sided grinding, etc., and then chucking one surface of the semiconductor wafer by vacuum suction or the like to perform single-sided surface grinding. Then, final double-side polishing and finish polishing are performed to finish the mirror-polished state.
When this mirror-finished semiconductor wafer is measured by the above-described nanotopography measuring apparatus, a semiconductor wafer with good nanotopography is observed in a state with less shading as shown in the map of FIG.
On the other hand, as shown in the map of FIG. 2, a ring-shaped shading appears on a semiconductor wafer with poor nanotopography.

Nanotopography measurement originally evaluates minute irregularities on the surface of a semiconductor wafer, but when the shape change of the surface of the semiconductor wafer is large, this affects the nanotopography.
That is, the ring-shaped shading is caused by a large change in the surface shape of the semiconductor wafer. As shown in FIG. 3, the semiconductor wafer W1 having a high flatness in the ground state is good. As shown in FIG. 4, there is a knowledge that the semiconductor wafer W <b> 2 having a low flatness and a warped surface shape in a ground state tends to generate ring-shaped shading as shown in FIG. 4. Obtained.
This large change in the surface shape of the semiconductor wafer is caused by the fact that the reference surface of chucking due to vacuum suction is grounded by single-side grinding after double-sided grinding by lapping and other grinding processes. It is caused by being transferred to.

According to this invention, since the nanotopography can be measured in the grinding process of the semiconductor wafer, the shape change of the outer peripheral end portion of the semiconductor wafer can be performed after mirror polishing of the semiconductor wafer as in the prior art, without measuring with the nanotopography measuring device. Therefore, it is possible to selectively polish only a semiconductor wafer having a good nanotopography, and the manufacturing yield of a semiconductor wafer having a good nanotopography can be improved.
In addition, since the quality of nanotopography can be judged after double-sided grinding such as lapping, it is possible to grasp the double-sided grinding state and feed back to machining conditions in a timely manner, improving yield and reducing the time required for it. be able to.
Furthermore, by obtaining a large shape change on the surface of the semiconductor wafer as an approximate function representing a curve, a part of the measurement data is deleted and the accuracy of the data is deteriorated as in the case of using the moving average method. Since it can prevent, the big shape change of a semiconductor wafer outer periphery edge part can be recognized more correctly.

In the above, it is preferable to use a quadratic function as the procedure for obtaining the approximate function.
According to the present invention, by expressing the approximate function representing a curve with a simple quadratic function, the surface shape of the region of a constant dimension inside from the outer peripheral edge of the semiconductor wafer can be expressed by a simple formula, The function can be easily obtained.

In the present invention, the warpage amount is a straight line connecting the thickness direction position of the semiconductor wafer surface at the start position of the surface shape measurement by the surface shape measuring means and the thickness direction position of the semiconductor wafer surface at the end position. It is preferable to calculate the peak height at which the distance between the position in the thickness direction of the semiconductor wafer surface and the position in the thickness direction of the semiconductor wafer surface determined from the approximate function is the largest.
According to the present invention, the nanotopography of the semiconductor wafer can be evaluated based on the obtained peak height of the quadratic function. Therefore, the evaluation can be performed very easily.

The present invention is also established as a semiconductor wafer grinding method using the semiconductor wafer evaluation method, specifically,
A semiconductor wafer grinding method for grinding a semiconductor wafer,
After grinding the front and back surfaces of the semiconductor wafer, using the semiconductor wafer evaluation method according to any of the above, after evaluating the warpage of the front and back surfaces of the semiconductor wafer,
The semiconductor wafer is chucked on the basis of a surface with less warpage, and a surface grinding process is performed.

  According to the present invention, after the double-side grinding step such as lapping, the warpage amount (surface shape) of the front and back surfaces of the semiconductor wafer is measured by the above-described evaluation method, and the surface is chucked on the basis of the surface having a small warpage amount. By performing the grinding process, the surface grinding process can be performed on the basis of the surface with less warpage, that is, the flatness at the end, so that the surface shape of the reference surface by chucking is transferred to the grinding surface. By reducing this, a semiconductor wafer with higher flatness can be obtained.

Further, the present invention is also established as a semiconductor wafer processing method for processing a mirror-polished semiconductor wafer, and is characterized in that after the semiconductor wafer grinding method described above is performed, finish polishing is performed.
According to the present invention, a semiconductor wafer with good nanotopography can be obtained by the above-described action.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 5 is a flowchart showing a semiconductor wafer processing method according to the embodiment of the present invention.
In the semiconductor wafer processing method according to this embodiment, first, a silicon ingot pulled up by the Czochralski method or the like is sliced with a wire saw or the like to produce a disk-shaped semiconductor wafer having a predetermined thickness (step) S1).
Next, the sliced semiconductor wafer is chamfered at the corners of the outer peripheral edge to prevent the corners from being chipped in the following grinding process (step S2).

Next, double-sided lapping is performed as rough grinding for adjusting the shape of the semiconductor wafer (step S3). Although the illustration of the wrapping apparatus is omitted, the semiconductor wafer accommodated in the carrier is sandwiched between the lower surface plate and the upper surface plate, and abrasive grains for grinding between the semiconductor wafer and the lower surface plate surface and between the semiconductor wafer and the upper surface plate The semiconductor wafer is ground by relatively rotating the lower surface plate and the upper surface plate while supplying.
At this time, a sun gear is provided at the center of rotation of the lower surface plate, and an internal gear is provided on the outer periphery of the lower surface plate. These gears mesh with gears formed on the outer periphery of the carrier. Is revolving around the sun gear and grinding is performed while the carrier itself rotates.

When lapping is completed, the surface shape of the semiconductor wafer is measured with a laser displacement meter as a surface measuring device (step S4). The measurement location is a predetermined dimension on the inner side from the outer peripheral end of the semiconductor wafer, for example, the surface shape measurement of a portion having L1 = 30 mm to 40 mm inward from the outer peripheral end of the semiconductor wafer. At this time, it is important to measure the surface shape of the semiconductor wafer in a free state where an external force such as vacuum suction does not act.
As the measurement result of the surface shape, for example, data having a roughness of about 3 μm is acquired as shown in FIG. 6A is a surface (wafer surface) ground by the upper surface plate during lapping, and FIG. 6B is a surface ground by the lower surface plate (wafer back surface). is there.

Based on the results measured in FIG. 6, the obtained approximate curves are graphs G1 and G2 shown in FIG.
The surface shape shown in FIG. 7 shows an average value of the measurement results of the surface shape in units of 10 measurement points. This is a process for making the graph easier to see for the sake of convenience because the curve is smaller than the unevenness of the surface shape, and it is also possible to obtain an approximate function directly from the results measured in FIG.
In the case of obtaining approximate functions representing the graphs G1 and G2, in the present embodiment, as a quadratic function,
y = ax ² + b (1)
And an approximate function of each of the graphs G1 and G2 is obtained (step S5). Here, y is the position in the thickness direction of the surface shape, and x is the distance from the outer peripheral edge of the semiconductor wafer toward the inside along the surface of the semiconductor wafer.

In evaluating nanotopography from the obtained graphs G1 and G2, first, as shown in FIG. 8, the thickness direction position (y0) of the semiconductor wafer at the fitting start position (measurement start position) at the time of surface shape measurement. Then, the thickness direction position (y1) of the semiconductor wafer at the fitting end position (measurement end position) is obtained, and a linear function that gives a straight line G3 connecting these is calculated.
Next, the difference between the straight line G3 and the graphs G1 and G2 approximated as a quadratic function is taken, and the point at which the difference between the straight line G3 and the graphs G1 and G2 is the largest is the peak height. The amount of warpage is evaluated (step S6).
7A and 7B, it can be seen that the peak height is smaller in the graph G1, and the warpage amount is smaller on the surface side of the semiconductor wafer.

When the nanotopography evaluation is completed through the above-described steps S4 to S6, surface grinding (finish grinding) of the semiconductor wafer is performed (step S7).
In the surface grinding, first, a surface having a large shape change, that is, a surface of the graph G1 that is evaluated well in the nanotopography evaluation is used as a reference surface, and is used as a chucking surface of the chucking member.
In the conventional surface grinding method, the ground surface on the lower surface plate side is used as a reference surface, and as shown in FIG. 9A, a surface (wafer back surface) having a large shape change of the semiconductor wafer W may be used as a reference surface. Although the chucking member was used for vacuum suction with the wafer back surface as the suction surface, if the surface with a large shape change was used as the reference surface, the semiconductor wafer was deformed to follow the flat suction surface, and the originally flat processing surface was It will be chucked in a warped state so that the center part is convex.

When surface grinding is performed in this state and the vacuum suction by the chucking member is released, the reference surface side returns to the original, but on the processing surface side, the central portion of the semiconductor wafer W is more ground and the outer peripheral portion is hard to be ground. As shown in FIG. 9B, the processed surface of the semiconductor wafer in the unloaded state is a surface having a high flatness before grinding, which is a concave surface corresponding to the shape change of the reference surface. End up. That is, when surface grinding is performed, the shape change of the reference surface is transferred to the processed surface.
Furthermore, when the semiconductor wafer W is inverted and surface grinding on the back surface side of the semiconductor wafer W is performed, as shown in FIG. Therefore, in the suction state, the central portion of the semiconductor wafer W is in close contact with the suction surface, and the processed surface is seemingly flat, and flattening by grinding cannot be performed.

Therefore, in the evaluation of the nanotopography in step S6, the surface having such a large surface shape is transferred to a good surface by using the one having a small peak height, that is, a surface having no significant change in the surface shape as a reference surface. Therefore, the surface change of the front and back surfaces of the semiconductor wafer W can be reduced by surface grinding.
When the surface grinding of the semiconductor wafer is completed for both the front surface and the back surface, finish polishing is performed to mirror the surface of the semiconductor wafer (step S8).

When the semiconductor wafer after the completion of the polishing step S8 was measured with a nanotopography measuring device, the evaluation was performed by the steps S4 to S6, and in the case of an embodiment product that was ground using a surface with little shape change as a reference surface, The peak height of the warpage amount at the outer peripheral edge was −0.05 μm to −0.15 μm.
On the other hand, in the conventional product ground using the back side ground by the lower surface plate as a reference surface as in the past, the peak height is as bad as −0.15 μm to −0.22 μm, and the evaluation method of the present invention is used. Thus, it was confirmed that the quality of nanotopography can be determined without performing mirror polishing.

A map showing the state of a semiconductor wafer with good nanotopography. A map showing the state of a semiconductor wafer with poor nanotopography. The schematic diagram for demonstrating the semiconductor wafer shape after a lapping process. The schematic diagram for demonstrating the semiconductor wafer shape after a lapping process. The flowchart for demonstrating the processing method of the semiconductor wafer which concerns on embodiment of this invention. The graph showing the surface shape measurement result of the outer periphery edge part of a semiconductor wafer. The graph showing the approximate function calculated | required from the surface shape measurement result of the outer peripheral edge part of a semiconductor wafer. The schematic diagram for demonstrating calculating a curvature amount from the surface shape measurement result of the outer peripheral edge part of a semiconductor wafer, and evaluating nanotopography. The schematic diagram for demonstrating the cause which nanotopography deteriorates with the conventional grinding method. The graph for demonstrating the effect of this embodiment.

Explanation of symbols

  S1 ... Slicing step of ingot, S2 ... Chamfering step, S3 ... Lapping step, S4 ... Surface shape measuring step, S5 ... Step of setting approximate function, S6 ... Step of evaluating nanotopography, S7 ... Surface grinding step, S8 ... Finish polishing process, W, W1, W2 ... Semiconductor wafer

Claims (5)

A semiconductor wafer evaluation method for evaluating nanotopography of a semiconductor wafer surface before a polishing process,
Using a surface shape measuring means, in a free state in which no force is applied, a procedure for measuring the surface shape of a region of a constant dimension inside from the outer peripheral edge of the semiconductor wafer after the grinding step;
A procedure for obtaining an approximate function representing a curve that gives an end surface shape of the semiconductor wafer based on a measurement result by the surface shape measuring means;
A step of calculating a warping amount of a region having a constant dimension inside from an outer peripheral end portion of the semiconductor wafer based on the obtained approximate function and evaluating a nanotopography of the semiconductor wafer. Wafer evaluation method. The semiconductor wafer evaluation method according to claim 1,
The procedure for obtaining the approximate function uses a quadratic function. In the evaluation method of the semiconductor wafer according to claim 2,
The warpage amount is the semiconductor wafer on a straight line connecting the thickness direction position of the semiconductor wafer surface at the start position of the surface shape measurement by the surface shape measuring means and the thickness direction position of the semiconductor wafer surface at the end position. A semiconductor wafer evaluation method, wherein the distance between the position in the thickness direction of the surface and the position in the thickness direction of the surface of the semiconductor wafer obtained from the approximate function is calculated as a peak height. A semiconductor wafer grinding method for grinding a semiconductor wafer,
After grinding the front and back surfaces of the semiconductor wafer, after evaluating the warpage of the front and back surfaces of the semiconductor wafer using the semiconductor wafer evaluation method according to any one of claims 1 to 3,
A semiconductor wafer grinding method, wherein a surface grinding step is performed by chucking the semiconductor wafer using a surface with less warpage as a reference surface. A semiconductor wafer processing method for processing a mirror-polished semiconductor wafer,
After carrying out the semiconductor wafer grinding method according to claim 4,
A method for processing a semiconductor wafer, comprising performing finish polishing.