JP5472073B2 - Semiconductor wafer and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor wafer having a chamfered portion on the outer periphery and a method for manufacturing the same.

  As the degree of integration of devices such as DRAMs and flash memories increases, the flatness standards required for silicon wafers as material substrates are becoming stricter. In particular, the flatness of the outer peripheral portion of the silicon wafer greatly affects the yield of semiconductor elements.

  Parameters such as ROA (also referred to as roll-off amount or edge roll-off amount) and ESFQR that define the flatness of the outer periphery of a silicon wafer are being standardized. ROA and ESFQR are parameters indicating the amount of sag (edge roll-off) of the silicon wafer.

  A general definition of ROA will be described with reference to FIG. The horizontal axis in FIG. 7 indicates the distance from the outer peripheral edge of the wafer, and the vertical axis indicates the amount of displacement of the shape of the wafer surface. In general, ROA refers to a flat area 3 to 6 mm from the outer periphery of the wafer after correcting the tilt of the wafer surface with the wafer back surface corrected to a flat surface, and 0.5 mm or 1 mm ( In FIG. 7, the change of the shape displacement amount from the above reference at the point of the point (the distance indicated by “d” from the wafer outer peripheral edge) is shown as a sag amount. Further, a general ESFQR is an SFQR value (maximum displacement from the least square surface in the region) of a region (substantially rectangular region) having a circumferential direction of 5 ° and a radial direction of 30 mm surrounded in the circumferential direction of the outer peripheral portion of the wafer. In both ROA and ESFQR, the smaller the absolute value, the smaller the amount of sagging.

  A method for producing a silicon wafer used as a semiconductor substrate material generally includes a crystal growth step of producing a single crystal ingot using a Czochralski (CZ) method or the like, and slicing the single crystal ingot to at least one main. Through the wafer processing step, the surface is processed into a mirror surface. In this wafer processing process, when further subdivided, a slicing process for slicing a single crystal ingot to obtain a thin disk-shaped wafer, and its outer peripheral portion to prevent cracking and chipping of the wafer obtained by the slicing process. A chamfering process for chamfering, a lapping process or a grinding process for flattening the wafer, an etching process for removing processing distortion caused by the chamfering, lapping, grinding, etc. and remaining on the wafer, and the front and back surfaces of the wafer Usually, it comprises a polishing step in which at least one of them is mirror-finished, and a cleaning step in which the polished wafer is cleaned to remove abrasives and foreign substances adhering thereto. Further, a chamfered portion polishing step is added before and after the front and back surface polishing steps.

  Among these processes, there are various types of polishing systems in the polishing process, but the mirror polishing method for large diameter silicon wafers with a diameter of 300 mm or more is a double-side polishing system in which both sides are mirrored simultaneously like lapping. And a chemical mechanical polishing (CMP) method for polishing one side. In these polishings, the amount of work applied to the outer peripheral portion of the wafer is larger than that of the central portion, so that outer peripheral sagging occurs, and further, when the diameter of the wafer increases, outer peripheral sagging tends to occur. This peripheral sag is known to be due to the concentration of pressure on the outer peripheral portion of the wafer due to polishing, the influence of the viscoelasticity of the polishing slurry and polishing cloth (see Patent Document 1).

  In order to suppress the outer peripheral sag, Patent Document 2 discloses that the diameter of the wafer before the primary polishing is larger than the product diameter, and the diameter of the wafer is reduced after the primary polishing to the product diameter before the final polishing. It has been proposed to chamfer.

  In the method described in Patent Document 2, it is necessary to perform one polishing process before the wafer diameter is large, and it is necessary to modify the apparatus and change the conditions. Furthermore, excessive silicon kerf loss occurs due to diameter reduction. Therefore, the method described in Patent Document 2 has a problem that the production cost increases. In addition, with this method, in order to further improve the peripheral sag, it is necessary to use a wafer with a larger diameter and perform a larger diameter reduction process, which significantly increases the cost.

  By the way, as described above, the chamfered shape of the silicon wafer is formed by the chamfering process after the slicing process from the silicon ingot. This chamfering process generally uses a chamfering apparatus that places a wafer on a rotating wafer table and chamfers the outer periphery of the wafer with a rotating grindstone having a groove shaped in a desired shape ( (See Patent Document 3). Further, a chamfering device that creates a chamfered shape by scanning a grindstone with contour control is also used (see Patent Document 4).

As the angle of the chamfered portion of the semiconductor wafer, there are the following documents.
In Patent Document 5, in a method for manufacturing an epitaxial wafer, a mirror surface in which a chamfered slope portion of a silicon substrate having a chamfered slope portion angle of more than 16 degrees has a maximum surface roughness (R _max ) of 1 μm or less. It is described that processing is performed together to prevent generation of crown in epitaxial growth.

  Patent Document 6 describes that as a primary chamfering, chamfering is performed at an inclination angle of 10 to 45 degrees, preferably 20 to 24 degrees, and after lapping, secondary chamfering is performed to shape the final shape of the chamfered portion. ing.

  Patent Document 7 describes that edge polishing is performed at an angle of 22 degrees or 37 degrees with respect to the main surface of a semiconductor wafer.

  Patent Document 8 discloses a semiconductor wafer in which a chamfering process is performed on a peripheral part, and then a mirror surface process is performed on at least a main surface side. The peripheral part has an inclination angle of 5 ° or more and 25 ° or less with respect to the main surface. A semiconductor wafer characterized by having an inclined surface is described.

JP 2002-222781 A JP 2001-338899 A JP 2007-30119 A JP 2008-177348 A JP-A-3-280537 JP 2004-319910 A JP 2002-187050 A JP 2003-209033 A

  The present invention has been made in view of the above-mentioned problems of the prior art. A semiconductor wafer in which the peripheral sag (edge roll-off) of the semiconductor wafer is improved within a desired value without causing an increase in production cost, and An object is to provide a method for manufacturing such a semiconductor wafer.

  The present invention was made in order to solve the above-mentioned problem, a slicing step of slicing a single crystal ingot to obtain a semiconductor wafer, a chamfering step of chamfering the outer periphery of the semiconductor wafer obtained by the slicing step, A method for manufacturing a semiconductor wafer, comprising: a flattening step of flattening the chamfered semiconductor wafer; and a polishing step of polishing at least one of main surfaces of the flattened semiconductor wafer, wherein the chamfering step comprises: In the chamfered portion on the main surface side to be polished by the polishing step among the main surfaces of the semiconductor wafer, an angle formed by the main surface and the inclined surface of the chamfered portion is 30 ° according to the standard of the edge roll-off amount. Provided is a method for producing a semiconductor wafer, wherein the semiconductor wafer is adjusted within a range of 40 ° or less.

  In such a chamfering process, an angle formed between the main surface and the inclined surface of the chamfered portion (in this specification, this angle is also simply referred to as “chamfering angle”) is adjusted within a range of 30 ° to 40 °. Therefore, if it is a semiconductor wafer manufacturing method that can obtain the edge roll-off amount according to the standard, it does not significantly change the conventional semiconductor wafer manufacturing process and suppresses the occurrence of defects such as chips and chips. Only by changing the chamfered shape, a semiconductor wafer having excellent flatness of the outer peripheral portion can be manufactured. Moreover, the edge roll-off amount can be adjusted simply by selecting the chamfering angle within a range of 30 ° to 40 °, and there is no problem such as an increase in cost.

  Moreover, it is preferable that the width | variety from the outer periphery end of the said semiconductor wafer to the boundary of the said main surface and the inclined surface of the said chamfering part shall be 0.25 mm or less.

  As described above, the width from the outer peripheral edge of the semiconductor wafer to the boundary between the main surface and the inclined surface of the chamfered portion (in this specification, this width is also simply referred to as “chamfer width”. If it is called 0.25 mm or less, the improvement of the edge roll-off amount due to the limitation of the chamfer angle becomes remarkable.

  Further, the present invention is a semiconductor wafer in which a chamfered portion is formed on an outer peripheral portion and at least one main surface is polished, and at least the polished main surface side chamfered portion of the main surface of the semiconductor wafer. The angle formed between the main surface of the semiconductor wafer and the inclined surface of the chamfered portion is 30 ° or more and 40 ° or less, and the edge roll-off amount of the outer peripheral portion is 0.5 mm when the outer peripheral exclusion region at the time of measurement is 0.5 mm. Provided is a semiconductor wafer having a thickness of 150 nm or less, or 50 nm or less when the outer periphery exclusion region at the time of measurement is 1 mm.

  If it is such a semiconductor wafer, it can be set as the semiconductor wafer by which generation | occurrence | production of defects, such as a chip | tip and a chip | tip, was suppressed while the flatness of the outer peripheral part was adjusted within the desired value.

  In this case, it is preferable that the width from the outer peripheral end of the semiconductor wafer to the boundary between the main surface and the inclined surface of the chamfered portion is 0.25 mm or less.

  Thus, if the chamfering width is 0.25 mm or less, the improvement of the edge roll-off amount due to the limitation of the chamfering angle becomes remarkable.

  With the semiconductor wafer manufacturing method according to the present invention, a desired value with a small peripheral sag only by changing the chamfering shape without greatly changing the conventional semiconductor wafer manufacturing process and suppressing the occurrence of defects such as chips and chips. A highly accurate semiconductor wafer controlled inside can be manufactured. For this reason, an increase in manufacturing cost of the semiconductor wafer can be suppressed. In particular, the present invention can improve the peripheral sagging of the semiconductor wafer, and the edge roll-off amount (ROA) after polishing is 150 nm or less when the outer peripheral exclusion region is 0.5 mm, and 50 nm when the outer peripheral exclusion region is 1 mm. Thus, it is possible to provide a wafer adjusted to have excellent flatness.

It is a schematic sectional drawing which shows the chamfering shape of the semiconductor wafer which concerns on this invention. It is a graph which shows the relationship between the chamfering angle and ROA in Experimental example 1. It is a graph which shows the relationship between the chamfering angle in Example 1, and SFQR. It is a graph which shows the relationship between the chamfer angle in Experimental example 1, and ESFQR. It is a graph which shows the relationship between the chamfering width in Example 2, and ROA. It is a graph which shows the relationship between the chamfering angle in Example 3, and a chip | tip chipping incidence. It is sectional drawing for demonstrating ROA in a semiconductor wafer.

  Hereinafter, the present invention will be described in more detail, but the present invention is not limited thereto. The present invention is suitable when the semiconductor wafer is a silicon wafer, and is particularly suitable for a silicon wafer having a diameter of 300 mm or more. Hereinafter, the case where the semiconductor wafer is a silicon wafer will be mainly described. However, this invention is not limited to these, It can apply also to semiconductor wafers other than a silicon wafer.

First, the chamfered shape of the outer peripheral portion of the semiconductor wafer will be described with reference to FIG.
The outer peripheral cross section of the semiconductor wafer 11 is composed of a straight line and a curve having a substantially constant curvature. Specifically, the semiconductor wafer 11 includes main surfaces 12a and 12b, inclined surfaces (chamfered slopes) 13a and 13b of the chamfered portion, a tip straight portion 15 serving as a wafer outer peripheral end, and chamfered slopes 13a and 13b and a tip straight portion. 15 is formed of curved portions 16a and 16b having a substantially constant curvature. Further, the widths from the outer peripheral edge of the semiconductor wafer 11, that is, the tip straight portion 15, to the boundaries 14 a and 14 b between the main surfaces 12 a and 12 b and the chamfered slopes 13 a and 13 b, that is, chamfer widths are denoted as A <b> 1 and A <b> 2. Further, the curvatures of the curved portions 16a and 16b are denoted as R1 and R2. Further, the length of the front straight portion 15 is BC, the chamfering angle, that is, the angles (angles on the acute angle side) between the wafer main surfaces 12a and 12b and the chamfered slopes 13a and 13b are θ1 and θ2, and the thickness of the wafer is Indicated as t.

  In general, typical values of a 300 mm diameter silicon wafer having a thickness t = 775 μm are A1 = 0.25 to 0.40 mm, BC = 0.2 to 0.3 mm, R1 = 0.2 to 0.3 mm, θ1 = 20-25 °. A2, R2, and θ2 may be the same as or different from A1, R1, and θ1, respectively. Such a chamfered shape is formed by a chamfering device as described in Patent Document 3 or Patent Document 4, for example.

  In the present invention, as shown in FIG. 1, chamfered portions (chamfered slopes 13 a and 13 b, curved portions 16 a and 16 b, and tip straight portions 15) are formed on the outer peripheral portion of the semiconductor wafer 11. Further, at least one main surface is polished. Here, description will be made assuming that at least the main surface 12a on the wafer surface side is polished. In the present invention, an angle θ1 formed between the main surface 12a and the inclined surface (chamfered inclined surface) 13a of the chamfered portion is at least 30 ° and not more than 40 ° in the chamfered portion on the polished main surface 12a side of the main surfaces 12a and 12b. It is. Further, in the semiconductor wafer 11 of the present invention, the edge roll-off amount at the outer peripheral portion is the outer peripheral exclusion region at the time of measurement (also referred to as the peripheral excluding region, and the distance from the outer peripheral edge of the portion outside the flatness standard application range. ) Is 0.5 nm, it is 150 nm or less, and when the outer periphery exclusion region at the time of measurement is 1 mm, it is 50 nm or less. These values can be adjusted by adjusting θ1 in the range of 30 ° to 40 °. That is, the edge roll-off amount can be reduced by increasing θ1 within the range.

  Furthermore, in the present invention, it is preferable that the distance (chamfering width) A1 from the outer peripheral end (namely, the straight end portion) 15 of the semiconductor wafer 11 to the boundary 14a is 0.25 mm or less.

  Such a semiconductor wafer 11 is manufactured by the following processes.

  First, a slicing step for slicing a single crystal ingot to obtain a semiconductor wafer is performed. The manufacturing method of a semiconductor ingot is not specifically limited, Well-known methods, such as a Czochralski method (CZ method) and a floating zone melting method (FZ method), can be used. The slicing method is not particularly limited, and the slicing can be performed using an inner peripheral blade or a multi-wire saw.

  Next, a chamfering process for chamfering the outer peripheral portion of the semiconductor wafer obtained by the slicing process is performed. At this time, an angle (chamfer angle) formed by the main surface and the inclined surface of the chamfered portion is 30 ° or more and 40 ° at least in a chamfered portion on the main surface side to be polished by a polishing step described later among the main surfaces of the semiconductor wafer. The following. In the method for manufacturing a semiconductor wafer according to the present invention, the chamfer angle is adjusted in the range of 30 ° to 40 ° in this way in accordance with the standard of the edge roll-off amount of the semiconductor wafer. That is, the chamfering angle is increased within a range of 30 ° to 40 ° for those with stricter edge roll-off standards. As a result, a wafer with improved edge roll-off can be manufactured without generating chips or chips. In this chamfering step, it is further preferable that the width (chamfering width) from the outer peripheral edge of the semiconductor wafer to the boundary between the main surface and the inclined surface of the chamfered portion is 0.25 mm or less.

  The angle between the main surface and the inclined surface of the chamfered part (chamfering angle) without changing the width (chamfering width) from the outer peripheral edge of the semiconductor wafer to the boundary between the main surface and the inclined surface of the chamfered part from the conventional one. ) Can also be adjusted. Also, the chamfering width can be fixed (for example, 0.25 mm) and the chamfering angle can be adjusted within a range of 30 ° to 40 °.

  Next, a flattening step for flattening the semiconductor wafer chamfered by the chamfering step is performed. The planarization process can include a lapping process, a grinding process, an etching process, and the like.

  Next, a polishing process for polishing at least one of the main surfaces of the planarized semiconductor wafer is performed. As described above, if the angle formed between the main surface and the inclined surface of the chamfered portion is 30 ° or more in the chamfering step, the flatness of the wafer outer peripheral portion can be improved in this polishing step. This effect can correspond to a stricter standard of the edge roll-off amount, particularly when the chamfer width is as small as 0.25 mm or less, and further 0.2 mm or less.

  Furthermore, if the chamfering angle is 40 ° or less, generation of chips and chips around the wafer chamfered portion can be suppressed when handling a semiconductor wafer.

  With such a method of manufacturing a semiconductor wafer according to the present invention, the outer periphery can be obtained only by changing the chamfering shape without greatly changing the conventional semiconductor wafer manufacturing process and suppressing the occurrence of defects such as chips and chips. A semiconductor wafer having excellent flatness of the part can be manufactured.

(Experimental example)
The numerical values such as the chamfer angle and the chamfer width will be described below with reference to experimental examples.

  For the chamfered shape, a silicon wafer was prototyped using a chamfering device of Patent Document 3 and a grindstone formed into a desired total groove shape. ROA, SFQR, and ESFQR are measured after etching by including at least a carrier plate having a wafer holding hole, an upper surface plate and a lower surface plate to which a polishing cloth is pasted, and a slurry supply means, and the wafer is placed in the wafer holding hole. While holding and supplying the slurry, the carrier plate was moved between the upper and lower surface plates, and both surfaces were polished using a double-side polishing apparatus that simultaneously polished both the front and back surfaces of the wafer.

  For measurement of the chamfered shape, LEP-2200 manufactured by Kobelco Kaken Co., Ltd., which uses an image processing method using transmitted light, was used. Further, LER-310M manufactured by Kobelco Kaken Co., Ltd. was used for ROA measurement after polishing, and WaferSight manufactured by KLA-Tencor Co., Ltd. was used for SFQR and ESFQR measurements.

(Experimental example 1)
Five silicon wafers having different chamfering angles were prepared by changing the groove shape of the grindstone having a total groove, and the edge roll-off amount (ROA) after 20 μm double-side polishing was measured. The specific procedure is as follows.
First, a silicon wafer obtained by slicing from a silicon ingot was chamfered at five levels of chamfering angles (11 to 50 °). Thereafter, lapping, etching, and double-side polishing were performed. Here, the chamfered shapes other than the chamfer angles are constant A1, A2≈0.35 mm, and constant, R1, R2≈0.25 mm. By adjusting the length of the outer straight portion 15, that is, the BC value, the chamfering angles θ1 and θ2 are set to some extent without changing the chamfering width (A1, A2) and the curvature (R1, R2) of the curved portions 16a, 16b. It can be adjusted arbitrarily.

  The results of measuring ROA, SFQR, and ESFQR after the double-side polishing will be described with reference to FIGS.

FIG. 2 shows a graph showing the relationship between the chamfering angle θ (= θ1 = θ2) and ROA in Experimental Example 1. In FIG. 2, ♦ and ■ indicate the cases where the outer peripheral exclusion region is 0.5 mm and 1 mm, respectively.
It was found that ROA monotonously decreases with an increase in chamfer angle when the outer peripheral exclusion region is 0.5 mm and 1 mm. In particular, an improvement of about 20 to 30% is observed at 33 ° compared to the conventional chamfering angle of about 20 °.

FIG. 3 shows a graph showing the relationship between the chamfer angle and SFQR in Experimental Example 1. FIG. 4 shows a graph showing the relationship between the chamfer angle and ESFQR in Experimental Example 1. In FIGS. 3 and 4, SFQRmax and ESFQRmax are the maximum values in the wafer among the numerical values of the respective sites in the respective measurements.
As with ROA, SFQR was found to decrease monotonically with increasing chamfer angle. In particular, an improvement of about 20% is observed at 33 ° compared to the conventional chamfering angle of about 20 ° (see FIG. 3). Further, ESFQR also shows an improvement of less than 20% (see FIG. 4).

  All the parameters of ROA, SFQR, and ESFQR are improved as the chamfer angle is increased, and it can be seen that the chamfer angle greatly affects the peripheral sag of the wafer. The above proved to be very effective. And the larger the chamfer angle, the smaller the outer sag, and the desired value can be adjusted.

  In Experimental Example 1, as shown in FIG. 2, by adjusting the chamfer angle to 30 ° or more, the edge roll-off amount (ROA) after polishing is 150 nm or less when the outer peripheral exclusion region is 0.5 mm, A wafer having excellent flatness of 50 nm could be manufactured in the case of the outer periphery exclusion region of 1 mm.

(Experimental example 2)
Further, by forming a grindstone groove shape at the time of chamfering with a chamfering angle constant at a chamfering angle of 33 ° at which a good edge roll-off amount was obtained in Experimental Example 1, a chamfering width of 0.20 mm, 0. The amount of edge roll-off after double-side polishing when compared with 25 mm, 0.35 mm, and 0.40 mm was compared.

FIG. 5 shows a graph showing the relationship between the chamfer width and ROA in Experimental Example 2. In FIG. 5, ♦ and ■ indicate the cases where the outer peripheral exclusion region is 0.5 mm and 1 mm, respectively.
It can be seen that the edge roll-off amount after double-side polishing varies depending on the chamfer width, and shows a monotonic decrease with respect to the chamfer width. In particular, significant improvement was achieved with a chamfer width of 0.25 mm or less. This is because the shape of the outer peripheral sag is relatively on the outer peripheral side with respect to the edge roll-off measurement region.

(Experimental example 3)
Using a wafer at the same level as in Experimental Example 1, a visual inspection under a fluorescent lamp was performed on the outer periphery of the wafer. In some wafers, chips and chips were observed at the boundary between the main surface of the wafer and the chamfer. In FIG. 6, the graph which shows the relationship between the chamfering angle and chip | tip chipping incidence in Experimental example 3 was shown. From the vicinity of the chamfering angle exceeding 40 °, the occurrence rate of chips and chips increases. Chip chipping easily causes wafer cracking in the semiconductor element manufacturing process, resulting in enormous defects. In principle, chipping should not occur. Therefore, it is necessary to set an upper limit on the chamfer angle, and it is necessary that the angle is 40 ° or less.

  According to the present invention, as described above, the peripheral sag can be improved by setting the chamfer angle to 30 ° or more, and the outer periphery can be adjusted by adjusting the chamfer angle within a range of 30 ° to 40 °. You can also control the sagging. In particular, it is possible to provide a wafer having excellent flatness such that the edge roll-off amount (ROA) after polishing is 150 nm or less when the outer periphery exclusion region is 0.5 mm, and 50 nm when the outer periphery exclusion region is 1 mm.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

DESCRIPTION OF SYMBOLS 11 ... Semiconductor wafer, 12a, 12b ... Main surface, 13a, 13b ... Inclined surface,
14a, 14b ... boundary between the main surface and the inclined surface, 15 ... straight tip portion,
16a, 16b ... curve portions.

Claims (4)

Slicing a single crystal ingot to obtain a semiconductor wafer; and
A chamfering step for chamfering the outer peripheral portion of the semiconductor wafer obtained by the slicing step;
A planarization step of planarizing the chamfered semiconductor wafer;
A polishing step of polishing at least one of the main surfaces of the flattened semiconductor wafer, comprising:
In the chamfered portion on the main surface side to be polished by at least the polishing step of the main surface of the semiconductor wafer by the chamfering step, the main surface and the inclined surface of the chamfered portion according to the standard of the edge roll-off amount. A method of manufacturing a semiconductor wafer, wherein an angle formed is adjusted in a range of 30 ° to 40 °.   2. The method of manufacturing a semiconductor wafer according to claim 1, wherein a width from an outer peripheral end of the semiconductor wafer to a boundary between the main surface and the inclined surface of the chamfered portion is 0.25 mm or less. A chamfered portion is formed on the outer periphery, and at least one main surface is polished semiconductor wafer,
An angle formed between the main surface of the semiconductor wafer and the inclined surface of the chamfered portion is 30 ° or more and 40 ° or less in at least the chamfered portion on the polished main surface side of the main surface of the semiconductor wafer, and the outer peripheral portion. The edge roll-off amount of the semiconductor wafer is 150 nm or less when the outer periphery exclusion region at the time of measurement is 0.5 mm, or 50 nm or less when the outer periphery exclusion region at the time of measurement is 1 mm.   4. The semiconductor wafer according to claim 3, wherein a width from an outer peripheral end of the semiconductor wafer to a boundary between the main surface and the inclined surface of the chamfered portion is 0.25 mm or less.

Images