JP5505334B2 - Semiconductor wafer and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor wafer having high flatness near an edge and a method for manufacturing the same.

  As the degree of integration of devices such as DRAMs and flash memories increases, the flatness standards required for semiconductor wafers as material substrates are becoming stricter. In particular, the flatness of the outer periphery of the semiconductor wafer greatly affects the yield of semiconductor elements.

  In recent years, as miniaturization progresses, a flat shape is required to the outer periphery of a semiconductor wafer, and ROA (also called Roll Off Amount, roll-off amount, edge roll-off amount) is used to evaluate the flatness near the edge. And ESFQR (Edge Site Front square Range). ROA and ESFQR are parameters indicating the amount of sag (edge roll-off) of the semiconductor wafer.

A general ROA definition will be described with reference to FIG. The horizontal axis in FIG. 16 indicates the distance from the outer peripheral edge of the semiconductor wafer, and the vertical axis indicates the amount of displacement of the shape of the wafer surface. In general, ROA is a flat region of 3 to 6 mm from the outer periphery of a semiconductor wafer (from r ₁ to r _{2 in} FIG. 16) after correcting the inclination of the surface of the semiconductor wafer with the back surface of the semiconductor wafer corrected to a flat surface. The change d in the amount of displacement of the shape from the reference at the position 0.5 mm or 1 mm from the outer peripheral edge (the distance from the outer peripheral edge of the semiconductor wafer is indicated by r ₀ in FIG. 16). It is shown as a quantity. The outer peripheral end side from r ₀ is also referred to as an outer peripheral exclusion region (also referred to as a peripheral exclusion region, which is a distance from a wafer outer peripheral portion that is outside the applicable range of the flatness standard).

A general ESFQR definition will be described with reference to FIG. FIG. 17A shows a top view of the semiconductor wafer, and shows that the outer periphery is divided into 72 rectangular regions. FIG. 17 (b) is an enlarged view of the one of the rectangular regions, as shown in FIG. 17 (b), the rectangular area and the straight line L ₂ of 35mm which extend from an outer peripheral end in the radial direction, the semiconductor wafer periphery The region is surrounded by an arc L ₁ corresponding to 5 ° in the circumferential direction of the portion, and does not include a region of ₁ mm L _{3 in} the diameter direction from the outer peripheral end. Here, ESFQR is the SFQR value (maximum displacement from the least square surface in the region) of this rectangular region. In both ROA and ESFQR, the smaller the absolute value, the smaller the amount of sagging. The outer peripheral end side shown in L ₃ (also called edge exclusion, refers to the distance from the wafer outer peripheral end of the site outside the scope of flatness standard) outer peripheral excluded region as referred to.

  A method for manufacturing a silicon wafer used as a semiconductor substrate material is generally a crystal growth process for manufacturing a single crystal ingot using the Czochralski (CZ) method or the like, and slicing the single crystal ingot to process the wafer. Through the wafer processing process. In this wafer processing process, when further subdivided, a slicing process for slicing a single crystal ingot to obtain a thin disk-shaped wafer, and its outer peripheral portion to prevent cracking and chipping of the wafer obtained by the slicing process. A chamfering process for chamfering, a lapping process or a grinding process for flattening the wafer (planarization process), a polishing process for mirroring at least one of the front and back surfaces of the wafer, and cleaning the polished wafer. In general, it comprises a cleaning step for removing abrasives and foreign matters adhering to the surface. Further, a chamfered portion polishing step may be added before and after the front and back surface polishing steps.

  Among these processes, there are various types of polishing systems in the polishing process, but the mirror polishing method for large diameter silicon wafers with a diameter of 300 mm or more is a double-side polishing system in which both sides are mirrored simultaneously like lapping. And a chemical mechanical polishing (CMP) method for polishing one side. In these polishings, the amount of work applied to the outer peripheral portion of the wafer is larger than that of the central portion, so that outer peripheral sagging occurs, and further, when the diameter of the wafer increases, outer peripheral sagging tends to occur. The outer periphery sag is particularly large near the boundary between the wafer surface and the chamfer, and specifically changes greatly between 0.5 to 1 mm from the edge. ROA or ESFQR includes a point 1 mm from the outer periphery as a measurement area. The value of is bad. Such peripheral sagging is caused by an increase in polishing pressure due to deformation of the polishing cloth. In order to reduce the influence of cloth deformation, a polishing head having a retainer mechanism is used (Patent Document 1), or the cloth physical properties are changed. Improvements have been made.

JP-A-8-257893

  When a polishing head with a retainer mechanism is used as in the past, the effect of suppressing the peripheral sag of the wafer can be expected, but since the retainer ring is pressed against the polishing cloth and the cloth is compressed and deformed, the slurry is polished. Due to insufficient supply or damage to the cloth surface, surface defects may occur on the polished wafer, or the cross life may be shortened. Further, when a soft polishing cloth that does not cause surface defects is used, even a polishing head having a retainer mechanism has a limit in terms of improvement in principle. Further, the polishing head having the retainer mechanism is a cause of cost increase because the mechanism is complicated. In addition, when using a hard polishing cloth with little cross deformation to improve peripheral sag, it is difficult to achieve compatibility with wafer quality other than peripheral sag, such as cross clogging, surface scratches, and micro defects due to reduced slurry retention. The product yield was a factor.

  The present invention has been made in view of the above-described problems of the prior art, and by adjusting the chamfering width and the wafer diameter of the outer peripheral portion of the semiconductor wafer, the boundary position between the main surface and the chamfered portion of the semiconductor wafer is adjusted to the outer peripheral end side. As a result, the occurrence of defects such as chips and chips has been suppressed without causing production cost increase factors, and the peripheral sag (ROA and ESFQR) of the semiconductor wafer has been improved within the desired value. It is an object to provide a semiconductor wafer and a method for manufacturing such a semiconductor wafer.

  In addition, even if there is a request to make the excluded area of the edge of the semiconductor wafer smaller than the current 1 mm in the future, only the outer circumference sag is maintained while maintaining the current surface quality without changing the polishing conditions and the polishing apparatus. It is an object of the present invention to provide a semiconductor wafer that can be improved and a method for manufacturing such a semiconductor wafer.

The present invention was made in order to solve the above problems, and a slicing step of slicing a single crystal ingot to obtain a semiconductor wafer;
Chamfering the outer periphery of the semiconductor wafer obtained by the slicing step, and forming a chamfered portion; and
A planarization step of planarizing the chamfered semiconductor wafer;
A method of manufacturing a semiconductor wafer, comprising a polishing step of polishing at least one of the main surfaces of the planarized semiconductor wafer,
In the polishing step, the flattened semiconductor wafer adjusted in a range of a diameter 0.3 mm or less larger than a desired diameter and a chamfer width of the chamfered portion in a range of 50 μm or more and 250 μm or less according to the ROA and ESFQR standards. A method of manufacturing a semiconductor wafer is provided, wherein at least one of the main surfaces of the semiconductor wafer is polished.

  As described above, according to the required ROA and ESFQR standards, the semiconductor wafer before the polishing step is in a range of a diameter that is 0.3 mm or less larger than a desired diameter, and the chamfer width of the chamfered portion is in a range of 50 μm or more and 250 μm or less. By adjusting, it is possible to move the boundary position between the main surface and chamfered portion of the semiconductor wafer to the outer peripheral end side, so that the production cost is not increased without greatly changing the conventional semiconductor wafer manufacturing process. In addition, it is possible to manufacture a semiconductor wafer with excellent flatness of the outer peripheral portion only by changing the chamfered shape while suppressing the occurrence of defects such as chips and chips.

  That is, in the present invention, through the slicing step, the chamfering step, and the flattening step, the diameter of the semiconductor wafer is increased within the above range and the chamfer width is shortened, so that the boundary position between the main surface and the chamfered portion of the semiconductor wafer is outside. ROA and ESFQR can be improved according to the amount of movement of the boundary position to the outside.

  Further, in the polishing step, at least one of the main surfaces of the flattened semiconductor wafer adjusted in the range of 0.05 mm or more and 0.2 mm or less larger than the desired diameter is polished according to the ROA and ESFQR standards. It is preferable to do.

  As described above, by increasing the diameter in a smaller range, the semiconductor wafer manufacturing method can suppress the increase in cost associated with the adjustment of the manufacturing apparatus such as the adjustment of the edge handling apparatus while satisfying the strict ROA and ESFQR standards. preferable.

  Further, in the polishing step, it is preferable to polish at least one of the main surfaces of the flattened semiconductor wafer whose chamfered width of the chamfered portion is adjusted in the range of 50 μm or more and 200 μm or less according to the ROA and ESFQR standards.

  As described above, the width from the outer peripheral edge of the semiconductor wafer to the boundary between the main surface and the inclined surface of the chamfered portion (in this specification, this width is also simply referred to as “chamfer width”. It is also preferable that more stringent ROA and ESFQR standards can be satisfied by simply adjusting in the range of 50 μm or more and 200 μm or less.

  According to this method, the ROA standard can correspond to a standard of 200 nm or less when the outer periphery exclusion region is 0.5 mm, or a standard of 50 nm or less when the outer periphery exclusion region is 1.0 mm.

  In this way, even with the stricter ROA standards, only the adjustment of the diameter range and chamfering width range of the semiconductor wafer does not significantly change the conventional semiconductor wafer manufacturing process, and defects such as chips and chips It is possible to manufacture a semiconductor wafer excellent in flatness of the outer peripheral portion only by changing the chamfered shape while suppressing the occurrence of the above.

  Further, the ESFQR standard can correspond to a standard of ESFQRave of a rectangular region having an outer periphery of 1 to 35 mm and an angle of 5 ° of the polished semiconductor wafer of 65 nm or less.

  In this way, even with the stricter ESFQR standard, only the adjustment of the diameter range and chamfering width range of the semiconductor wafer does not significantly change the conventional semiconductor wafer manufacturing process, and defects such as chips and chips It is possible to manufacture a semiconductor wafer excellent in flatness of the outer peripheral portion only by changing the chamfered shape while suppressing the occurrence of the above.

Further, in the present invention, a chamfered portion is formed on the outer peripheral portion, and at least one main surface is polished, a semiconductor wafer,
A diameter of the semiconductor wafer is 0.3 mm or less larger than a desired diameter, and a chamfer width from an outer peripheral end of the semiconductor wafer to a boundary position between the chamfered portion and the main surface is 50 μm or more and 250 μm or less. The ROA of the outer peripheral portion is 200 nm or less when measured with an outer peripheral exclusion region of 0.5 mm, or 50 nm or less when measured with an outer peripheral exclusion region of 1.0 mm, and the outer periphery of the semiconductor wafer is 1 mm to 35 mm. The semiconductor wafer is characterized in that the ESFQRave of a rectangular region having an angle of 5 ° is 65 nm or less.

  If it is such a semiconductor wafer, it can be set as the semiconductor wafer by which the flatness of the outer peripheral part was adjusted in the desired value excellent, and generation | occurrence | production of defects, such as a chip | tip and a chip, was suppressed at low cost. .

  The diameter of the semiconductor wafer is preferably 0.05 mm or more and 0.2 mm or less larger than a desired diameter.

  Thus, by increasing the diameter in a smaller range, it is preferable to achieve a lower cost semiconductor wafer while satisfying strict ROA and ESFQR standards.

  Further, the chamfer width is preferably 50 μm or more and 200 μm or less.

  Such a chamfering width range is preferable because it becomes a semiconductor wafer that can satisfy stricter ROA and ESFQR standards.

  In the semiconductor wafer manufacturing method according to the present invention, the boundary position between the main surface and the chamfered portion of the semiconductor wafer can be moved to the outer peripheral end side by adjusting the chamfer width and the wafer diameter of the outer peripheral portion of the semiconductor wafer. In this way, a semiconductor wafer in which the peripheral sag (ROA and ESFQR) of the semiconductor wafer is improved within a desired value by suppressing the occurrence of defects such as chips and chips, without causing a cost increase in production. Can do. Further, according to the present invention, the ROA of the outer peripheral portion is 200 nm or less when measured with the outer periphery exclusion region being 0.5 mm, or 50 nm or less when measured with the outer periphery exclusion region being 1.0 mm, It is possible to provide a semiconductor wafer having excellent flatness with an ESFQRave of 65 nm or less in a rectangular region having an outer periphery of 1 mm to 35 mm and an angle of 5 °.

  In addition, even if there is a demand to make the excluded area of the edge of the semiconductor wafer smaller than the current 1 mm in the future, if the semiconductor wafer manufacturing method according to the present invention is used, the allowable diameter of the device processing apparatus (0.3 mm) The diameter of the chamfer is reduced to a chamfering width (50 μm or more and 250 μm or less) that does not affect device manufacturing, and the outer circumference is maintained while maintaining the current surface quality without changing polishing conditions and polishing equipment. It is possible to improve only the sagging. Furthermore, according to this method, since it is possible to improve without changing the polishing conditions, polishing apparatus, etc., it is possible to improve only the outer sag while maintaining the current surface quality, resulting in a decrease in yield and an increase in cost. Does not occur. In addition, since the chamfer width and diameter are only adjusted within the range of the targeted values, it is possible to reduce the time and cost for setting conditions associated with the process change.

It is a schematic sectional drawing which shows the chamfering shape of the semiconductor wafer which concerns on this invention. It is a graph which shows the stress distribution concerning the grinding | polishing surface of a semiconductor wafer in case a chamfering width is 350 micrometers. It is the graph which calculated the differential pressure | voltage of the stress of 148mm (position 2mm from an outer periphery end) and 149mm (position 1mm from an outer periphery end) from the center of a semiconductor wafer, respectively, and plotted according to the chamfering width. It is a graph which shows the result of having grind | polished the semiconductor wafer which has a chamfering width of 50 micrometers, 150 micrometers, 250 micrometers, 350 micrometers, and 450 micrometers, and measuring ESFQR after grinding | polishing. It is a graph which shows the result of having grind | polished the semiconductor wafer which has a chamfering width of 50 micrometers, 150 micrometers, 250 micrometers, 350 micrometers, and 450 micrometers, and investigated the micro defect of the chamfering part using the review scanning electron microscope JWS-3000. It is a graph which shows the result of having grind | polished the semiconductor wafer which has a chamfering width of 250 micrometers and 350 micrometers, and measuring ROA after grinding | polishing. FIG. 7 is a diagram comparing the graph of the semiconductor wafer having a chamfer width of 350 μm in FIG. 6 with the graph of the semiconductor wafer having a chamfer width of 250 μm by translating 100 μm to the outer peripheral end side. It is a graph which shows the displacement amount of the shape of the semiconductor wafer outer peripheral part which has a chamfering width of 250 micrometers and 350 micrometers after chamfering, planarization, and grinding | polishing. FIG. 9 is a diagram comparing the graph of the semiconductor wafer having a chamfer width of 350 μm in FIG. 8 with the graph of the semiconductor wafer having a chamfer width of 250 μm by translating 100 μm to the outer peripheral end side. It is a graph which shows the displacement amount of the semiconductor wafer outer peripheral part at the time of chamfering, planarizing, and grinding | polishing the semiconductor wafer larger than a desired diameter. It is a graph which shows the relationship between the change of the diameter of a semiconductor wafer, and the change of ESFQR. It is a graph which shows the relationship between the change of the diameter of a semiconductor wafer, and an ESFQR improvement rate. It is the graph which compared ESFQR of the semiconductor wafer of Example 1 and a comparative example. It is the graph which compared ESFQR of the semiconductor wafer of Example 2 and a comparative example. It is the graph which compared ESFQR of the semiconductor wafer of Example 3 and a comparative example. It is sectional drawing for demonstrating ROA in a semiconductor wafer. It is sectional drawing for demonstrating ESFQR in a semiconductor wafer.

  Hereinafter, the present invention will be described in more detail, but the present invention is not limited thereto. The present invention is suitable when the semiconductor wafer is a silicon wafer, and is particularly suitable for a silicon wafer having a diameter of 300 mm or more. Hereinafter, the case where the semiconductor wafer is a silicon wafer will be mainly described. However, this invention is not limited to these, It can apply also to semiconductor wafers other than a silicon wafer.

(Simulation of stress distribution on polished surface of semiconductor wafer)
In order to investigate the stress distribution on the polished surface of the semiconductor wafer, a semiconductor wafer having a diameter of 300 mm is assumed, and the chamfer width is set to 0 μm, 100 μm, 200 μm, 250 μm, 350 μm, and 500 μm. In particular, a stress distribution simulation on the outer periphery was performed using ANSYS structural analysis. FIG. 2 shows the stress distribution on the polished surface of the semiconductor wafer when the chamfer width is 350 μm. From this profile, the stress at the position of 149 mm (position of 1 mm from the outer edge) is larger than the stress at the position of 148 mm from the center of the semiconductor wafer (position of 2 mm from the outer edge), and the stress distribution on the same polished surface of the semiconductor wafer. It can be seen that is non-uniform.

  Next, from the profile of stress distribution when the chamfer width is 0 μm, 100 μm, 200 μm, 250 μm, 350 μm, and 500 μm, 148 mm from the center of the semiconductor wafer (position 2 mm from the outer edge) and 149 mm (position 1 mm from the outer edge) FIG. 3 shows the results of the calculation of the differential pressures of the stress) and plotting by the chamfer width. FIG. 3 shows that the stress difference between the position of 148 mm and the position of 149 mm from the center of the semiconductor wafer decreases as the chamfer width decreases.

(Semiconductor wafer polishing rate)
It is known that the polishing speed of the semiconductor wafer depends on the pressure applied to the polishing surface of the semiconductor wafer and the relative speed of the polishing surface and the polishing cloth, as indicated by the Preston equation of the following equation (1). Since the stress distribution described above exists in the outer peripheral portion of the semiconductor wafer, the polishing rate of the outer peripheral portion varies depending on the location. As described above, the shorter the chamfering width, the more uniform the stress distribution is obtained with respect to the outer peripheral portion of the polished surface of the semiconductor wafer, so that the polishing rate becomes uniform and the outer peripheral sag is improved.
[Formula (1): Preston's formula]
RR = Q / t = k · p · v
RR: Polishing speed
Q: Polishing amount
t: Polishing time
k: proportionality constant
p: Pressure applied to the polished surface of the semiconductor wafer
v: Relative speed of polishing surface of semiconductor wafer and polishing cloth

(Relationship between chamfer width of semiconductor wafer and ESFQR)
Actually, 10 semiconductor wafers each having a chamfer width of 50 μm, 150 μm, 250 μm, 350 μm, and 450 μm were polished, and the ESFQR after polishing was measured. FIG. In FIG. 4, ♦ indicates an average value, and a semiconductor wafer having a chamfer width of 350 μm is used as a standard, and the ESFQR average value (ESFQRave) is set to 100%, and the relative ratio (%) is indicated. In addition, ESFQR was evaluated using Wafersight of KLA Tencor. Specifically, ESFQRave of a rectangular region having an outer periphery of 1 mm to 35 mm and an angle of 5 ° was evaluated (see FIG. 17).

(Quality check of chamfered part of polished semiconductor wafer)
From the result of FIG. 4, it can be seen that by reducing the chamfer width, the value of ESFQRave is reduced, and the sagging of the outer periphery is improved. The ESFQR improves as the chamfer width decreases, but there is a concern that cracks and cracks may occur in the outer peripheral portion due to the shorter chamfer width. Therefore, the quality of the chamfered part was checked using the same wafer. No cracks or cracks were observed on all the wafers.

  In order to investigate in more detail, 10 pieces of the same semiconductor wafer each having a chamfering width of 50 μm, 150 μm, 250 μm, 350 μm, and 450 μm, each using a defect review scanning electron microscope JWS-3000 manufactured by JEOL Ltd. We investigated minute defects (number of minute edge defects). The result is shown in FIG. In FIG. 5, ● represents an average value, and the relative value is shown with an average value of the number of defects at the edge portion that can be observed with an electron microscope as 100% with a semiconductor wafer having a chamfer width of 350 μm as a standard. Since the chamfer width of 250 μm has a smaller number of micro defects than the chamfer width of 50 μm, the chamfer width is preferably adjusted in a range of 50 μm or more and 250 μm or less when the quality of the micro defects in the chamfered portion is required.

(Relationship between chamfer width of semiconductor wafer and ROA)
Moreover, in order to evaluate ROA of the semiconductor wafer after polishing, ROA after polishing of the semiconductor wafer having chamfered portions of 250 μm and 350 μm was measured using LER-310M manufactured by Kobelco Research Institute. Table 1 shows each ROA at a distance of 0.5 mm, 0.7 mm, and 1.0 mm from the outer peripheral edge. FIG. 6 shows the result of polishing a semiconductor wafer having a chamfer width of 250 μm and 350 μm and measuring the ROA after polishing. When comparing a semiconductor wafer with a chamfered portion of 350 μm and 250 μm, ROA is 11 nm different at a point 1 mm from the outer periphery (improvement rate 20%), but 47 nm (an improvement rate 34%) at a position 0.7 mm from the outer periphery. In the position of 0.5 mm from the outer periphery, the difference was larger as the distance from the outer periphery was 229 nm (54% improvement rate), and the ROA improvement rate was also increased. FIG. 7 shows a graph of the semiconductor wafer having a chamfering width of 350 μm in FIG. 6 compared with the graph of the semiconductor wafer having a chamfering width of 250 μm by translating 100 μm to the outer peripheral end side. When the ROA value of 250 μm is shifted by 100 μm and plotted together with the data of 350 μm, it can be seen that they are almost on the same line. 6 and 7 indicate the semiconductor wafer having a chamfer width of 350 μm and the semiconductor wafer having a chamfer width of 250 μm, respectively.

  FIG. 8 shows the shape of the outer peripheral portion of the semiconductor wafer having chamfer widths of 250 μm and 350 μm after chamfering, planarization, and polishing. The vertical axis represents the amount of displacement after chamfering, flattening, and polishing. FIG. 9 shows a graph of the semiconductor wafer having a chamfer width of 350 μm in FIG. 8 compared with the graph of the semiconductor wafer having a chamfer width of 250 μm after being translated by 100 μm to the outer peripheral end side. Similar to the relationship between FIGS. 6 and 7, the 250 μm and 350 μm profiles in FIG. 8 have similar shapes. If the graph when the chamfer width is 350 μm is shifted by 100 μm, the graph when the chamfer width is 250 μm You can see that they are on the same line. 8 and 9, the ♦ and ■ marks indicate a semiconductor wafer having a chamfer width of 350 μm and a semiconductor wafer having a chamfer width of 250 μm, respectively.

  From the above results, it can be said that the sagging amount of the wafer is determined simply depending on the boundary position between the main surface and the chamfered portion of the semiconductor wafer. As described above, since the peripheral sag can be improved by moving the boundary position between the main surface and the chamfered portion of the semiconductor wafer, the chamfer width of the semiconductor wafer can be shortened regardless of the combination of polishing conditions. By doing so, it can be seen that ROA and ESFQR can be improved.

(Relationship between semiconductor wafer diameter and ESFQR)
Next, in order to investigate what effect the diameter of the semiconductor wafer has on improving the ESFQR, a simulation was performed when the diameter was increased. The results are shown in FIG. In FIG. 10, ♦ marks indicate semiconductor wafers having a diameter of 300 mm, ■ marks indicate 300 + 0.2 mm, Δ marks indicate 300 + 0.4 mm, and ◯ marks indicate 300 + 0.6 mm. As a result of calculating the displacement amount from 140 mm to the outer peripheral edge by changing the diameter on the basis of a flat point 140 mm from the center of the semiconductor wafer, the displacement amount at a point of 149 mm from the center (1 mm from the outer periphery) is increased as the diameter is increased. It turns out that it improves. Here, in the present invention, the “desired diameter” is a diameter determined by the standard of the semiconductor wafer, for example, 4 inches (100 mm), 5 inches (125 mm), 6 inches (150 mm), 8 inches. (200 mm) and 12 inches (300 mm).

  Therefore, assuming ESFQR of 68 nm, 78 nm, 99 nm, 136 nm, 162 nm, and 314 nm semiconductor wafers, simulation of the improvement rate of ESFQR was performed when these diameters were increased by 0.01 to 0.6 mm, respectively. FIG. 11 shows the relationship between the diameter of the semiconductor wafer and the change in ESFQR, and FIG. 12 shows the relationship between the diameter of the semiconductor wafer and the improvement rate of ESFQR. In FIGS. 11 and 12, the asterisk indicates a semiconductor wafer having an ESFQR of 68 nm, the ◯ mark is 78 nm, the ▲ mark is 99 nm, the △ mark is 136 nm, the ● mark is 162 nm, and the ◯ mark is 314 nm. As shown in FIG. 12, ESFQR is improved by 23 to 39% (average of about 30%) when the diameter of the semiconductor wafer is increased by 0.2 mm. This improvement rate almost coincides with the simulation result (FIG. 4) when the chamfer width is 350 μm to 250 μm. Therefore, the effect of changing the diameter is the effect of moving the boundary position between the main surface and the chamfered portion to the outside of the semiconductor wafer, as with the effect of changing the chamfering width. By combining with the change of the chamfering width, the ROA and ESFQR Improvement is possible.

  As a result of intensive studies, the present inventors have found that the chamfer width is reduced (in the range of 50 μm or more and 250 μm or less) and the diameter is increased (0 from the desired diameter) according to the ROA and ESFQR standards. .3mm or less diameter range) The boundary position can be moved to the outside only by adjusting the semiconductor wafer, and the outer peripheral sag (ROA, ESFQR) is small after polishing according to the amount of the boundary position moved to the outside. As a result, the present inventors have found that a semiconductor wafer can be manufactured at a low cost and without the occurrence of defects such as chips and chips without significantly changing the conventional semiconductor wafer manufacturing process. Hereinafter, the present invention will be described in more detail.

[Semiconductor wafer]
In the present invention, a chamfered portion is formed on the outer peripheral portion, and at least one main surface is a polished semiconductor wafer,
A diameter of the semiconductor wafer is 0.3 mm or less larger than a desired diameter, and a chamfer width from an outer peripheral end of the semiconductor wafer to a boundary position between the chamfered portion and the main surface is 50 μm or more and 250 μm or less. The ROA of the outer peripheral portion is 200 nm or less when measured with an outer peripheral exclusion region of 0.5 mm, or 50 nm or less when measured with an outer peripheral exclusion region of 1.0 mm, and the outer periphery of the semiconductor wafer is 1 mm to 35 mm. The semiconductor wafer is characterized in that the ESFQRave of a rectangular region having an angle of 5 ° is 65 nm or less.

  First, the chamfered shape of the outer peripheral portion of the semiconductor wafer will be described with reference to FIG. The outer peripheral cross section of the semiconductor wafer 11 is composed of a straight line and a curve having a substantially constant curvature. Specifically, the semiconductor wafer 11 includes main surfaces 12a and 12b, inclined surfaces (chamfered inclined surfaces) 13a and 13b of the chamfered portion, and a tip linear portion 15 serving as the outer peripheral edge of the wafer. Further, the widths A1 and A2 from the outer peripheral edge of the semiconductor wafer 11, that is, the straight end portion 15 to the boundaries 14a and 14b between the main surfaces 12a and 12b and the chamfered slopes 13a and 13b are defined as chamfered widths.

  The semiconductor wafer of the present invention is 0.3 mm or less larger than the desired diameter. For example, when a semiconductor wafer having a diameter of 300 mm is manufactured, the diameter is greater than 300 mm and not greater than 300.3 mm. In particular, it is preferably 0.05 mm or more and 0.2 mm or less larger than the desired diameter. If it is larger by 0.05 mm or more and 0.2 mm or less, it is preferable to increase the diameter in a smaller range to achieve a semiconductor wafer that can further suppress cost increase while satisfying strict ROA and ESFQR standards. In particular, when the diameter is 0.2 mm or less larger than the desired diameter, it is preferable because the SEMI standard is satisfied. If the diameter is larger than 0.3 mm than the desired diameter, it is difficult to cope with the handling device, and the object of the present invention cannot be achieved.

  In the semiconductor wafer of the present invention, the chamfer width from the outer peripheral edge of the semiconductor wafer to the boundary position between the chamfered portion and the main surface is 50 μm or more and 250 μm or less. In particular, the chamfer width is preferably 50 μm or more and 200 μm or less. A chamfer width of 50 μm or more and 200 μm or less is preferable because it can satisfy stricter ROA and ESFQR standards. When the chamfering width is less than 50 μm, defects at the wafer edge portion increase, and the object of the present invention cannot be achieved.

  Further, in the semiconductor wafer of the present invention, the ROA of the outer peripheral portion is 200 nm or less when measured with the outer periphery excluded region being 0.5 mm, and is 50 nm or less when measured with the outer periphery excluded region being 1.0 mm. Thus, the semiconductor wafer of the present invention satisfies the stricter ROA standard.

  Further, in the semiconductor wafer of the present invention, the ESFQRave of the rectangular region having the outer periphery of 1 mm to 35 mm and the angle of 5 ° is 65 nm or less. As described above, the semiconductor wafer of the present invention satisfies the stricter ESFQR standard. These ROA and ESFQR values can be adjusted by adjusting them within a range that is 0.3 mm or less larger than the desired diameter, and adjusting the chamfer width within a range of 50 μm or more and 250 μm or less. That is, by increasing the diameter within the range and reducing the chamfer width within the range, a semiconductor wafer having a small ROA and ESFQR is obtained.

  The semiconductor wafer of the present invention is not particularly limited as long as it satisfies the chamfer width, diameter, ROA, and ESFQR, and may be a silicon semiconductor wafer or a compound semiconductor wafer.

[Semiconductor wafer manufacturing method]
In order to produce the semiconductor wafer as described above, in the present invention, a slicing step of slicing a single crystal ingot to obtain a semiconductor wafer,
Chamfering the outer periphery of the semiconductor wafer obtained by the slicing step, and forming a chamfered portion; and
A planarization step of planarizing the chamfered semiconductor wafer;
A method of manufacturing a semiconductor wafer, comprising a polishing step of polishing at least one of the main surfaces of the planarized semiconductor wafer,
In the polishing step, the flattened semiconductor wafer adjusted in a range of a diameter 0.3 mm or less larger than a desired diameter and a chamfer width of the chamfered portion in a range of 50 μm or more and 250 μm or less according to the ROA and ESFQR standards. A method of manufacturing a semiconductor wafer is provided, wherein at least one of the main surfaces of the semiconductor wafer is polished.

[Slicing process]
First, a slicing step for slicing a single crystal ingot to obtain a semiconductor wafer is performed. The manufacturing method of a semiconductor ingot is not specifically limited, Well-known methods, such as a Czochralski method (CZ method) and a floating zone melting method (FZ method), can be used. The slicing method is not particularly limited, and the slicing can be performed using an inner peripheral blade or a multi-wire saw. At this time, it is considered that the diameter of the semiconductor wafer polished in the polishing process is adjusted within a range of 0.3 mm or less larger than the desired diameter through at least a chamfering process and a planarization process described later.

[Chamfering process]
Next, the outer periphery of the semiconductor wafer obtained by this slicing step is chamfered to perform a chamfering step for forming a chamfered portion. At this time, it is considered that the diameter of the semiconductor wafer polished in the polishing process is adjusted within a range of 0.3 mm or less larger than the desired diameter through at least a planarization process described later. It is considered that the chamfer width of the semiconductor wafer polished in the polishing process is adjusted in the range of 50 μm or more and 250 μm or less through the planarization process.

[Planarization process]
Next, a flattening step for flattening the semiconductor wafer chamfered by the chamfering step is performed. The planarization process can include a lapping process, a grinding process, an etching process, and the like. In the present invention, also in the planarization step, the diameter and chamfering width of the semiconductor wafer to be polished in the polishing step to be described later are in a range of a diameter that is 0.3 mm or less larger than the desired diameter according to the ROA and ESFQR standards. Flattening is performed in consideration of the chamfering width being adjusted in the range of 50 μm to 250 μm.

[Polishing process]
Next, in accordance with ROA and ESFQR standards, the main surface of the flattened semiconductor wafer is adjusted in a range of a diameter that is 0.3 mm or less larger than a desired diameter and a chamfer width of the chamfered portion is in a range of 50 μm or more and 250 μm or less. A polishing step of polishing at least one of the surfaces is performed. As described above, according to the ROA and ESFQR standards before the polishing step, the semiconductor is adjusted to a diameter range of 0.3 mm or less larger than a desired diameter, and the chamfer width of the chamfered portion is adjusted to a range of 50 μm to 250 μm. The wafer has a boundary position moved toward the outer peripheral end, and a semiconductor wafer having a desired ROA and ESFQR can be manufactured according to the amount of movement of the boundary position.

  In the method for manufacturing a semiconductor wafer according to the present invention, the diameter of the semiconductor wafer polished in the polishing step is within a range of a diameter that is 0.3 mm or less larger than a desired diameter in accordance with the ROA and ESFQR standards of the semiconductor wafer. In addition, the chamfer width is adjusted within a range of 50 μm to 250 μm. In other words, for those with stricter ROA and ESFQR standards, the chamfering is adjusted to be larger within the range of 0.3 mm or less than the desired diameter of the semiconductor wafer manufactured from the above-described slicing process to flattening process. The chamfered portion can be formed by adjusting the width smaller within the range of 50 μm or more and 250 μm or less. As a result, a wafer with improved edge roll-off can be manufactured without generating chips or chips. Then, by adjusting the diameter and the chamfering width within the above range, a wafer having ROA and ESFQR values satisfying the required standards can be finished.

  Further, in the polishing step, at least one of the main surfaces of the semiconductor wafer adjusted in a range of a diameter larger by 0.05 mm or more and 0.2 mm or less than a desired diameter may be polished according to the ROA and ESFQR standards. preferable. As described above, by increasing the diameter in a smaller range, the semiconductor wafer manufacturing method can suppress the increase in cost associated with the adjustment of the manufacturing apparatus such as the adjustment of the edge handling apparatus while satisfying the strict ROA and ESFQR standards. preferable.

  Further, in the polishing step, it is preferable to polish at least one of the main surfaces of the semiconductor wafer whose chamfered width of the chamfered portion is adjusted in the range of 50 μm or more and 200 μm or less according to the ROA and ESFQR standards. It is preferable because the stricter ROA and ESFQR standards can be satisfied only by adjusting the chamfer width in such a range.

  The standard of the ROA is 200 nm or less when the ROA of the semiconductor wafer after polishing is measured with the outer periphery exclusion region being 0.5 mm, or 50 nm or less when the outer periphery exclusion region is 1.0 mm. It is preferable. Even for these stricter ROA standards, the semiconductor wafer diameter range and the chamfer width range can be adjusted as described above, and the conventional semiconductor wafer manufacturing process can be reduced at a low cost. In addition, it is preferable because it is possible to manufacture a semiconductor wafer excellent in flatness of the outer peripheral portion only by changing the diameter and chamfering shape while suppressing the occurrence of defects such as chips and chips.

  The ESFQR standard is preferably such that the ESFQRave of a rectangular region having a circumference of 1 mm to 35 mm and an angle of 5 ° of the polished semiconductor wafer is 65 nm or less. Even for these stricter ESFQR standards, the semiconductor wafer diameter range and the chamfer width range can be adjusted as described above, and the conventional semiconductor wafer manufacturing process can be reduced at a low cost. In addition, it is preferable because it is possible to manufacture a semiconductor wafer with excellent flatness of the outer peripheral portion only by changing the chamfered shape while suppressing the occurrence of defects such as chips and chips.

  EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to the following Example.

Example 1
A silicon single crystal ingot was sliced to obtain a silicon wafer having a diameter of about 300 mm, the outer periphery of the obtained silicon wafer was chamfered to form a chamfer, and the chamfered silicon wafer was flattened. In this case, the ROA standard after polishing is that the ROA of the polished silicon wafer is 200 nm or less when the outer periphery exclusion region is measured as 0.5 mm, and the outer periphery exclusion region is measured as 1.0 mm. And the ESFQR standard is adjusted so that the ESFQRave of the rectangular area of the polished silicon wafer is 1 to 35 mm and the angle is 5 °, and the chamfering width is 250 μm. A silicon wafer larger by 0.05 mm than the diameter (300 mm) was prepared. Thereafter, the silicon wafer was polished to obtain a silicon wafer of the present invention, and ROA and ESFQR were measured and calculated. The results of ESFQR are shown in FIG. In FIG. 13, a circled plot and a shaded bar graph are Example 1. ROA is calculated when the outer peripheral exclusion area is 0.5 mm and 1.0 mm, and ESFQRmax is easily affected by notches and laser marks. Compared with ESFQRave for the purpose of confirming the effect of changing conditions. Went. ESFQR was performed under the measurement conditions of an outer periphery of 1 mm to 35 mm and an angle of 5 °.

(Example 2)
Next, in the same manner as in Example 1, a silicon wafer having a chamfer width of 250 μm and 0.2 mm larger than a desired diameter was produced. Thereafter, the silicon wafer was polished to obtain a silicon wafer of the present invention, and ROA and ESFQR were measured and calculated in the same manner as in Example 1. The results of ESFQR are shown in FIG. In FIG. 14, a circled plot and a shaded bar graph are Example 2.

(Example 3)
In the same manner as in Example 1, a silicon wafer having a chamfer width of 50 μm and 0.3 mm larger than a desired diameter was produced. Thereafter, the silicon wafer was polished to obtain a silicon wafer of the present invention, and ROA and ESFQR were measured and calculated in the same manner as in Example 1. The results of ESFQR are shown in FIG. In FIG. 15, the circled plot and the shaded bar graph are Example 3.

(Comparative example)
A silicon single crystal ingot is sliced by a conventional manufacturing method without considering ROA and ESFQR standards to obtain a silicon wafer having a diameter of about 300 mm, and the outer periphery of the obtained silicon wafer is chamfered to form a chamfered portion. Then, the chamfered silicon wafer was flattened to produce a silicon wafer having a chamfer width of 350 μm and the same size as the desired diameter. Thereafter, the silicon wafer was polished to obtain a comparative silicon wafer, and ROA and ESFQR were measured and calculated in the same manner as in Example 1. The results of ESFQR are shown in FIGS. In FIGS. 13, 14, and 15, the ● plots and the unfilled bar graphs are comparative examples.

  The results of improvement of ESFQR and ROA in Comparative Examples manufactured according to the conventional manufacturing method and Examples 1 to 3 of the present invention are summarized in Table 2. Thus, according to ROA and ESFQR standards, a comparison was made by polishing a silicon wafer that was not adjusted within a range of a diameter 0.3 mm or less larger than a desired diameter and a chamfer width of the chamfered portion of 50 μm to 250 μm. It was shown that Examples 1-3 of this invention have a remarkable improvement result in ESFQR and ROA rather than an example.

  As described above, according to the present invention, there is provided a method of manufacturing a semiconductor wafer in which the peripheral sag (ROA and ESFQR) of the semiconductor wafer is improved within a desired value without causing an increase in production cost. be able to. Further, according to the present invention, the polished ROA is 200 nm or less in the case of the outer periphery exclusion region of 0.5 mm, or 50 nm or less in the case of the outer periphery exclusion region of 1 mm, and the outer periphery of the semiconductor wafer is from 1 mm to 35 mm. Can provide a semiconductor wafer having excellent flatness in which ESFQRave of a rectangular region of 5 ° is 65 nm or less.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

DESCRIPTION OF SYMBOLS 11 ... Semiconductor wafer, 12a, 12b ... Main surface, 13a, 13b ... Inclined surface,
14a, 14b ... boundary between main surface and inclined surface, 15 ... straight end portion, A1, A2 ... chamfer width

Claims (8)

Slicing a single crystal ingot to obtain a semiconductor wafer; and
Chamfering the outer periphery of the semiconductor wafer obtained by the slicing step, and forming a chamfered portion; and
A planarization step of planarizing the chamfered semiconductor wafer;
A method of manufacturing a semiconductor wafer, comprising a polishing step of polishing at least one of the main surfaces of the planarized semiconductor wafer,
In the polishing step, the flattened semiconductor wafer adjusted in a range of a diameter 0.3 mm or less larger than a desired diameter and a chamfer width of the chamfered portion in a range of 50 μm or more and 250 μm or less according to the ROA and ESFQR standards. A method for producing a semiconductor wafer, comprising polishing at least one of the main surfaces of the semiconductor wafer.   In the polishing step, at least one of the main surfaces of the flattened semiconductor wafer adjusted in a range of 0.05 mm to 0.2 mm larger than a desired diameter is polished according to the ROA and ESFQR standards. The method for producing a semiconductor wafer according to claim 1.   In the polishing step, at least one of the main surfaces of the flattened semiconductor wafer, in which the chamfer width of the chamfered portion is adjusted in a range of 50 μm or more and 200 μm or less, is polished according to ROA and ESFQR standards. The manufacturing method of the semiconductor wafer of Claim 1 or Claim 2 to do.   The standard of the ROA is 200 nm or less when the ROA of the semiconductor wafer after polishing is measured with the outer periphery exclusion region being 0.5 mm, or 50 nm or less when the outer periphery exclusion region is 1.0 mm. The method of manufacturing a semiconductor wafer according to any one of claims 1 to 3, wherein:   5. The ESFQR standard according to claim 1, wherein an ESFQRave of a rectangular region having a periphery of 1 mm to 35 mm and an angle of 5 ° is 65 nm or less. Semiconductor wafer manufacturing method. A chamfered portion is formed on the outer periphery, and at least one main surface is polished semiconductor wafer,
A diameter of the semiconductor wafer is 0.3 mm or less larger than a desired diameter, and a chamfer width from an outer peripheral end of the semiconductor wafer to a boundary position between the chamfered portion and the main surface is 50 μm or more and 250 μm or less. The ROA of the outer peripheral portion is 200 nm or less when measured with an outer peripheral exclusion region of 0.5 mm, or 50 nm or less when measured with an outer peripheral exclusion region of 1.0 mm, and the outer periphery of the semiconductor wafer is 1 mm to 35 mm. A semiconductor wafer characterized in that ESFQRave of a rectangular region having an angle of 5 ° is 65 nm or less.   The diameter of the said semiconductor wafer is 0.05 mm or more and 0.2 mm or less larger than a desired diameter, The semiconductor wafer of Claim 6 characterized by the above-mentioned.   The semiconductor wafer according to claim 6 or 7, wherein the chamfering width is 50 µm or more and 200 µm or less.

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