JP2007149923A - Planarization processing method of semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a planarization processing method of effectively planarizing a wafer by improving SFQRmax that is one of indexes of planarization. <P>SOLUTION: A planarization processing method of a semiconductor wafer implements a mirror surface polishing process, a surface shape measuring process, and a local dry etching process in this order. In the mirror finishing process, relative rotation is imparted to a platen on which abrasive cloth is stuck and to a holding tool, and the semiconductor wafer is subject to mirror finishing processing while supplying a polishing composition. In the surface shape measuring process, the surface shape of the semiconductor wafer is measured after the mirror finishing process. In the local dry etching process, neutral active species gas has been changed to electrically neutral in the course of flowing down from a plasma producer, and is blown off to the surface of a workpiece through a relatively movable nozzle. Materials are removed from the surface while controlling at least one among a relative speed, a distance between the workpiece and the nozzle, plasma output of the plasma producer, and gas flow rates in response to the measured surface shape. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention is a semiconductor wafer flattening method having a mirror polishing process of a workpiece, a surface shape measurement process of the workpiece, and a local dry etching process, and SFQRmax ( The present invention relates to a method for planarizing a semiconductor wafer to improve the following.

  A semiconductor wafer such as a silicon wafer or a compound wafer is sliced from a single crystal ingot, and then the thickness is adjusted by lapping or grinding, and one or both surfaces thereof are finished to a mirror surface through a mirror polishing process. In the manufacturing process of semiconductor wafers, flattening of semiconductor wafers has been a challenge for many years, increasing wafer size and edge exclusion (invalid areas around semiconductor wafers, usually expressed as distance from the edge). Development is underway based on issues such as demands for reduction of power consumption and device wiring miniaturization.

  By increasing the size of the semiconductor wafer and reducing the edge exclusion, the effective area ratio that can be taken out of the chip is increased, and the yield of the semiconductor chip is improved. For this reason, as for the width of edge exclusion, in recent years, it has been required to suppress the width of edge exclusion to 2 mm or less with a 200-300 mm size silicon wafer.

  Furthermore, regarding the miniaturization of device wiring, according to the International Technology Roadmap for Semiconductors, the target wiring width of the device is 90 nm in 2004, 65 nm in 2007, 50 nm in 2010, and 35 nm in 2013. As shown, the demand for miniaturization of the wiring width of the device has been increasing year by year.

  As device wiring widths become finer, higher quality is required for the flatness of semiconductor wafers. Of the required flatness of a semiconductor wafer, SFQRmax is required to have a value that is almost the same as the wiring width, and as the device wiring width becomes finer, improving the quality of the SFQRmax of the semiconductor wafer is an essential issue. ing.

  SFQR (Site Front Least Squares Range) calculates the reference plane (regression plane) in the site by the least square method from all the data showing the surface position of each point in the surface reference site. It is the sum of the maximum and minimum values, and there are as many sites for each wafer. SFQRmax indicates the maximum value of SFQR at all the sites in the wafer, and there is one value for each wafer.

  The cause of worsening the flatness of the semiconductor wafer is a surface roughness with a short wavelength such as Ra. Here, Ra (arithmetic mean roughness) is obtained by extracting the reference length L from the roughness curve, integrating the absolute value of the deviation from the average line of this portion to the roughness curve, and dividing by the reference length L. Value.

  Also, since most semiconductor wafers are finished by wet mirror polishing, ring-shaped sagging at the outer periphery, which is also called roll-off, is one of the causes. In order to improve the flatness of these semiconductor wafers, various techniques as shown in the following Patent Documents 1 to 10 have been developed.

JP 2002-16049 A Japanese Patent Laid-Open No. 2004-22676 JP-A-11-260771 JP 2003-324081 A JP 2002-231700 A JP 2001-176845 A JP 2001-210626 A Japanese Patent Application No. 2004-258777 JP 2000-754 A JP 11-235662 A

  However, as shown in the international semiconductor technology roadmap, progress in miniaturization of device wiring is remarkable, and it is certain that higher flatness is required. An object of the present invention is to provide a planarization processing method for improving SFQRmax, which is one of indices of flatness, and efficiently planarizing a wafer.

  The above problem is solved by the following means. That is, the solution of the first invention is a semiconductor wafer flattening method in which a workpiece mirror polishing step, a workpiece surface shape measuring step, and a local dry etching step are performed in this order. The mirror polishing step is a step of applying a relative rotation to the surface plate to which the polishing cloth is attached and the semiconductor wafer held by the holder, and polishing the semiconductor wafer while supplying the polishing composition. The surface shape measuring step is a measuring step for measuring the surface shape of the semiconductor wafer that has undergone the mirror polishing step, and the local dry etching step is electrically neutral while flowing down from the plasma generator. The neutral activated species gas is sprayed onto the surface of the work piece through a nozzle that can be moved relative to the surface of the workpiece. Surface shape of the workpiece by removing material from the surface of the workpiece while controlling at least one of the relative speed, the distance between the workpiece and the nozzle, the plasma output of the plasma generator and the gas flow rate. This is a method for planarizing a semiconductor wafer, which is a dry etching process for correcting the above.

  According to a second aspect of the present invention, there is provided a semiconductor wafer planarizing method according to the first aspect, wherein the mirror polishing step is a single-side polishing or a double-sided mirror polishing step. This is a flattening method.

  According to a third aspect of the invention, there is provided a semiconductor wafer flattening method according to the first or second aspect of the invention, wherein an etching rate in the local dry etching step is formed by an oxide film formed on the surface of the semiconductor wafer. In order to prevent the semiconductor wafer from being affected, a chemical etching process for removing the oxide film is performed after the mirror polishing process and immediately before the local dry etching process. This is a flattening method.

  After completion of the mirror polishing process, a silicon oxide film generally called a natural oxide film is formed on the surface of the semiconductor wafer by oxidizing the surface silicon with the passage of time. When a natural oxide film is formed on the surface of the semiconductor wafer, this oxide film solves problems such as non-uniform etching rates that are likely to occur in the subsequent local dry etching process and haze that is likely to occur on the semiconductor wafer surface. The

  According to a fourth aspect of the present invention, in the method for planarizing a semiconductor wafer according to the first to third aspects of the invention, the local dry etching step is a step of partially correcting the shape of the semiconductor wafer. A method for planarizing a semiconductor wafer.

  In the present invention, the local dry etching process partially modifies the semiconductor wafer. Examining the SFQR value distribution at each site of the semiconductor wafer manufactured in the mirror polishing process, it was found that the SFQR value tends to increase at limited sites such as the outer periphery of the semiconductor wafer.

  Therefore, SFQRmax is improved by mitigating a sudden shape change of a limited site such as the outer peripheral portion of the semiconductor wafer.

  According to the planarization processing method of the semiconductor wafer of the present invention, SFQRmax is greatly improved, and thus a planarization processing method with extremely good production efficiency can be established.

  The present invention is a method for planarizing a semiconductor wafer in which a mirror polishing step, a surface shape measuring step of a workpiece, and a local dry etching step described below are performed in this order.

  In the mirror polishing step, the surface plate with the polishing cloth and the semiconductor wafer held by the holder are given a relative rotation, and at the same time have high conductivity and alkalinity made of silicon oxide particles dispersed in water. The material is removed from the surface of the semiconductor wafer while supplying a composition or the like. In general, the mirror polishing step includes two means: a single-side polishing method and a double-side polishing method. The polishing cloth used in the mirror polishing process is preferably a soft polishing cloth in the single-side polishing process and a hard polishing cloth in the double-side polishing process.

  Although it does not specifically limit as a polishing composition used for the grinding | polishing process of this invention, it is a composition containing the silicon oxide disperse | distributed to water, pH is in the range of 10.0 to 11.5, and it is for grinding | polishing. The electrical conductivity of the composition at 25 ° C. is preferably 30 milliS / m (unit: Siemens, m: meter) or more per 1% by weight of silicon oxide particles.

  Further, the primary particle diameter of silicon oxide is preferably 100 nm or less, and the concentration of silicon oxide is preferably 6% by weight or less. When the physical properties of the polishing composition deviate from this region, the polishing rate decreases, the surface quality of the workpiece is deteriorated by etching, and the depth of the ring-shaped sag generated on the outer periphery of the workpiece increases.

  The method for measuring the surface shape of the semiconductor wafer can employ a method for measuring capacitance, a method for measuring displacement by laser reflection, etc., but it is sufficient if the displacement at the nanometer level can be measured with high accuracy, particularly these specific measurements. The means is not limited.

  In the local dry etching step, a fluorine compound gas such as sulfur hexafluoride (SF6) is introduced into the plasma generator, and this gas is converted into plasma by irradiating microwaves or the like. Neutral activated species gas containing neutral activated species F radicals that have become electrically neutral while flowing down from the plasma generator is sprayed onto the surface of the workpiece through a nozzle that can be relatively moved.

  At the same time, at least one of the relative speed, the distance between the workpiece and the nozzle, the plasma output of the plasma generator, and the gas flow rate is controlled in accordance with the surface shape measured in the surface shape measuring step. Since the material on the surface of the workpiece reacts with the neutral active species and flows away as a gaseous compound, the material can be removed. Adjustment of the material removal amount at each position is usually performed by controlling the relative speed (scanning speed), thereby correcting the surface shape of the workpiece.

  In solving this problem, the unevenness shape and SFQR distribution of a high flatness wafer manufactured by a single-sided and double-sided polishing apparatus were examined in detail.

  FIG. 1A is a SFQR distribution of a semiconductor wafer manufactured by a general single-side polishing apparatus, and FIG. 1B is an example of a graph of the cross-sectional shape of FIG. FIG. 2A is an SFQR distribution of a semiconductor wafer manufactured by a general double-side polishing apparatus, and FIG. 2B is an example of a graph of the cross-sectional shape of FIG.

  As can be seen from these figures, the semiconductor wafer of FIGS. 1 and 2 has a region that does not satisfy the SFQR target value including SFQRmax (SFQR is set to 30 nm or less, and is a shaded portion in the figure). The diameter of the semiconductor wafer is 300 mm, and the measurement is performed by a measuring instrument manufactured by ADE.

  From the above, it has been confirmed in other samples that many of the high flatness wafers flattened by the polishing machine have non-uniform surfaces. Therefore, if processing for reducing SFQR in a region not satisfying the SFQR target value including SFQRmax of each semiconductor wafer is added, SFQRmax can also be reduced.

  The present invention is based on such knowledge, and a local dry etching method capable of setting a very thin thickness (etching rate) of about 30 to 40 nm is optimal for the above processing. Therefore, we decided to adopt this.

  Hereinafter, the method for planarizing a semiconductor wafer according to the present invention will be described in detail with reference to examples, but the present invention is not limited thereto. In the present invention, the mirror polishing step, the surface shape measuring step of the workpiece, and the local dry etching step are performed in this order. In some cases, a chemical etching step for removing an oxide film on the surface of the semiconductor wafer is interposed immediately before the local dry etching step.

Mirror polishing process In this example, a double-side polishing machine manufactured by Speedfam was used as a general polishing apparatus. As the polishing cloth, MHS-15A (manufactured by Nitta Haas) was used. The polishing composition was prepared and used in-house. In the single-side polishing apparatus, a single-side polishing apparatus manufactured by Speed Fam Co., Ltd. was used. Suba800 (manufactured by Nitta Haas) was used as the polishing cloth. The polishing composition was adjusted and used in-house.

<Aqueous polishing composition>
An aqueous polishing composition was prepared using colloidal silica produced by hydrolyzing tetramethoxysilane. The physical properties of the aqueous polishing composition were pH 11.3, primary particle size 18.3 nm, silicon oxide concentration 1.0%, and conductivity 38 mS / m / kg-SiO2. To this composition, hydroxyethyl cellulose was added to a concentration of 0.1%.

Surface shape measurement step After polishing, the surface of the semiconductor wafer was measured using an ADE measuring instrument to determine SFQR. The result has already been shown in FIG. 1 and FIG.

Chemical etching step After the completion of the double-side polishing step, specifically, after the completion of the surface shape measurement step, the oxide film formed on the surface of the semiconductor wafer was removed by the chemical etching step. In this example, a 1.0% hydrofluoric acid aqueous solution was used, and etching treatment was performed at room temperature for 60 seconds. This is because a silicon oxide film generally called a natural oxide film is formed on the surface of a semiconductor wafer by oxidizing the surface silicon over time. The purpose of this step is to remove this natural oxide film.

  If a natural oxide film is formed on the surface of a semiconductor wafer, problems such as non-uniform etching rate and haze on the surface of the semiconductor wafer are likely to occur in the subsequent local dry etching process. This is because the oxide film is removed.

  Normally, after the polishing process is completed, specifically, after the surface shape measurement process is completed, a considerable time elapses until the local dry etching process is performed. In this example, the chemical etching process is also interposed. Although the natural oxide film is very thin, the amount of removal in the subsequent local dry etching process is very small. Therefore, although the natural oxide film is removed or not, it appears as a large difference in the degree of improvement of SFQR. is there.

Local dry etching process For the local dry etching, a DCP-300X plasma etching apparatus (manufactured by Speed Fam Co., Ltd.) was used. Table 1 in FIG. 5 shows various conditions in the local dry etching process. From the measurement result in the surface shape measurement step, the removal amount to be removed at each position by local dry etching, that is, the scan speed is calculated, and dry etching is performed while controlling the scan speed. In addition to controlling the scan speed, the distance between the semiconductor wafer and the nozzle, the plasma output from the plasma generator, and the gas flow rate may be controlled.

  The etching gas supplied to the plasma generator was mixed with a large amount of helium gas and nitrogen gas, and the etching rate was lowered by reducing the ratio of sulfur hexafluoride (SF6).

  As can be seen from the above, since the SFQRmax of the semiconductor wafer can be improved by improving the flatness of the region that does not satisfy the SFQR target value including SFQRmax, the region is processed by local dry etching. Just do it.

  As described above, since only the region not satisfying the SFQR target value including SFQRmax is removed, the throughput is improved as compared with the case where the entire surface of the semiconductor wafer is scanned. Furthermore, since an etching gas having a low removal capability is used, damage to the semiconductor wafer is small.

  In addition, after the local dry etching step, it is possible to further perform a local dry etching or wet polishing step under different conditions in order to improve the surface state of the semiconductor wafer.

Results and evaluation of this example The results of this example are shown. 3A shows the SFQR distribution of the semiconductor wafer after the local dry etching process, FIG. 3B shows a graph obtained by measuring the cross-sectional shape of FIG. 3A, and FIG. Fig. 4B is a graph obtained by measuring the SFQR distribution of the semiconductor wafer after the local dry etching process, and Fig. 4B is a graph obtained by measuring the cross-sectional shape of Fig. 4A.

  SFQR in each region is shown in FIG. 3A and FIG. 4A, and it can be seen that SFQRmax is improved as shown in FIG.

  As described above, according to the method for planarizing a semiconductor wafer of the present invention, the yield of a product from one silicon wafer could be remarkably improved. In other words, in actual semiconductor-related production, the contribution is extremely large.

It is SFQR distribution of the semiconductor wafer manufactured with the common single-side polish apparatus. It is an example of what graphed the cross-sectional shape of Fig.1 (a). It is SFQR distribution of the semiconductor wafer manufactured with the common double-side polish apparatus. It is an example of what graphed the cross-sectional shape of Fig.2 (a). It is SFQR distribution of the semiconductor wafer which performed the local dry etching process about the semiconductor wafer of FIG. It is the graph obtained by measuring the cross-sectional shape of (FIG. 3a). It is SFQR distribution of the semiconductor wafer which performed the local dry etching process about the semiconductor wafer of FIG. It is the graph obtained by measuring the cross-sectional shape of Fig.4 (a). It is Table 1 which shows the various conditions in a local dry etching process.

Claims (4)

  A method of planarizing a semiconductor wafer in which a mirror polishing process of a workpiece, a surface shape measurement process of the workpiece, and a local dry etching process are performed in this order, and the mirror polishing process is performed by attaching a polishing cloth. The surface shape measuring step is a step of mirror polishing the semiconductor wafer while supplying a polishing composition while giving a relative rotation to the surface plate and the semiconductor wafer held by the holder. Is a measurement process for measuring the surface shape of a semiconductor wafer that has undergone the above process, and the local dry etching process is a nozzle capable of relatively moving neutral activated species gas that has become electrically neutral while flowing down from the plasma generator And spraying on the surface of the workpiece through the relative speed, the distance between the workpiece and the nozzle according to the surface shape measured by the surface shape measurement step It is a dry etching process for correcting the surface shape of the workpiece by removing material from the surface of the workpiece while controlling at least one of the plasma output and gas flow rate of the plasma generator. A semiconductor wafer flattening method.   2. The method for planarizing a semiconductor wafer according to claim 1, wherein the mirror polishing step is a mirror polishing step by single-side polishing or double-side polishing.   3. The planarization method of a semiconductor wafer according to claim 1, wherein the oxide film formed on the surface of the semiconductor wafer is prevented from being affected by an etching rate in the local dry etching process. A method for planarizing a semiconductor wafer, wherein a chemical etching step for removing the oxide film is performed immediately after the mirror polishing step and immediately before the local dry etching step.   4. The method for planarizing a semiconductor wafer according to claim 1, wherein the local dry etching step is a step of partially correcting the semiconductor wafer. Chemical processing method.

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