JPWO2020055571A5 - - Google Patents

Description

Cross-reference to related applications

(Cross reference to related applications)
This application claims the priority benefit of US Provisional Patent Application No. 62/729,134, filed September 10, 2018. The disclosure of that US provisional patent application is incorporated herein by reference for all relevant and consistent purposes.

(Field of Disclosure)
The field of the present disclosure relates to methods for polishing semiconductor substrates. In particular, the field of the present disclosure involves adjusting the finish polishing sequence based on pad-to-pad variation (or pad-to-pad variation, offset or variance, pad-to-pad variance) in the polishing pad. The present invention relates to a method for polishing a semiconductor substrate.

(background)
Semiconductor wafers are commonly used in the manufacture of integrated circuit (IC) chips on which electrical circuits are printed. Electrical circuits are first printed in microscopic form on the surface of the wafer, and then the wafer is divided into circuit chips. Such fine electrical circuits require that the front and back sides of each wafer be extremely flat and parallel to ensure that the electrical circuits are properly printed across the entire surface of the wafer. For this reason, grinding and polishing processes are often used to improve the flatness and parallelism of the front and back sides of the wafer after the wafer is cut from the ingot. A particularly good finish is required when wafer polishing is performed in preparation for printing miniaturized electrical circuits on the wafer by e-beam lithographic or photolithographic processes. The wafer surface on which the miniaturized electrical circuits are to be printed should be flat.

Polishing processes can introduce changes in the profile of a semiconductor wafer, causing variations near the edges of the structures due to uneven distribution of mechanical and/or chemical forces near the edges. can be For example, the thickness profile may be reduced at the peripheral edges of the structure, ie, an "edge roll-off" may be observed. Edge roll-off reduces the portion of the wafer available for device fabrication. Although edge roll-off can be controlled through dynamic control methods such as those disclosed in U.S. Patent Publication No. 2017/0178890, variations (or variations) between polishing pads can affect the edge roll-off of the substrate being polished. can cause a difference in Such variations may result from allowed tolerances within the manufacturing process and may arise due to pad compressibility and/or thickness variations.

A semiconductor substrate that minimizes edge roll-off while offsetting variations in edge roll-off that may be due to pad-to-pad variation and that improves substrate flatness and/or surface roughness. There is a need for a polishing method.

This section is intended to introduce the reader to various technical aspects that may be related to various subject matter (or aspects) of the disclosure described and/or claimed herein. ing. The material discussed herein is believed to be useful in providing background information to the reader and is believed to aid in a better understanding of various aspects of the present disclosure. Accordingly, such discussion should be read in that light and should not be understood as being admitted as prior art.

SUMMARY OF THE INVENTION One subject of the present disclosure is directed to a method for polishing a semiconductor substrate(s). Each substrate has a front side and a back side substantially parallel to the front side. The front surface of the first semiconductor substrate is brought into contact with the polishing pad. A polishing slurry is supplied to the polishing pad to polish the front surface of the first semiconductor substrate, resulting in a polished first semiconductor substrate. Edge roll-off of the first semiconductor substrate is measured. The front surface of the second semiconductor substrate is brought into contact with the polishing pad. A polishing slurry is supplied to the polishing pad to polish the front surface of the second semiconductor substrate. The amount of polishing slurry supplied to the polishing pad while the second semiconductor substrate is in contact with the polishing pad (or while the second semiconductor substrate is in contact with the polishing pad, or while the second semiconductor substrate is in contact with the polishing pad) is controlled based at least in part (or at least in part) on the measured edge roll-off of the first semiconductor substrate.

Another aspect of the present disclosure is directed to a method for finish-polishing a semiconductor substrate(s). Each substrate has a front side and a back side substantially parallel (or substantially parallel) to the front side. The lifetime of the polishing pad is determined. Only the front surface of the semiconductor substrate is brought into contact with the polishing pad. A polishing slurry is supplied to the polishing pad to polish the front surface of the semiconductor substrate, resulting in a polished semiconductor substrate. The amount of polishing slurry supplied to the polishing pad while the semiconductor substrate is in contact with the polishing pad (or while the semiconductor substrate is in contact with the polishing pad, or while the semiconductor substrate is in contact with the polishing pad) determines the life of the polishing pad. controlled at least in part (or at least in part) based on time;

Various modifications and improvements are conceivable for the features noted in connection with the above aspects of the disclosure. Additional features may also be incorporated for the above-described aspects of the disclosure. Such modifications, improvements and additional features may exist individually or in any combination. For example, the various features described below in accordance with any illustrated aspect of the disclosure may be incorporated in any of the above-described aspects of the disclosure, particularly alone or in combination. .

FIG. 1 is a schematic diagram of a final polishing apparatus. FIG. 2 is a cross-sectional view of a wafer schematically showing the measurement of the roll-off amount. FIG. 3 is a graph showing variations in the amount of material removed across the wafer radius for different finish polish conditions. FIG. 4 is a graph showing the change in edge roll-off of a finish polished wafer as the amount of the first silica-containing polishing slurry is varied. FIG. 5 is a graph showing changes in near-edge (or near-edge) flatness of a final-polished wafer when the amount of the first silica-containing polishing slurry is varied. FIG. 6 is a box plot showing the change in edge roll-off of a finish polished wafer with varying amounts of alkaline polishing slurry. FIG. 7 is a graph showing the change in edge roll-off of a wafer being finish polished when the first silica-containing polishing slurry and the second silica-containing polishing slurry are supplied for varying times. FIG. 8 is a graph showing the change in edge roll-off of a finish-polished wafer with change in pad lifetime. FIG. 9 is a graph showing the change in edge rolloff of a finish polished wafer as the global flatness of the wafer changes.

Corresponding reference numbers indicate corresponding parts/parts throughout the drawings.

The present disclosure provides a method for polishing/polishing a plurality of semiconductor substrates. Suitable substrates (which may also be referred to herein as "wafers" or "structures") include monocrystalline silicon substrates, including substrates obtained by slicing wafers from ingots formed by the Czochralski method. be Each substrate includes a central axis, a front surface, and a back surface generally parallel to the front surface. The front side surface and the back side surface are substantially perpendicular to the central axis. A peripheral edge joins the front and back sides, and a radius extends from the central axis to the peripheral edge. Structures polished according to the methods of the present disclosure may have any diameter suitable for use by those skilled in the art, such as 200 mm diameter, 300 mm diameter, or greater than 300 mm diameter, or even , a wafer having a diameter greater than 450 mm.

In one or more aspects of the present disclosure, a semiconductor substrate is polished (eg, finish polished) and the polished semiconductor substrate is subjected to analysis to determine edge roll-off. Edge rolloff is used to determine the pad-to-pad variation in pads (ie, the deviation (or deviation) from the average rolloff for pads of the same type). The polishing process may be adjusted based at least in part on the measured edge rolloff. In some embodiments, batches of semiconductor structures are polished and edge rolloff measured for batches of wafers is used to adjust a polishing sequence. be.

In one or more aspects of the present disclosure, polishing a semiconductor substrate in one or more steps prior to determining the pad-to-pad variation of one of the plurality of pads used in the polishing sequence. You can For example, in some embodiments, a first polishing step is performed in which the front side of the structure and optionally its back side are polished (ie, a double side polishing is performed). Generally, the polish is a "rough" polish, which reduces the surface roughness of the wafer from less than about 3.5 Å to as low as about 2.5 Å, even as low as about 2 Å (about 1 μm x about 1 μm to about 100 μm x about 100 μm as measured by an atomic force microscope (AFM)). For the purposes of this specification, surface roughness is expressed as root mean square (RMS), unless otherwise specified. Rough polishing typically removes from about 1 μm to about 20 μm of material from the surface of the wafer, more typically from about 5 μm to about 15 μm.

A rough polish (and a final polish, described below) can be accomplished, for example, by chemical mechanical planarization (CMP). CMP typically involves dipping the wafer in an abrasive slurry and polishing the wafer with a polymer pad. Through a combination of chemical and mechanical action, the surface of the wafer is smoothed. Polishing is typically performed until chemical and thermal steady state conditions are obtained and until the wafer achieves the desired shape and flatness. A double sided polisher (e.g. AC2000 polisher) from Peter Wolters, Lenzburg, Germany, or a double sided polisher from Fujikoshi, Tokyo, Japan or Speedfam, Kanagawa, Japan. Rough polishing may be performed with a side polisher. Stock removal pads for silicon polishing are available from Psiloquest (Orlando, Fla.), Dow Chemical Company (Midland, Mich.). Silica-based slurries are available from Dow Chemical Company, Cabot (Boston, MA), Nalco (Naperville, IL), Bayer MaterialScience (Leverkusen, Germany), DA NanoMaterials (Tempe, AZ) and Fujimi (Kyoso Japan). ing.

The rough polishing step is performed for about 300 seconds to about 300 seconds with a slurry flow rate of about 50 mL/min to about 300 mL/min (or about 75 mL/min to about 125 mL/min) and a pad pressure of about 150 g/cm ² to about 700 g/cm ² . It may take about 60 minutes. However, other polishing times, pad pressures and slurry flow rates may be employed without departing from the scope of this disclosure.

After the rough polish is completed, the wafer is rinsed and dried. Additionally, the wafer may be subjected to wet bench cleaning or spin cleaning. Wet bench cleaning involves contacting the wafer with SC-1 cleaning solutions (ie, ammonium hydroxide and hydrogen peroxide), optionally at elevated temperatures (eg, about 50° C. to about 80° C.). ° C.), such wafers are contacted with the SC-1 cleaning solution. Spin cleaning involves contact with an HF solution and ozonated water and may be performed at room temperature.

After cleaning, a second polishing step may be performed. The second polishing step is typically a "finish" or "mirror" polish, in which the front side of the substrate is polished with a polishing pad attached to a turntable or platen. is brought into contact with The final polish reduces the surface roughness of the wafer to less than about 2.0 Å (as measured by AFM with a scan size of about 10 μm×about 10 μm to about 100 μm×about 100 μm). The final polish may reduce the surface roughness of the wafer to less than about 1.5 Å or less than 1.2 Å (scan size of about 10 μm×about 10 μm to about 100 μm×about 100 μm). Typically, only about 0.5 μm or less of material is removed from the surface in the final polish.

Referring to FIG. 1, a suitable final polishing apparatus may include a polishing pad 1 mounted on a polishing table 7. FIG. The polishing head 31 holds the substrate 20 through the use of a retainer 25 so that the front surface of the substrate 20 is in contact with the polishing pad 1 . A slurry 38 is supplied to the polishing pad 1 . The polishing head 31 vibrates at a high speed so that the substrate 20 is moved relative to the polishing pad 1 for polishing the front surface of the substrate.

A suitable polisher for final polishing is available from Lapmaster SFT (eg, LGP-708, Chiyoda-ku, Tokyo). Suitable pads include polyurethane impregnated polyethylene pads such as SUBA pads from Dow Chemical Company, suede type pads (also called polyurethane foam pads) such as SURFIN pads from Fujimi, Ciyoda Company (Osaka, Japan). and SPM pads from The Dow Chemical Company.

The final polish (ie, the first table of final polishes) may be performed for at least about 60 seconds, or even at least about 90 seconds, about 120 seconds, or about 180 seconds. A total slurry flow rate can range from about 500 mL/min to about 1000 mL/min (total as a mixture), and a pad pressure can range from about 60 g/cm ² to about 200 g/cm ² . It's okay. However, other polishing times, pad pressures and slurry flow rates may be employed without departing from the scope of this disclosure.

Final polishing may involve several polishing steps. For example, structures may be applied to several separate polishing sequences at two or more tables of a finish polisher (ie, at different workstations where different polishing pads are used). Also, the polishing slurry supplied to the polishing pad at a given table may be changed/changed during the polishing sequence.

One or more polishing slurries may be applied to the polishing pad in various sequences at the first table (ie, first polishing pad) of the polishing apparatus. According to aspects of the present disclosure, suitable slurries that may be used alone or in combination in a polishing sequence include a first polishing slurry comprising an amount of silica particles and a lower concentration of silica particles than the first polishing slurry. and a third polishing slurry that is alkaline (i.e., caustic) and typically contains no silica particles and a fourth polishing slurry that is deionized water. Contains no abrasive slurry. It should be noted that the term "slurry" as referred to herein refers to various suspensions and solutions, including solutions in which particles are not present, such as caustic solutions and deionized water. , is not specifically intended to imply the presence of particles in the liquid.

The silica particles of the first slurry and the second slurry may be colloidal silica, and the particles may be encapsulated with a polymer. Suitable first silica-containing polishing slurries are Syton-HT50 (Du Pont Air Products NanoMaterials, Tempe, Ariz.) and DVSTS029 (Nalco Water, St. Paul, Minn.). Suitable second silica-containing polishing slurries are Glanzox-3018 (Fujimi, Tokyo, Japan) and NP 8020 (Nitta Haas, Osaka, Japan).

The silica concentration in the first polishing slurry and the second polishing slurry may be altered using fewer silica particles in the second slurry. More typically, such concentrations are modified using silica particles that contain less silica in the particles themselves (ie, more polymer encapsulated and less silica).

In some aspects, the first polishing slurry includes a first set of silica particles and the second slurry includes a second set of silica particles. A first set of silica particles has a silica content of X ₁ and a second set of silica particles has a silica content of X ₂ , where X ₁ is greater than X ₂ . The silica content of the particles may be varied by individually encapsulating the particles in at least one set with a polymer, such that the degree of encapsulation (i.e., polymer thickness) is different between the two sets. . The polymer reduces the silica content in the set of particles. In some embodiments, the ratio of X ₁ to about X ₂ (the ratio of X ₁ to about X ₂ ) is at least about 2:1, or even at least about 3:1, at least about 5:1, At least 10:1, or even at least about 15:1. The difference between X ₁ and about X ₂ (ie, X ₁ -X ₂ ) is about 5 weight percent, at least about 10 weight percent, at least about 25 weight percent, or at least about 50 weight percent.

In some aspects, the silica particles in the first set of the first polishing slurry are individually encapsulated or encapsulated with a polymer, and the first set is at least about 50 weight percent silica, or at least about 60 weight percent silica. % silica, at least about 70% silica, or from about 50% to about 95% silica, from about 60% to about 95% silica, or from about 70% to about 90% silica Contains silica.

A second set of silica particles of the second polishing slurry may also be individually enclosed or encapsulated with a polymer. The second set of polymer-encapsulated silica particles may comprise less than about 25 wt% silica, in other aspects less than about 15 wt% silica, or less than about 10 wt% silica. Alternatively, from about 1% to about 25% silica, from about 1% to about 15% silica, or from about 1% to about 10% silica.

The third polishing slurry is alkaline. For example, the _third polishing slurry comprises KOH, NaOH or NH4 salts and typically does not contain silica particles. The slurry may have a pH greater than 12, such as from about 13 to about 14.

The first polishing slurry, second polishing slurry, third polishing slurry and fourth polishing slurry may be applied singly or in various combinations in various polishing sequences. In an exemplary sequence, in some aspects of the present disclosure, final polishing on the first table of the final polisher may begin with a first final polishing step, in which a first polishing comprising silica is applied. The polishing pad is simultaneously contacted with the slurry and the alkaline third polishing slurry. The two slurries may be combined in the polisher (ie, fed individually (or separately or separately) in the pad) or mixed prior to being fed to the pad.

In the second final polishing step of the first table, the second silica-containing polishing slurry and the third alkaline polishing slurry are simultaneously supplied to the polishing pad. A fourth slurry comprising deionized water may be used in the second step in addition to or in place of the third alkaline slurry. may be used. Generally, the second polishing slurry is applied to the pad only after the first polishing slurry has been sufficiently applied in the first step.

In the third final polishing step of the first table, a second polishing slurry comprising silica particles and/or a fourth polishing slurry comprising deionized water are supplied to the polishing pad. Generally, the third slurry does not contain alkali so as to prevent the formation of etching pits.

After the polishing sequence of the first table is completed, the semiconductor substrate may be transferred to the second table or even to the third table. The second and third tables may include polishing pads that are the same as the polishing pads of the first table or that are different from the polishing pads of the first table. A second polishing slurry having a lower silica concentration than the first slurry and/or a fourth slurry comprising deionized water may be used in the second and third tables.

In aspects of the present disclosure, a substrate, or batch of substrates, that has been subjected to polishing (e.g., a final polish) is subjected to analysis by measuring the edge roll-off of the substrates, thereby determining the polishing of the final polisher. Feedback is provided to adjust the sequence (eg, the sequence of the first table). The polished substrate is subjected to analysis to determine edge roll-off (“roll-off amount” or simply “ROA”).

The edge roll-off is M.I. It may be measured using a height data profile as disclosed by Kimura et al. Such M. Height data profiles such as those disclosed by Kimura et al. of Silicon Polished Wafer)/Jpn. Jo. Appl. Phys., Vol. incorporated into the specification. In general, Kimura's method has been standardized in the industry. Such Kimura's method is described, for example, in SEMI M69 (Practice for Determining Wafer Near-Edge Geometry using Roll-off Amount). 2007), which is also incorporated herein by reference for all relevance and consistency. Most commercially available wafer inspection equipment is pre-programmed to calculate ROA. For example, ROA may be determined by use of the KLA-Tencor Wafer Inspection System with WaferSight analysis hardware (Milpitas, Calif.).

Referring to FIG. 2, the ROA of wafer 20 is generally determined by referencing three points (P ₁ , P ₂ and P ₃ ) along the wafer radius. A reference line R is fitted between two points (P ₁ and P ₂ ). A third point (P ₃ ) is near (or near) the peripheral edge of the wafer where roll-off is routinely observed. ROA is the distance between the reference line R and the _third point P3. The reference line R may be fitted as a first order linear line or as a third order polynomial. For the purposes of this disclosure, reference lines may be fitted as first-order straight lines unless otherwise stated.

In this regard, the ROA can be expressed in terms of a front side ROA, a back side ROA, or a thickness ROA (ie, an ROA using an average thickness profile). The measurement of the front side ROA and the back side ROA involves fitting _a best fit reference line R between P1 and P2 along the front _side or back side respectively. , the thickness ROA involves fitting for a best-fit line for various wafer ₂₀ thicknesses between P1 and P2 ₍ i.e., the thickness ROA is and back side).

Although any of the three points can be chosen for ROA determination, one common method used in the art (especially the method used for 300 mm substrates) is the This includes using a first point that is approximately 80% of the wafer radius from the central axis and a second point that is approximately 93.3% of the wafer radius from the central axis of the wafer. Such points are approximately 120 mm and 140 mm from the central axis of the wafer for a 300 mm diameter wafer. A third point approximately 98.7% of the wafer radius from the central axis (i.e., a third point approximately 148 mm from the central axis for a 300 mm diameter wafer) may be used, and the distance between the reference line and the third point may be can be the ROA. or a third point about 98.0% of the wafer radius from the central axis, or a third point about 99.3% of the wafer radius from the central axis (a third point of about 147 mm or about 149 mm, respectively, for a 300 mm diameter wafer). point) may be used to determine the ROA.

ROA may be measured and averaged across several radii of the wafer. For example, the ROA for 2, 4 or 8 radii spaced angularly across the wafer may be measured and averaged. For example, 8 radius ROA (e.g. 8 radius ROA at 0°, 45°, 90°, 135°, 180°, 225°, 275° and 315° in the R-Θ coordinate system referred to in SEMI M69) ) may be measured.

As noted above, ROA measurements may involve front side profiles, back side profiles, or thickness profiles. In this regard, "ROA" as used herein refers to ROA measured by use of a best-fit thickness profile of the wafer (i.e., thickness rather than front-side ROA) unless otherwise specified. ROA) with a linear primary line established between 80% and 93.3% of the wafer radius, and the reference point at the annular edge portion of the wafer being the point at 98.7% of the radius It refers to ROA measured by using a best-fit thickness profile.

It is understood that the ROA for the thickness profile can be a positive number where the wafer is thicker at its peripheral edge, or a negative number where the wafer is thinner at its peripheral edge. want to be In this regard, the use of terms such as “less than” as used herein with respect to an ROA amount (whether positive or negative) means that the ROA is less than the stated amount. to about 0 (for example, an ROA of "less than about -700 nm" refers to an ROA of about -700 nm to about 0, and an ROA of "less than about 700 nm" refers to ROA ranging from about 700 nm to about 0). Furthermore, "greater than" (whether a positive or negative number) with respect to an ROA quantity means that the edge portion of the wafer is centered around the axis of the wafer, rather than the stated quantity. contains the roll-off amount further away from .

References to "delta ROA/ERO" (see Figures 4 and 6) refer to the change in ROA from the preceding previous process conditions. For negative ROA (e.g. -700 nm) where a "downward" (or fall-off) is observed at the edge, positive delta ROA/ERO is observed for edge roll-off under varied conditions. (i.e., the edge does not have much "down"), and the negative delta ROA/ERO indicates that there is additional "down" at the edge. For positive ROA (e.g., 700 nm) where an "up-tick" (or up-tick) is observed at the edge, positive delta ROA/ERO is more at the edge for changed conditions. It shows that there is "upwards" and less "upwards" at the edge for conditions where the negative delta ROA is changed.

In some aspects, after a new polishing pad is installed, one or more of the plurality of semiconductor substrates (e.g., a batch (or a collection of substrates or a group of substrates)) are Subject to analysis. The edge roll-off of the polished semiconductor substrate is used to determine pad-to-pad variation or deviation (eg, variation (or deviation) from an "average" edge roll-off). The measured edge rolloff of a polished semiconductor substrate (which may also be referred to herein as a "first" semiconductor substrate) or a batch of substrates (or a plurality of polished substrates) is subsequently polished. used to coordinate the polishing sequence of the first table of the finish polisher for a substrate (which may also be referred to herein as a "second" semiconductor substrate). For example, the amount of first polishing slurry supplied to the polishing pad may be controlled. In some aspects, the first polishing slurry volume and/or the second polishing slurry volume supplied at the first table is controlled based on the measured edge roll-off of the substrate subjected to analysis. The polishing process may be controlled for edge roll-off adjustment according to one or more of the techniques disclosed in U.S. Patent Publication No. 2017/0178890 (note that U.S. Patent Publication No. 2017/0178890 , incorporated herein by reference for all relevance and consistency).

In some aspects of the present disclosure, edge roll-off in a batch of a first semiconductor substrate or substrates is used to polish a first semiconductor substrate to determine pad-to-pad variation of the polishing pad. The pad is compared to the average edge rolloff of a polishing pad of the same type. The amount of polishing slurry (e.g., first silica-containing slurry) supplied to the polishing pad while the second semiconductor substrate is in contact with the polishing pad (or while the second semiconductor substrate is in contact with the polishing pad) is may be based, at least in part, on the difference between the measured edge rolloff of 1 and the average edge rolloff of polishing pads of the same type. The average edge rolloff for a particular type of polishing pad may be determined from a previous polishing run using the same type of pad.

In embodiments in which a polished first semiconductor substrate (or a plurality of polished first semiconductor substrates) is subjected to analysis by measuring edge roll-off to determine the pad-to-pad variation of the polishing pad, the pad is It may be a new pad provided on the table. The semiconductor substrate (or semiconductor substrates) may (ideally) be the first semiconductor structure to be polished with a new pad, or the first five (or first) to be polished with a new polishing pad. 5), first 10 (or first 10), or first 20 (or first 20) substrates. In aspects where a new polishing apparatus and/or pad arrangement is used, many wafers (e.g., the first (or first) 50, 100 or 200 wafers) achieve stable removal A first semiconductor substrate (or a plurality of first semiconductor substrates) that has been first polished to , and then polished as mentioned above measures the edge roll-off to determine the pad-to-pad variation of the polishing pad. may be subjected to analysis by

In some aspects, a batch of multiple substrates is subjected to analysis by measuring edge roll-off of each substrate, determining pad-to-pad variation in a polishing pad (e.g., a new pad), and performing a polishing process. is adjusted. A batch may include at least two (or two) semiconductor substrates, or in other aspects at least 5, at least 10, at least 15 or at least 20 semiconductor substrates. . Each measured edge rolloff for the polished semiconductor substrate may be averaged, and the amount of polishing slurry supplied to the polishing pad between contacting the second semiconductor substrate with the polishing pad is averaged for the batch. may be based, at least in part, on the amount of roll-off.

In some aspects, the ratio of the "first abrasive slurry volume supplied at the first table" to the "second abrasive slurry volume supplied at the first table" is adjusted. As shown in Examples 2 and 4 below, by reducing the supply of the first silica-containing polishing slurry relative to the second silica-containing slurry, the edge produced during final polishing • Roll-off is reduced (ie, a negative ROA indicating the presence of roll-off at an edge becomes less "negative"). If the edge roll-off is expected to be larger (i.e., due to pad-to-manufacture variations) as predicted from the measured roll-off of the structures subjected to analysis. , the supply rate of the first silica-containing polishing slurry supplied relative to the second silica-containing slurry may be reduced, thereby increasing edge roll-off due to pad-to-pad variability may be offset. If the edge roll-off is expected to be smaller (i.e., smaller due to pad-to-manufacture variations) as predicted from the measured roll-off of the structures subjected to analysis. , the supply amount of the first silica-containing polishing slurry supplied relative to the second silica-containing slurry may be increased, thereby offsetting the increase due to pad-to-pad variation.

In some aspects, by varying the length of time that the first silica-containing slurry is applied to the polishing pad and/or varying the amount of time that the second silica-containing slurry is applied to the polishing pad. adjusts the ratio of the first slurry to the second slurry. For example, the total time during which the first and second slurries are supplied may be maintained constant while the time during which the first and second slurries are supplied to the pad is varied.

Alternatively, or in addition to adjusting the ratio of the first and second silica-containing polishing slurries, the amount of alkaline third polishing slurry added to the first table (i.e. (total amount of alkali added in ) is adjusted based on the measured edge roll-off of the substrates subjected to analysis. In some aspects, the amount of the third alkaline polishing slurry added simultaneously with the second silica-containing polishing slurry is controlled for edge roll-off adjustment. As shown in Example 3 below, increasing the amount of alkali added during the first table run of the finish polisher reduces the edge roll-off that occurs during the finish polish (i.e. A negative ROA is less "negative" indicating the presence of roll-off at the edge). The amount of alkaline polishing slurry supplied at the first table of the finish polisher may be increased based on the measured increase in roll-off due to pad-to-pad variation, or the amount of roll-off due to pad-to-pad variation. It may be reduced based on the measured reduction.

In some aspects, the target edge roll-off is determined and the process conditions (e.g., amount of silica-containing first polishing slurry and/or amount of alkaline third polishing slurry) are adjusted for the analyzed structure (or structures). based on the determined pad-to-pad variation from the edge rolloff of the object). In addition to measuring edge roll-off, the feedback control method evaluates other parameters such as wafer flatness and improves edge roll-off without unacceptable degradation of wafer flatness. may be done to control the polishing parameters to achieve. Other parameters may be monitored to ensure process quality (eg, to verify the presence of etch pits, etc.).

subsequently used in lieu of or in addition to controlling the amount of polishing slurry supplied to polishing based on the edge roll-off of the first semiconductor substrate (or first semiconductor substrates); The amount of polishing slurry to be applied may be based at least in part on one or more other parameters associated with the polishing process. For example, the amount of polishing slurry supplied to the polishing pad between contacting the second semiconductor substrate with the polishing pad may be based at least in part on the lifetime of the polishing pad.

The lifetime of the pad may be determined based on the number of substrates polished by the pad, or the time the pad is used to polish substrates, or any other suitable method (e.g., time multiplied by the polishing pressure). may be determined by the accumulation/accumulation value of The lifetime may be normalized to the average lifetime the pad is typically used for, or it may be normalized to a given lifetime after pad replacement. As shown in FIG. 8, edge roll-off generally increases as pad lifetime increases. By reducing the amount of the first silica-containing polishing slurry supplied, the edge roll-off that occurs in the final polish can be reduced (i.e., the negative ROA indicating the presence of roll-off at the edge is less "negative"). ”), offsetting the increased edge roll-off due to the increased lifetime of the pad. Alternatively, the amount of the third slurry (ie alkaline slurry) may be adjusted.

In some aspects, the polishing process is adjusted based at least in part on the measured flatness (or flatness or flatness) of the second semiconductor wafer. As shown in FIG. 9, increased doming (ie, doming between wafer center and edge areas) causes increased edge roll-off. Such an increase may be offset (or offset) by reducing the amount of the first silica-containing polishing slurry supplied to the pad (e.g., reducing the amount of the first silica-containing polishing slurry relative to the second silica-containing slurry). , the edge roll-off that occurs in the final polish may be reduced. Alternatively, the amount of alkaline slurry may be adjusted.

Compared to conventional methods for polishing substrates, the method of the present disclosure has several advantages. By measuring the edge roll-off in a batch of first semiconductor substrates or substrates (or polished substrates or first semiconductor substrates) after a new polishing pad has been placed on the polishing table, the pad- A pad-to-pad variation of the pad can be determined, thereby allowing the polishing process to be prepared for the substrate to be subsequently polished. Deviations (or deviations) from the average expected roll-off for the polishing pad can be dynamically offset during the final polishing sequence by decreasing or increasing the amount of silica-containing or alkaline polishing slurry. . Adjusting the polishing process to account for effects on edge roll-off due to polishing pad lifetime and/or flatness of the semiconductor being polished further drives the polishing process to achieve more consistent roll-off. becomes possible. Such methods are particularly useful for reducing edge roll-off in single-sided polishing processes where less than about 0.5 μm of material is removed from the surface of the structure (which is typical in polishing 300 mm diameter wafers). can be.

The processes of the present disclosure are further illustrated by the following examples. Such examples should not be viewed as limiting the present disclosure.

Example 1 : Effect of Varying Amounts of First and Second Silica Slurries on Removal Profile in Final Polishing A double-sided rough-polished wafer was subjected to final polishing with a single-sided polisher. In the first polishing step of the first table of the final polishing apparatus, a first polishing slurry comprising silica particles (Syton-HT50) and an amount of alkaline polishing slurry (KOH) were supplied to the polishing pad. In a second step, a second polishing slurry comprising silica particles (a mixture of Glanzox-3018 and NP 8020) and alkali were fed to the table. The second silica-containing slurry contained less silica than the first silica-containing slurry. In a third step, a second silica-containing slurry and deionized water were supplied to the pad.

The wafer was transferred to the second table, followed by the third table. In both Tables 2 and 3, a second silica-containing polishing slurry and deionized water were supplied to the pads.

The amounts of the first silica-containing slurry and the second silica-containing slurry were varied from the conventional polishing method for several runs of wafers. Normalized removal for various runs was measured after treatment with the first, second and third tables. As shown in FIG. 3, the use of additional first slurry resulted in increased removal at the edges (increased edge roll-off). Using less first slurry also resulted in increased removal at the edge of the wafer. However, the change in removal (i.e., the degree of removal near 148 mm compared to the fitted line showing the change in removal towards the edge) was greater when additional first slurry was used, with the first It was shown that edge roll-off increased with increasing slurry. The use of additional second slurry resulted in less removal towards the edge of the wafer and reduced roll-off.

Example 2 Effect of Varying First Silica-Containing Slurry in Final Polishing The polishing process of Example 1 was performed while adjusting the total flow of the first silica-containing polishing at the first table of the final polisher. FIG. 4 shows the change in edge roll-off (measured at 148 mm) before and after finish polishing (finish ROA-coarse ROA). As shown in FIG. 4, using a small volume of the first silica-containing polish reduces edge roll-off (ie, negative ROA becomes less "negative"). Such improvement diminishes with additional volume of the first silica-containing polishing slurry. The volume to the right of the intersection with the x-axis shows the increase in edge roll-off caused by the use of additional first slurry.

FIG. 5 shows the near edge flatness (ESFQR) variation for a wafer. As shown in FIG. 5, near-edge flatness degrades (or worsens) with the use of additional volumes of the first silica-containing polishing slurry in the first table of the finish polisher. Become.

Example 3 : Effect of Varying the Amount of Alkali in Final Polishing In the second polishing step of Table 1 of the finishing process described in Example 1, the ratio of the amount of alkali to the amount of the second silica-containing slurry was varied. The wafer edge roll-off was measured (measured at 148 mm) after the final polish.

A box plot of the results is shown in FIG. As shown in FIG. 6, at a second silica-containing slurry volume of 20 mL (first 5 data points), edge roll-off improved with increasing alkali content. This is also seen in the data points for the 25 mL second silica-containing slurry.

Example 4 : Effect of Varying First and Second Silica Slurry Time on Removal Profile in Final Polish Double-sided rough polished wafers were subjected to final polishing in a single-sided polisher. In the first polishing step in the first table of the final polishing apparatus, a first polishing slurry comprising silica particles (DVSTS029 from Nalco) and an amount of alkaline polishing slurry (KOH) were supplied to the polishing pad. In a second step, a second polishing slurry comprising silica particles (NP 8020H from Nitta Haas) and alkali were fed to the table. The second silica-containing slurry contained less silica than the first silica-containing slurry. The relative feed rates for the first and second steps are shown in Table 1 below.

表１：第１テーブルの第１工程および第２工程における第１および第２のシリカ・スラリーのフィード・レートならびにアルカリのフィード・レート（Ｘ＋Ｙ＝３５秒） [Table 1]

Table 1: Feed rate of first and second silica slurries and feed rate of alkali (X+Y = 35 seconds) in first and second steps of the first table

In a third step, a second silica-containing slurry and deionized water were supplied to the pad.

The total polishing time for steps 1 and 2 was held constant at 35 seconds. The amount of time for step 1 (“X”) and the amount of time for step 2 (“Y”) are varied and the change in edge rolloff is shown in FIG. As shown in FIG. 7, increasing the time of the first polishing step caused an increase in roll-off (ie, the negative ROA became more "negative").

Example 5 Effect of Pad Lifetime on Edge Roll-off FIG. 8 shows the change in edge roll-off before and after final polishing with increasing pad lifetime, normalized It is shown. As can be seen from FIG. 8, the edge rolloff increases (ie becomes more "negative") as the lifetime of the pad increases.

Example 6 Effect of Wafer Flatness on Edge Roll-off Wafer doming (i.e. thickness variation between center and edge, positive parameters result in domed wafers, negative numbers results in a dished wafer) was measured before and after the finish polish ("delta doming"), and the edge roll-off of the wafer was measured before and after the finish polish ("delta roll-off"). FIG. 9 shows the change in roll-off as a function of change in delta doming. As shown in FIG. 9, increased delta doming resulted in decreased edge roll-off (ie, less "negative" edge roll-off of "negative").

As used herein, the terms "about," "substantially," "essentially," and "approximately" refer to dimensions, concentrations, temperatures, or other When used in connection with a range of physical or chemical properties or characteristics, it is intended to cover variations that may exist at the upper and/or lower limits of the range for that property or characteristic (e.g., rounding, measurement technique or other statistical variation).

When describing elements of the disclosure or aspects thereof, articles such as “a,” “an,” “the,” and “said” may be used to refer to one or more is intended to mean many elements. Terms such as "comprising", "including", "containing" and "having" are meant to be inclusive. , meaning that there may be additional elements other than those listed. The use of terms indicating particular orientations (e.g., "top," "bottom," "side," etc.) is for convenience of description and is for the element specific. direction is not required.

Various changes may be made in the arrangements and methods described above without departing from the scope of the disclosure, and therefore all matter contained in the above description and shown in the drawings should be considered as illustrative. and are not intended to be construed in a limiting sense.

Claims (17)

A method for polishing a plurality of semiconductor substrates each having a front side and a back side substantially parallel to the front side, comprising:
contacting the front surface of the first semiconductor substrate with a polishing pad;
supplying a polishing slurry to a polishing pad to polish the front side surface of the first semiconductor substrate as a final polish to produce a polished first semiconductor substrate;
measuring the edge roll-off of the first semiconductor substrate;
contacting the front surface of the second semiconductor substrate with the polishing pad;
supplying a polishing slurry to the polishing pad to polish a front surface of the second semiconductor substrate as a final polishing ; and based at least in part on the measured edge roll-off of the first semiconductor substrate, the second semiconductor substrate. and controlling the amount of polishing slurry supplied to the polishing pad during contacting said polishing pad with said polishing pad. The first semiconductor substrate comprises a batch of semiconductor substrates, the method of polishing the semiconductor substrates comprising:
contacting the front surface of each semiconductor substrate of the batch of semiconductor substrates with a polishing pad;
supplying a polishing slurry to a polishing pad to polish the front surface of each of the plurality of semiconductor substrates in the batch to produce a batch of polished plurality of semiconductor substrates;
measuring an edge rolloff of each of the batch of polished semiconductor substrates; and based at least in part on the measured edge rolloff of the batch of polished semiconductor substrates, a second semiconductor substrate. controlling the amount of polishing slurry supplied to the polishing pad while contacting the polishing pad;
2. The method of polishing a semiconductor substrate according to claim 1, comprising: averaging the measured edge roll-off of each of the batch of polished semiconductor substrates, and contacting a second semiconductor substrate to the polishing pad based at least in part on the averaged roll-off amount of the batch; 3. The method of polishing a semiconductor substrate according to claim 2, wherein the amount of polishing slurry supplied to the polishing pad in between is controlled. To determine the pad-to-pad variability of the polishing pads, the average edge roll-off of a batch of multiple semiconductor substrates was compared to the average edge roll-off of multiple polishing pads of the same type as the polishing pad used to polish the first semiconductor substrate. 4. The method of polishing a semiconductor substrate of claim 3, further comprising comparing with roll-off. A method of polishing semiconductor substrates according to any one of claims 2 to 4, wherein a batch comprises at least 2 semiconductor substrates, or at least 5, at least 10 or at least 20 semiconductor substrates. 6. The method of claim 1, wherein the amount of polishing slurry supplied to the polishing pad between contacting the second semiconductor substrate with the polishing pad is controlled based at least in part on the lifetime of the polishing pad. A method for polishing a semiconductor substrate. 7. Any of claims 1-6, wherein the amount of polishing slurry supplied to the polishing pad while the second semiconductor substrate is in contact with the polishing pad is controlled based at least in part on the flatness of the second semiconductor substrate. A method of polishing a semiconductor substrate as described. The polishing slurry is a first polishing slurry comprising silica, the first polishing slurry being supplied to the polishing pad in a first polishing slurry volume, the method of polishing a semiconductor substrate comprising:
further comprising supplying a second polishing slurry to the polishing pad in a second polishing slurry volume;
The first polishing slurry has a relatively higher silica concentration than the second polishing slurry, and the amount of the first polishing slurry supplied to the polishing pad is such that the ratio of the first polishing slurry volume to the second polishing slurry volume is 8. The method of polishing a semiconductor substrate according to claim 1, wherein the polishing method is controlled by being controlled. 9. The method of polishing a semiconductor substrate of claim 8, wherein the second polishing slurry comprises silica. 10. The semiconductor of claim 8 or 9, wherein the ratio of the first polishing slurry volume to the second polishing slurry volume is controlled by controlling the time the first polishing slurry and the second polishing slurry are applied to the polishing pad. Substrate polishing method. 11. The method of polishing a semiconductor substrate according to claim 8, wherein the first polishing slurry and the second polishing slurry are separately supplied to the polishing pad. The amount of polishing slurry supplied to the polishing pad is the total amount of polishing slurry supplied when polishing is performed on the first table of the polishing apparatus, and the polishing method of the semiconductor substrate is the same as that of the second table of the polishing apparatus. A method of polishing a semiconductor substrate according to any one of claims 1 to 11, comprising transferring the substrate. 13. The method of polishing a semiconductor substrate according to claim 1, wherein the back side surfaces of the first semiconductor substrate and the second semiconductor substrate are not in contact with the polishing pad while the front side surfaces of the substrates are being polished. 14. The method of polishing a semiconductor substrate according to any one of claims 1 to 13, wherein the final polishing removes a material of about 0.5 µm or less from the front side surface of the substrate. 15. The method of polishing a semiconductor substrate according to claim 1, wherein the first semiconductor substrates are the first 5 substrates or the first 10 or 20 substrates to be polished by the polishing pad. 15. The method of polishing a semiconductor substrate according to claim 1, wherein the first semiconductor substrate is the first substrate to be polished by a polishing pad. The amount of polishing slurry supplied to the polishing pad between contacting the second semiconductor substrate with the polishing pad is determined by the measured edge roll-off of the first semiconductor substrate and the average edge roll of multiple polishing pads of the same type. 17. The method of polishing a semiconductor substrate according to any one of claims 1 to 16, based at least in part on a difference from off.