JP2018182160A - Evaluation method for semiconductor wafer and management method for semiconductor wafer manufacturing process - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an evaluation method for a semiconductor wafer capable of evaluating the presence/absence of over-polish into a principal surface of the semiconductor wafer which occurs in mirror plane chamfering work, and evaluating a measurement of an over-polish amount within a short time and a non-destructive manner.SOLUTION: The present invention relates to an evaluation method for a semiconductor wafer including: performing chamfering and polishing work on an edge of the semiconductor wafer sliced from a semiconductor ingot and comprising a principal surface consisting of a principal front face and a principal rear face; manufacturing the semiconductor wafer comprising the principal surface and a chamfered surface by then performing polishing work on the principal front face of the semiconductor wafer on which the chamfering and polishing work has been performed, or on both the principal front face and the principal rear face; and thereafter applying mirror plane chamfering work. The evaluation method for the semiconductor wafer is characterized in that the principal surface of the semiconductor wafer in the vicinity of the chamfered surface is irradiated with a laser beam, an inspection is performed in a dark field by detecting a scattered light from the irradiated surface, and over-polish performing the polishing work over a boundary between the chamfered surface and the principal surface during the mirror plane chamfering work is inspected.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor wafer evaluation method for evaluating the presence or absence of overpolishing on the main surface of a semiconductor wafer generated by mirror chamfering after polishing and the penetration amount of overpolishing, and a semiconductor using this semiconductor wafer evaluation method The present invention relates to a method of managing a wafer manufacturing process.

  When mirror chamfering is performed after single-sided or double-sided polishing of a semiconductor wafer, one or double-sided polished surface of the main surface of the front and back of the semiconductor wafer is re-polished (following polishing) again. Occur. Here, the main surface is composed of the main surface and the main back surface. The method of suppressing this over-polish is disclosed by patent documents 1-4. In these patent documents, surface shape measuring machines, such as edge roll-off and a flatness measuring machine, are used as a method of checking generation | occurrence | production of over polish. Patent Document 5 also discloses an over-polish suppression method, and a video microscope is used in the over-polish confirmation method.

JP, 2006-128269, A JP, 2013-258226, A JP, 2013-258227, A JP, 2015-153939, A WO 2002/005337

  However, when the surface shape measuring machine as described above is used as a method of checking the above-mentioned over-polish, there is a problem that the amount of penetration from the vicinity of the chamfered portion can not be grasped visually. In addition, video microscopes, which are visual, require workers to confirm each semiconductor wafer, which takes time and effort, and are destructive inspections because they are performed off-line separately from the manufacturing inspection line. There was a problem.

  The present invention has been made in view of the problems as described above, and its object is to evaluate the presence or absence of over-polishing in the main surface of a semiconductor wafer generated by mirror chamfering and to measure the amount of over-polish entering. It is an object of the present invention to provide a method of evaluating a semiconductor wafer capable of evaluating in a short time and nondestructively.

  In order to achieve the above object, according to the present invention, the main surface of a semiconductor wafer having a main surface sliced from a semiconductor ingot is chamfered and ground after chamfering and grinding the edge of the semiconductor wafer. The semiconductor wafer having the main surface and a chamfered surface is manufactured by polishing the front surface or both the main surface and the main back surface to produce a semiconductor wafer having a main surface and a chamfered surface, and thereafter mirror chamfered. The main surface of the semiconductor wafer is irradiated with laser light, and the scattered light from the irradiated surface is detected to inspect in a dark field, and the boundary between the chamfered surface and the main surface is inspected by the mirror chamfering process. Provided is a method of evaluating a semiconductor wafer characterized by inspecting over-polished to be polished over.

  Inside the main surface of the semiconductor wafer from the boundary between the main surface and the chamfered portion (chamfered surface) of the semiconductor wafer made by chamfering grinding processing before the polishing processing by mirror chamfering processing after single-sided or double-sided grinding processing of the semiconductor wafer Also in the present invention, the post-polished portion is described as over-polished. It is known that the thickness of the semiconductor wafer in the over-polished portion is reduced and the flatness of the semiconductor wafer is also deteriorated. The main surface near the chamfered portion (chamfered surface) of the semiconductor wafer where this over-polishing is supposed is irradiated with laser light and inspected in the dark field to measure the presence or absence of over-polishing and the amount of over-polish entering. It becomes possible in a short time and nondestructively.

  At this time, it is preferable to irradiate a laser beam to a region from the boundary between the chamfered surface and the main surface to the inner side of 2 mm toward the center of the semiconductor wafer.

  In addition, it is also preferable that the semiconductor wafer has a notch portion, and a region from the boundary between the chamfered surface and the main surface in the vicinity of the notch portion to the center side of the semiconductor wafer be irradiated with laser light.

  By designating the range to be irradiated with the laser light in the range as described above, observation and evaluation can be performed in a shorter time.

  At this time, it is preferable to set the wavelength of the laser beam to 200 nm to 700 nm.

  As described above, by limiting the wavelength of the laser light to be irradiated to the visible light region and the ultraviolet light region, it is possible to perform more excellent evaluation, that is, evaluation with which the presence or absence of overpolishing and the intruding amount of overpolishing can be measured more reliably. Become.

  The present invention also provides a method of controlling a semiconductor wafer manufacturing process, which is characterized by performing process control of mirror beveling using the result obtained by the above-described method of evaluating a semiconductor wafer.

  By acquiring the presence or absence of over-polish at the time of mirror surface chamfering and the penetration amount of over-polish, process control of the process of performing mirror surface chamfering becomes possible. Specifically, it can be used for grasping the machine difference of the mirror surface chamfering machine and changing the processing conditions of the mirror surface chamfering.

  As described above, according to the evaluation method of a semiconductor wafer of the present invention, it is possible to evaluate in a short time the presence or absence of over-polish generated by mirror chamfering and the amount of over-polish entering, and since it is nondestructive inspection There is no drop in yield. Furthermore, in the method for evaluating a semiconductor wafer of the present invention, data effective for process control of a mirror surface beveling process can also be obtained. Therefore, the semiconductor wafer manufacturing of the present invention using the results obtained by the method for evaluating a semiconductor wafer of the present invention If it is the management method of a process, process control of the process which performs mirror surface chamfering can be performed efficiently.

It is a flowchart which shows an example of the evaluation method of the semiconductor wafer of this invention. It is a dark field image of the chamfering process vicinity of the semiconductor wafer shown in a present Example. It is a bright field image of the chamfering process vicinity of the semiconductor wafer shown by a reference example. It is a dark field image of the notch part vicinity of the semiconductor wafer shown in a present Example. It is a bright field image of the notch part vicinity of the semiconductor wafer shown by a reference example. It is the ESFQR graph of the semiconductor wafer shown by a present Example. It is a dark-field image of the main surface of the chamfering process part vicinity of the semiconductor wafer shown in a present Example. It is an ESFQR graph of the semiconductor wafer of FIG. It is a schematic diagram of the detection mechanism of the edge inspection apparatus used in the present Example. It shows how the detection unit of the edge inspection apparatus used in this embodiment moves with respect to the edge portion of the semiconductor wafer to be evaluated.

  As described above, when a surface profile measuring machine is used as a method of confirming over-polish, there is a problem that the amount of penetration from the vicinity of the chamfered portion can not be grasped visually, and the video microscope which is visual is not It takes time and effort, and there is a problem that it becomes a destructive inspection because it is an off-line operation separate from the manufacturing inspection line.

  Therefore, the inventor of the present invention can evaluate the presence or absence of over-polishing in the main surface of a semiconductor wafer generated by mirror-chamfering processing and the measurement of the amount of penetration of over-polishing in a short time and nondestructively. We carefully examined the evaluation method.

  As a result, the inventor has found that the presence or absence of over-polishing and the amount of over-polish entering can be visually confirmed by using dark-field observation of the laser beam irradiated surface, and the laser light emitting portion and the dark field light receiving portion By observing the main surface of the semiconductor wafer in the vicinity of the chamfered portion (chamfered surface) of the semiconductor wafer using the inspection machine equipped with the above, online inspection becomes possible, and as a result, inspection time can be shortened and workers can It has been found that the time and effort required by the present invention can be reduced, and further that nondestructive inspection can be performed, thus completing the present invention.

  Hereinafter, the present invention will be described in detail by way of an embodiment with reference to the drawings, but the present invention is not limited thereto.

First, the method for evaluating a semiconductor wafer according to the present invention will be described with reference to FIG.
FIG. 1 is a flow chart showing an example of the semiconductor wafer evaluation method of the present invention. Here, a semiconductor wafer refers to a substrate material used to fabricate semiconductor integrated circuits (ICs) such as silicon, compound semiconductors such as GaAs, GaN, and SiC, and has a main surface including a main surface and a main back surface. There is.

In the former stage of the flow described in FIG. 1, for example, steps such as ingot preparation, slicing, chamfering, lapping, surface grinding, double-sided grinding, etching, and cleaning are appropriately performed.
A cleaning process or other inspection process may be included between the single-sided polishing or double-sided polishing process (S1) and the mirror surface chamfering process (S2) in FIG.

  Chemical mechanical polishing (CMP) processing is generally used as the single-side polishing or double-sided polishing step (S1) in FIG. In the present invention, the processing in which this CMP processing is applied to the main surface or main back surface of a semiconductor wafer is single-side polishing, and the one obtained by CMP processing both surfaces of the main surface and main back surface is referred to as double-side polishing. This CMP process may be performed according to a general method, and the details will be omitted. The semiconductor wafer subjected to the single-side polishing or the double-side polishing step (S1) has a main surface including a main surface and a main back surface, and a chamfered surface.

  In the mirror surface chamfering step (S2) in FIG. 1, the above-mentioned CMP processing is performed on a chamfered portion (chamfered surface) made by chamfering processing by grinding in the front stage of single-side polishing or double-side polishing step (S1) It is. As described above, this CMP process is performed on the chamfered portion of the semiconductor wafer, but the polishing cloth used there is thick and flexible. In addition, in the case of CMP processing on the main surface of a semiconductor wafer, it is general to apply a polishing cloth substantially parallel to that surface, but in the case of CMP processing on a chamfered portion (chamfered surface), the semiconductor wafer It is necessary to incline the polishing cloth with respect to the main surface of the It is known that not only the chamfered surface but also the main surface is polished depending on the inclination angle, the thickness of the above-mentioned polishing pad, and the flexibility of the polishing pad, and the amount of penetration of this over-polish changes.

  A cleaning process and other polishing and inspection processes may be included between the mirror surface chamfering process (S2) and the edge inspection process (S3) in FIG.

  The edge inspection step (S3) is a step of inspecting defects such as scratches, chipping, cracks and the like from the above-mentioned chamfered portion (chamfered surface) and its main surface in the vicinity thereof, for example, several mm from the tip of the semiconductor wafer. is there. Here, the foremost portion of the above-mentioned semiconductor wafer refers to the outermost peripheral portion farthest in the radial direction from the center of the circle of the main surface of the semiconductor wafer. In the inside of several mm, for example, defects such as flaws on the main surface of the semiconductor wafer or a particle inspection can not inspect the inside about 2 mm to 3 mm from the leading edge of the semiconductor wafer. The said several mm and it becomes an edge inspection object part.

  In this edge inspection, generally, inspection using a laser beam is mainly used, and as described above, defects are identified by observing light reflected by scratches, chips, cracks and the like. In the present invention, the main surface in the vicinity is in order to observe the trace of the over-polished additionally polished at the time of the mirror surface chamfering processing inside the boundary between the chamfering grinding process (chamfering surface) and the main surface of the semiconductor wafer as described above. The edge inspection process (S3) is performed until the laser beam is irradiated to the laser and the light reception by the dark field is further performed.

By mirror chamfering after single-sided or double-sided polishing of the semiconductor wafer, the inside of the main surface of the semiconductor wafer is further polished from the boundary between the main surface and the chamfered surface of the semiconductor wafer made by chamfering grinding processing prior to polishing. It is known that the thickness of the semiconductor wafer in the over-polished portion, which is the portion to be additionally polished, is reduced and the flatness of the semiconductor wafer is also deteriorated. The main surface near the chamfered surface of the semiconductor wafer where this over polishing is expected is irradiated with laser light, and inspection is performed using a dark field to measure the presence or absence of over polishing and the intruding amount of over polishing in a short time and not. It becomes possible by destruction.
Although the main surface in the vicinity of the chamfered surface described above does not specify a value, it can be a region several mm inside from the tip of the semiconductor wafer.

At this time, it is preferable to irradiate a laser beam to a region from the boundary between the chamfered surface and the main surface to the inner side of 2 mm on the center side of the semiconductor wafer. In addition, it is also preferable that the semiconductor wafer has a notch portion, and a region from the boundary between the chamfered surface and the main surface in the vicinity of the notch portion to the center side of the semiconductor wafer be irradiated with laser light. By designating the range to be irradiated with the laser light in the range as described above, observation and evaluation can be performed in a shorter time.
As described above, the laser irradiation range (that is, the inspection range) is preferably 2 mm from the boundary between the chamfered surface and the main surface of the semiconductor wafer to the center side of the semiconductor wafer. Since the width is approximately 0.2 mm to 0.4 mm, it can be said that the edge inspection range is appropriate 2 mm to 3 mm inside from the leading edge of the semiconductor wafer.

  The wavelength of this laser light is preferably 200 nm to 700 nm. As described above, by limiting the wavelength of the laser light to be irradiated to the visible light region and the ultraviolet light region, it is possible to perform more excellent evaluation, that is, evaluation with which the presence or absence of overpolishing and the intruding amount of overpolishing can be measured more reliably. Become.

  In this edge inspection step, the inspection device using a laser beam may be provided with means for automatically calculating the amount of entering the over-polish from the image of the over-polished part and recording the same, or the presence or absence of over-polish or over-exposure. Only the strength of the polish mark may be recorded. These records are useful for controlling the process of the mirror surface beveling process, for example, grasping the machine difference of the mirror surface beveling machine, and capturing the time-dependent change of each mirror surface beveling machine.

  As described above, in the method of managing a semiconductor wafer manufacturing process of the present invention, the process control of mirror beveling is performed using the result obtained by the method of evaluating a semiconductor wafer of the present invention described above. By acquiring the presence or absence of over-polishing and the amount of penetration of over-polishing during mirror chamfering processing by the semiconductor wafer evaluation method of the present invention, it is possible to control the process of the step of mirror-mirror chamfering processing. Specifically, it can be used for grasping the machine difference of the mirror surface chamfering machine and changing the processing conditions of the mirror surface chamfering.

  EXAMPLES The present invention will be more specifically described below with reference to examples, but the present invention is not limited to these.

(Example)
In this example, a semiconductor wafer obtained from a 300 mm diameter silicon single crystal ingot grown by the Czochralski method was used. Referring to the flow of FIG. 1, the semiconductor wafer used here is subjected to double-side polishing (S1) of FIG. 1 and is subjected to mirror-surface chamfering (S2) after cleaning.

  The double-side polishing (S1) used herein was DSP-20B manufactured by Fujikoshi Machine Industry Co., Ltd. The polishing removal of the semiconductor wafer was approximately 12 μm on both sides.

  The cleaning of the semiconductor wafer following the double-side polishing (S1) is a so-called SC1 cleaning in which water, ammonia and hydrogen peroxide are mixed.

  Furthermore, in mirror surface chamfering process (S2), it processed so that it might become the grinding | polishing removal margin substantially the same as double-sided grinding (S1), using IV type | mold edge polish apparatus by SpeedFam Co., Ltd. product.

  FIG. 2A is a dark field image of the main surface in the vicinity of the chamfered portion (chamfered surface) of the semiconductor wafer shown in the present embodiment. Explain how to read this image. The horizontal direction indicates 360 degrees of one circumference of this wafer as shown in the image as the entire circumference of the semiconductor wafer. Further, the vertical direction indicates the vicinity of the chamfered portion (chamfered surface) in the present invention, as described on the right side of the image at the wafer main surface side, the chamfering grinding processing area, and the wafer main surface side. As described above, it is a feature of this image that the entire circumference in the vicinity of the chamfered portion (chamfered surface) of the semiconductor wafer is extended and shown as a rectangle like this image.

The image of FIG. 2A is acquired using the edge inspection apparatus called CV350 by KLA-Tencor company.
FIG. 7 is a schematic view of a dark-field image and bright-field image detection mechanism of the edge inspection apparatus described above.
The dark field image in FIG. 2A is an image obtained by irradiating the wafer with the laser light emitted from the laser source in FIG. 7 and detecting the scattered light from the irradiated surface by the scattered light detector. The wavelength of the laser beam used here was 405 nm.

FIG. 2B is a bright field image of the main surface in the vicinity of the chamfered portion (chamfered surface) of the semiconductor wafer shown in the reference example, which is obtained by using the above-mentioned edge inspection apparatus.
The bright field image of FIG. 2B is an image obtained by irradiating the laser light emitted from the laser source in FIG. 7 onto the wafer and detecting the reflected light from the irradiated surface by the reflected light detector.
2A and 2B, the detection unit including the laser source, the scattered light detector, and the reflected light detector shown in FIG. 7 is, as shown in FIG. It is obtained by observing the wafer surface by moving in the order of → top surface.
Incidentally, the longitudinal magnifications of both the images of FIG. 2A and FIG. 2B are the same, and the lateral magnifications of both the images of FIG. 2A and FIG. 2B are the same. The reason why the bright field image of FIG. 2B is mounted is that the boundary between the chamfered grinding area (chamfered surface) and the main surface of the semiconductor wafer is unclear in the dark field image of FIG. 2A, and this boundary is clear in the bright field. Because it can be Thus, since the longitudinal magnifications are the same and the lateral magnifications are the same, the boundary between the chamfered grinding area (chamfered surface) obtained in FIG. 2B and the main surface of the semiconductor wafer is the same as in FIG. 2A. Can be shown in position.

Here, in FIG. 2A, white lines extending laterally can be seen in the regions on the main surface side and the main back surface side of the semiconductor wafer. This line is an over-polished trace that can be seen in the dark field of the present invention. Specifically, the in-plane center side of the over-polished portion additionally polished by mirror surface chamfering is manifested as a white line. Therefore, by measuring the radial length from the leading edge of the semiconductor wafer to this white line, it is possible to measure the amount of over-polishing incorporated.
In the image of FIG. 2A, it was 600 μm in the radial direction from the leading edge of the semiconductor wafer to the white line which is a trace of over-polish. Here, since the white line strikes a wave rather than a straight line in detail as in the image, the maximum amount of penetration is obtained as the amount of penetration into overpolishing.

  In the actual inspection, the bright field image in FIG. 2B is not necessary because it is not necessary to clarify the boundary between the chamfered grinding area (chamfered surface) and the main surface of the semiconductor wafer.

  FIG. 3A is a dark field image in the vicinity of the notch of the semiconductor wafer shown in the present embodiment. The image in FIG. 3A is different from that in FIG. 2A, and is taken in the vicinity of the notch portion on the main surface side of the semiconductor wafer.

  FIG. 3B is a bright field image of the vicinity of the notch of the semiconductor wafer shown in the reference example. FIG. 3A and FIG. 3B were also acquired by above-mentioned KLA-Tencor CV-350. Similar to FIG. 2B, FIG. 3B is also obtained for reference of the boundary in FIG. 3A because the boundary between the chamfered grinding area (chamfered surface) and the main surface of the semiconductor wafer is clear, but in the actual inspection, The 3B brightfield image is not required.

  The over-polished traces can be seen more clearly in the image of FIG. 3A. As described above, it is understood that the inspection of the dark field has high utility value even in the main surface near the chamfered portion (chamfered surface) of the notch portion as well as the main surface near the normal chamfered portion (chamfered surface) .

  FIG. 4 is an ESF QR graph of the semiconductor wafer shown in this embodiment. The ESFQR (Edge Site Front Surface Referenced Least sQuares Range) is a measurement of SFQR in a fan-shaped area formed in the outer peripheral area of the entire periphery of the semiconductor wafer. With SFQR (Site Front Least Squares Range), the in-site plane calculated by the least squares method in the set site is used as the reference plane, and the + side from this plane (that is, the main surface of the semiconductor wafer is (Upper side when placed horizontally), the maximum deviation on the-side (same lower side).

  The above fan-shaped size at the time of obtaining the graph of FIG. 4 was obtained by dividing the entire circumference of the wafer into 72 at intervals of 5 degrees, and the length of one side in the radial direction was 35 mm. In addition, although there are EE 0.5 mm, EE 1 mm, and EE 2 mm in the graph, this EE (Edge Exclusion) indicates an outer peripheral exclusion area at the time of ESFQR measurement. Therefore, the area of 0.5 mm to 35.5 mm in the radial direction (because one side of the above-mentioned radial direction is 35 mm) is measured with EE 0.5 mm from the tip of the semiconductor wafer. By the way, for the measuring machine of ESFQR, the WaferSight series manufactured by KLA-Tencor was used.

  The data in the graph of FIG. 4 are measured using the same semiconductor wafer used in FIGS. 2A and 2B and FIGS. 3A and 3B. In FIG. 4, it can be seen that the value of ESFQR of EE 0.5 mm is disturbed and deteriorated compared to EE 1 mm and EE 2 mm. The cause of this deterioration is due to over-polishing in mirror beveling. In the image of FIG. 2A, the overpolished has penetrated to the inside of 600 μm from the leading edge of the semiconductor wafer. Therefore, at EE 0.5 mm, the shape formed in the immediately preceding double-side polishing process was broken due to the influence of over-polish, leading to the deterioration of ESFQR. On the other hand, EE1mm and EE2mm are not affected by over-polish, and there is no deterioration in ESFQR.

  FIG. 5 is a dark field image in the vicinity of the chamfered portion (chamfered surface) of the semiconductor wafer shown in the present embodiment. Unlike the semiconductor wafer used in FIG. 2A, the semiconductor wafer of FIG. 5 is experimentally manufactured so as not to generate over-polish on the main surface side of the semiconductor wafer in the mirror chamfering step. It can be seen from the image of FIG. 5 that no trace of over-polishing as shown in FIG. 2A can be confirmed in the area described as the wafer main surface side.

  FIG. 6 is an ESF QR graph of the semiconductor wafer of FIG. Although the deterioration of ESFQR was seen at EE 0.5 mm in FIG. 4 due to the influence of over-polish which can be confirmed in the above-mentioned FIG. 2A, the semiconductor wafer having no over-polish on the main surface side as shown in FIG. It can be seen that no deterioration is seen even if

  From the above results, by performing the edge inspection by the dark field of the present invention, the presence or absence of over-polish and the amount of over-polish entering can be easily evaluated, and since nondestructive evaluation and measurement are possible, the product yield also decreases. Furthermore, it can be seen that data that can be used for process control of the mirror beveling process can also be obtained.

  As described above, in order to measure the position and the amount of penetration of the over-polish, the main surface and the edge portion of the semiconductor wafer are irradiated with the laser light for the purpose of explanation, but if only the over-polish is measured The laser beam may be irradiated to the main surface.

  The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and it has substantially the same configuration as the technical idea described in the claims of the present invention, and any one having the same function and effect can be used. It is included in the technical scope of the invention.

Claims (5)

After chamfering and grinding an edge of a semiconductor wafer having a main surface and a main back surface sliced from a semiconductor ingot, the main surface or both the front and back surfaces of the chamfered and ground semiconductor wafer is polished A method of evaluating a semiconductor wafer which is processed to produce a semiconductor wafer having the main surface and a chamfered surface, and is then subjected to mirror surface chamfering,
The main surface of the semiconductor wafer in the vicinity of the chamfered surface is irradiated with laser light, and the scattered light from the irradiated surface is detected to inspect in a dark field, and the chamfered surface and the main surface And a method of evaluating a semiconductor wafer characterized in that it inspects over-polished polished across the boundary with the above.   The method for evaluating a semiconductor wafer according to claim 1, wherein a region from the boundary between the chamfered surface and the main surface to an inner side of 2 mm on the center side of the semiconductor wafer is irradiated with laser light. The semiconductor wafer has a notch portion,
2. The semiconductor wafer according to claim 1, wherein a region from the boundary between the chamfered surface and the main surface in the vicinity of the notch portion to the center side of the semiconductor wafer is irradiated with a laser beam by 2 mm. Method.   The wavelength of the said laser beam shall be 200 nm-700 nm, The evaluation method of the semiconductor wafer as described in any one of the Claims 1-3 characterized by the above-mentioned.   A control method of a semiconductor wafer manufacturing process characterized by performing process control of the above-mentioned mirror surface chamfering processing using a result obtained by an evaluation method of a semiconductor wafer according to any one of claims 1 to 4. .