JP6493253B2 - Silicon wafer manufacturing method and silicon wafer - Google Patents

Description

  The present invention relates to a silicon wafer manufacturing method and a silicon wafer, and more particularly, to a silicon wafer manufacturing method and a silicon wafer capable of manufacturing a silicon wafer having a high flatness in a region in the vicinity of the notch with respect to a silicon wafer having a notch. .

  Conventionally, silicon wafers are widely used as substrates for semiconductor devices. In this silicon wafer, a single crystal silicon ingot grown by the Czochralski (CZchralski, CZ) method, etc. is cut into blocks, the outer periphery of the block is ground, and a notch indicating a specific direction is formed in the outer periphery. It is common to do. For example, a notch portion indicating the <110> direction, for example, is formed in a silicon wafer having a (100) crystal plane.

  The block in which the notch is formed is then subjected to wafer processing, and the resulting silicon wafer is subjected to chamfering, flattening (lapping) processing, double-side polishing processing, final polishing processing, etc., and then final cleaning. If no abnormality is confirmed through various quality inspections, the product is completed and shipped.

  In recent years, semiconductor devices have been increasingly miniaturized and highly integrated, and silicon wafers are required to have extremely high flatness. In addition, the device formation region is also expanding yearly outward in the wafer radial direction, and high flatness is required for the peripheral edge of the wafer.

  As described above, a notch portion for alignment is formed on the wafer peripheral portion. However, in the quality inspection process in the manufacturing flow described above, the notch portion and its neighboring region are excluded from the beginning and the wafer peripheral portion. It is common to measure the flatness.

  For example, when measuring the ESFQR (Edge Site Front Squares Range) of a wafer in the quality inspection process, the measurement is performed by excluding the notch portion and the vicinity thereof in the sector including the notch portion. Here, if the flatness is evaluated including the region where the notch portion exists, in some cases, the flatness measurement itself becomes impossible due to an error.

  Although a device cannot be formed in the notch portion, if the flatness of the region near the notch portion can be improved, the effective area of the device formation region (that is, the area of the region with high flatness) can be expanded.

  As a method for enlarging the device formation region, it is conceivable that the notch portion itself is not formed on the peripheral edge portion of the wafer. For example, in Patent Document 1, three or more notches are formed on the side surface of a block obtained by cutting a single crystal ingot, and a planarization process is performed on a semiconductor wafer obtained by wafer processing. After that, a technology that manufactures a semiconductor wafer without a notch at the wafer periphery by marking the wafer with a laser at a predetermined position and then chamfering the wafer periphery to remove all notches. Has been proposed.

JP 2014-232780 A

  However, the method described in Patent Document 1 cannot adopt a conventional alignment method by detecting the notch after the chamfering process for removing the notch, and is a new method for specifying the orientation of the wafer. There is a problem that requires equipment. For these reasons, there is a demand for establishment of a method capable of increasing the flatness of the region near the notch portion and expanding the device formation region for the silicon wafer having the notch portion.

  Accordingly, an object of the present invention is to provide a silicon wafer manufacturing method and a silicon wafer capable of manufacturing a silicon wafer having a high flatness in a region near the notch portion with respect to a silicon wafer having a notch portion.

  As a result of intensive studies on how to solve the above problems, the present inventor is extremely effective in setting the sum of the depth of the notch after the final polishing process and the width of the chamfered portion of the notch in the wafer radial direction to 900 μm or less. As a result, the present invention has been completed.

That is, the gist of the present invention is as follows.
(1) A notch portion is formed on the outer periphery of a single crystal silicon ingot grown by a predetermined method, and then the wafer processing is performed on the single crystal silicon ingot, and then the resulting silicon wafer is chamfered. In the method of manufacturing a silicon wafer for performing the planarization process and the polishing process, the width in the wafer radial direction of the chamfered portion in the notch portion in the stage after the final polishing process is adjusted to 350 μm to 450 μm, and the final A method for producing a silicon wafer, comprising adjusting a sum of a depth of the notch portion and a width of a chamfered portion of the notch portion in a wafer radial direction at a stage after a polishing process to 900 μm or less.

(2) The method for producing a silicon wafer according to (1), wherein a sum of a depth of the notch portion and a width of the chamfered portion in the notch portion in a wafer radial direction is adjusted to 400 μm or more and 900 μm or less.

(3) The method for manufacturing a silicon wafer according to (1) or (2), wherein a depth of the notch portion at a stage after the final polishing process is adjusted to 350 μm or more and 550 μm or less.

(4) In any one of the above (1) to (3) , the wafer radial direction cross section of the notch portion at the stage after the final polishing process is adjusted to have a symmetrical shape on the front and back of the wafer. The manufacturing method of the silicon wafer of description.

(5) In any one of (1) to (3) , the wafer radial direction cross section of the notch portion in the stage after the final polishing process is adjusted to have an asymmetric shape on the front and back of the wafer. The manufacturing method of the silicon wafer of description.

(6) In a silicon wafer having a notch at the periphery and a chamfered portion that has been chamfered with respect to the periphery , the width in the wafer radial direction of the chamfer at the notch is 350 μm or more and 450 μm or less. There, the silicon wafer sum of the wafer radial width of the chamfered portion in the depth and the notch of the notch is equal to or less than 900 .mu.m.

(7) The silicon wafer according to (6) , wherein the sum of the depth of the notch and the width in the wafer radial direction of the chamfered portion of the notch is 400 μm or more and 900 μm or less.

(8) The silicon wafer according to (6) or (7) , wherein the notch has a depth of 350 μm or more and 550 μm or less.

(9) The silicon wafer according to any one of (6) to (8) , wherein a cross section in the wafer radial direction in the notch portion has a symmetrical shape on the front and back sides of the wafer.

(10) The silicon wafer according to any one of (6) to (8) , wherein a cross section in the wafer radial direction in the notch portion has an asymmetric shape between the front and back surfaces of the wafer.

  ADVANTAGE OF THE INVENTION According to this invention, the silicon wafer with the high flatness of a notch part vicinity area | region can be manufactured about the silicon wafer which has a notch part.

It is a flowchart of an example of the manufacturing method of the silicon wafer of this invention. It is a figure explaining an example of a chamfering process. It is a schematic diagram which shows the silicon wafer by this invention.

  Embodiments of the present invention will be described below with reference to the drawings. The method for producing a silicon wafer according to the present invention includes forming a notch in the outer periphery of a single crystal silicon ingot grown by a predetermined method, and then subjecting the single crystal silicon ingot to wafer processing, and then obtaining the obtained silicon. This is a silicon wafer manufacturing method for performing chamfering, planarization and polishing on a wafer. Here, the sum of the depth of the notch portion in the stage after the final polishing process and the width of the chamfered portion of the notch portion in the wafer radial direction is adjusted to 900 μm or less.

  The present inventors diligently studied how to manufacture a silicon wafer having a high flatness in the vicinity of the notch portion with respect to the silicon wafer having the notch portion. The parameters of the peripheral edge of the silicon wafer that determine the flatness in the vicinity of the notch portion of the silicon wafer include the radius of curvature of the chamfered portion, the length of the end surface in the wafer thickness direction, the depth of the notch portion, and the chamfered portion in the wafer radial direction. Width (hereinafter referred to as “chamfer width”) and the like. The present inventors paid attention to the depth of the notch and the chamfer width of the notch among these parameters.

  The present inventors have attempted to optimize the depth of the notch and the chamfer width at the notch in order to improve the flatness of the peripheral edge of the wafer. However, simply adjusting the depth of the notch and the chamfering width at the notch is difficult to improve the flatness of the wafer peripheral edge, and the relationship between the notch depth and the chamfering width at the notch is difficult. It came to the knowledge that optimization is important.

  Specifically, the inventors have not been able to improve the flatness of the region near the notch only by reducing the depth of the notch or by simply reducing the chamfer width of the notch. Therefore, as a result of intensive studies on the relationship between the depth of the notch portion and the chamfer width at the notch portion, the present inventors have found that the sum of the depth of the notch portion and the chamfer width at the notch portion has a large flatness in the vicinity of the notch portion. I found out that it had an impact. In order to further improve the flatness of the region in the vicinity of the notch, the inventors further set the sum of the depth of the notch and the width in the wafer radial direction of the chamfer at the notch at the stage after the final polishing process to 900 μm. The inventors have found that the following adjustment is extremely effective, and have completed the present invention.

  As is apparent from the above description, the present invention is characterized in that the sum of the depth of the notch portion and the chamfer width at the notch portion after the final polishing process is adjusted to 900 μm or less. If the requirement is satisfied, other processing is not limited. Hereafter, each process is demonstrated with reference to the flowchart of an example of the manufacturing method of the silicon wafer shown in FIG.

  First, in Step S1, a single crystal silicon ingot is grown by melting polycrystalline silicon charged in a quartz crucible to about 1400 ° C. by, for example, CZ method, and then immersing the seed crystal in a liquid surface and pulling it up while rotating. To do. Here, in order to obtain a desired resistivity, for example, boron or phosphorus is doped. In addition, the oxygen concentration in the silicon ingot can be controlled by using a magnetic field applied Czochralski (MCZ) method in which a magnetic field is applied when growing an ingot.

  Next, in step S2, the obtained single crystal silicon ingot is cut into a plurality of single crystal silicon blocks using a wire saw or an inner peripheral cutting machine. This cutting process can also be performed after the notch part forming process described later.

  Subsequently, in step S3, the outer peripheral portion of the obtained block is subjected to a cylindrical grinding process to make the block diameter constant.

  Thereafter, in step S4, a notch portion indicating a predetermined direction is formed on the outer peripheral portion of the single crystal silicon block. The notch portion can be formed by pressing a grindstone having an appropriate shape on the outer peripheral surface of the block and repeating the movement of the ingot in the axial direction. At this time, the depth of the notch is formed shallower (eg, 400 μm) than in the past (eg, 1.2 mm) in consideration of the subsequent chamfering process. The direction indicated by the notch is, for example, the <110> direction or the <001> direction.

  Subsequently, in step S5, using a wire saw or an inner peripheral cutting machine, the single crystal silicon block in which the notch portion is formed is subjected to wafer processing, and sliced to a thickness of about 1 mm, for example, to obtain a silicon wafer. Get.

  Thereafter, in step S6, a primary chamfering process is performed on the peripheral edge portion of the silicon wafer obtained in step S5. This primary chamfering process can be performed by polishing using a fine grinding wheel in which grooves having a shape corresponding to the chamfered shape are formed in advance on the outer periphery by truing, a contouring process, or the like. FIG. 2 is a diagram for explaining a chamfering process using a precision grinding wheel. As shown in FIG. 2, the silicon wafer is pressed against the groove of the fine grinding wheel while the fine grinding wheel is rotated. Thereby, a wafer peripheral part can be chamfered by the chamfering shape which corresponds to the shape of the groove | channel of a fine grinding stone. As a grindstone for primary chamfering, for example, a # 600 metal bond can be used.

  Similarly, the primary chamfering process is performed on the notch portion. At that time, for example, a # 600 metal bond having a smaller diameter than the grindstone performed on the entire peripheral edge of the silicon wafer (the diameter of the portion in sliding contact with the wafer is 1 mm, for example) can be used. It can be performed by pressing against the notch while rotating and moving the grindstone along the contour of the notch.

  Subsequently, in step S7, a primary flattening process (lapping process) is performed on the main surface of the silicon wafer. In this primary planarization process, a silicon wafer is placed between a pair of parallel lapping plates, and a lapping solution made of, for example, a mixture of alumina abrasive grains, a dispersant, and water is supplied between lapping plates, with a predetermined amount. By rotating and sliding under pressure, the front and back surfaces of the silicon wafer are mechanically wrapped to increase the parallelism of the wafer.

  Next, in step S8, a secondary chamfering process is performed on the peripheral portion of the silicon wafer that has been subjected to the primary flattening process by polishing using a disc-shaped grindstone using a fine grinding wheel, a contouring process, or the like. . In this secondary chamfering process, the chamfering process is performed using, for example, a # 2000 metal chamfering grindstone that is finer than the primary chamfering process. The chamfered shape is the final target shape.

  Similarly, a secondary chamfering process is performed on the notch portion. At that time, for example, a # 2000 metal bond having a smaller diameter than the grindstone performed on the entire peripheral edge of the silicon wafer (the diameter of the portion in sliding contact with the wafer is 1 mm, for example) can be used. It can be performed by pressing against the notch while rotating and moving the grindstone along the contour of the notch.

  Subsequently, in step S9, the silicon wafer subjected to the secondary chamfering process is subjected to a surface grinding process to improve the flatness of the wafer. This surface grinding process can be performed using a surface grinding apparatus. As a grindstone for this surface grinding treatment, for example, a # 8000 vitrified grinding grindstone having a distribution center particle diameter of diamond grains of 0.7 μm can be used.

  Thereafter, in step S10, a double-side polishing process is performed on the silicon wafer subjected to the secondary chamfering process using a double-side polishing apparatus. In this double-side polishing treatment, after inserting a silicon wafer into the hole of the carrier plate, the carrier plate is sandwiched between an upper surface plate and a lower surface plate to which a polishing cloth is attached, and between the upper and lower surface plates and the wafer, for example, colloidal A slurry such as silica is poured, and the upper and lower surface plates and the carrier are rotated in opposite directions. Thereby, the unevenness | corrugation of a wafer surface can be reduced and a wafer with high flatness can be obtained.

  Subsequently, in step S11, a mirror chamfering process is performed on the peripheral edge of the silicon wafer. This mirror chamfering process can be performed using, for example, a mirror chamfering device that rotates a cylindrical urethane buff with a motor. In the mirror chamfering process, the urethane buff is rotated by a motor, and the peripheral portion of the silicon wafer is brought into contact with the outer peripheral surface of the rotating buff. Thereby, the wafer peripheral part is mirror-finished.

  Similarly, a mirror chamfering process is performed on the notch portion. At this time, the urethane buff formed in a disk shape can be pressed against the notch while rotating.

  Thereafter, in step S12, a single-side polishing process is performed on the silicon wafer subjected to the double-side polishing process using a single-side polishing apparatus. This single-side polishing treatment can be performed using a polishing cloth made of a suede material and using, for example, an alkaline polishing liquid containing colloidal silica as a polishing liquid. In the manufacture of the silicon wafer according to the flowchart of FIG. 1, the sum of the depth of the notch portion and the chamfer width at the notch portion is adjusted to 900 μm or less at the stage after the one-side polishing processing, which is the final polishing processing. To be.

  The depth of the notch portion at the stage after the one-side polishing process is determined by the depth of the notch portion at the time of forming the notch portion in step S4 and the chamfering processing in steps S6, S8 and S11. Since the amount of chamfering in the mirror chamfering process in step S11 is very small, the depth of the notch portion in the stage after the single-side polishing process is substantially determined after the secondary chamfering process in step S8. Is done.

  Further, the chamfering amount at the notch portion at the stage after the single-side polishing process is not only the chamfering process in steps S6, S8 and S11 but also the grinding or polishing process for the main surface performed in steps S7, S9, S10 and S12. Also depends on. However, since the amount of chamfering in the single-side polishing process in step S11 is very small, the chamfering width in the notch portion is substantially determined after the double-side polishing process in step S10.

  Therefore, in the flowchart shown in FIG. 1, the depth of the notch portion in the stage after the secondary chamfering process in step S <b> 8 and the chamfering width in the notch part in the stage after the double-side polishing process are adjusted. The sum is 900 μm or less. The lower limit of the sum is not particularly limited in terms of flatness in the vicinity of the notch part, but in order to maintain the function of specifying the direction of the notch part and to detect the notch part with the apparatus, it is 350 μm or more. It is preferable to do. More preferably, it is adjusted to 400 μm or more and 900 μm or less. Thereby, the flatness of the notch part vicinity area | region can be improved more.

  Moreover, it is preferable to adjust the depth of a notch part to 350 micrometers or more and 850 micrometers or less. Here, by setting the depth of the notch portion to 350 μm or more, wafer alignment can be performed reliably. Moreover, the flatness of a notch part vicinity area | region can be improved more by setting it as 850 micrometers or less.

  Furthermore, it is preferable to adjust the chamfer width at the notch portion to 50 μm or more and 450 μm or less. Here, by setting the chamfering width in the notch portion to 50 μm or more, it is possible to reliably prevent wafer cracking and chipping during wafer conveyance and handling. Moreover, the flatness of a notch part vicinity area | region can be improved more by setting it as 450 micrometers or less.

  Note that the shape of the cross section in the wafer radial direction of the chamfered portion at the stage after the final polishing process is not particularly limited for portions other than the notch portion, and can be appropriately set based on the specifications. The notch portion is not particularly limited as long as the sum of the depth of the notch portion and the chamfer width of the chamfered portion in the notch portion is 900 μm or less, and may be trapezoidal, for example. Moreover, it is good also as a symmetrical shape on the front and back of a wafer, or an asymmetrical shape.

  Finally, after the silicon wafer subjected to the single-side polishing treatment is finally cleaned, various quality inspections including the flatness of the wafer are performed in step S13. In this inspection, in addition to wafer flatness, the number of LPDs on the wafer surface, damage, contamination on the wafer surface, and the like are inspected, and only wafers that satisfy a predetermined product quality are shipped as products.

  In this way, a silicon wafer having a high flatness in the region near the notch can be manufactured for the silicon wafer having the notch.

(Silicon wafer)
Next, the silicon wafer according to the present invention will be described. FIG. 3A is a schematic top view showing a silicon wafer according to the present invention. The silicon wafer 1 shown in this figure is a silicon wafer having a notch portion 11 at the peripheral portion and a chamfered portion 12 in which the peripheral portion is chamfered. Here, the sum of the depth D of the notch portion 11 and the width (chamfer width) W of the chamfered portion 12 in the notch portion 11 in the wafer radial direction is 900 μm or less.

  The sum of the depth D of the notch 11 and the chamfer width W of the notch 11 is preferably 400 μm or more and 900 μm or less. Thereby, the flatness of the notch part vicinity area | region can be improved more.

  Moreover, it is preferable that the depth D of the notch part 11 is 350 micrometers or more and 850 micrometers or less. Here, by setting the depth D of the notch portion 11 to 350 μm or more, the wafer can be aligned with certainty. Moreover, the flatness of a notch part vicinity area | region can be improved more by setting it as 850 micrometers or less.

  Furthermore, it is preferable that the chamfering width W in the notch portion 11 is 50 μm or more and 450 μm or less. Here, by setting the chamfering width W in the notch portion to 50 μm or more, it is possible to reliably prevent wafer cracking and chipping during wafer conveyance and handling. Moreover, the flatness of a notch part vicinity area | region can be improved more by setting it as 450 micrometers or less.

  The shape of the cross section of the chamfered portion 12 in the wafer radial direction is not particularly limited with respect to portions other than the notch portion 11, and can be appropriately set based on specifications. Further, the notch portion 11 is not limited as long as the sum of the depth D of the notch portion 11 and the chamfering width W of the chamfered portion 12 in the notch portion 11 satisfies the requirement of 900 μm or less. For example, a trapezoidal shape as shown in FIG. Further, it is not necessary to have a symmetrical shape on the front and back of the wafer as shown in FIG.

  Next, in order to further clarify the effects of the present invention, the following examples are given, but the present invention is not limited to the following examples.

  A silicon wafer was manufactured according to the flowchart shown in FIG. Specifically, a single crystal silicon ingot is grown by the CZ method (step S1), the grown single crystal ingot is cut into a single crystal silicon block by a wire saw (step S2), and then cylindrical with respect to the outer periphery of the block. Grinding was performed to adjust the diameter (step S3), and a notch was formed on the outer periphery of the block (step S4). Thereafter, the single crystal silicon block was subjected to wafer processing to obtain a silicon wafer having a diameter of 300 mm and a thickness of 1 mm (step S5).

  The obtained silicon wafer was subjected to a primary chamfering process on the silicon wafer using a chamfering machine (step S6). Specifically, first, a primary chamfering process was performed on the periphery of the silicon wafer using a # 600 metal bond grindstone. Next, a # 600 metal bond grindstone having a small diameter (diameter 1 mm) was pressed against the notch portion while rotating, and the grindstone was moved along the contour of the notch portion, whereby primary chamfering was performed on the notch portion.

  Then, the silicon wafer which performed the primary chamfering process was conveyed to the lapping apparatus, and the primary planarization process was performed (step S7).

  Then, the secondary chamfering process was performed with respect to the silicon wafer which performed the primary planarization process using the chamfering apparatus used by step S6 (step S8). Specifically, first, a secondary chamfering process was performed on the peripheral portion of the silicon wafer using a # 2000 metal bond grindstone. Next, a # 2000 metal bond grindstone with a small diameter (diameter 1 mm) was pressed against the notch portion while rotating, and the grindstone was moved along the contour of the notch portion to perform secondary chamfering processing on the notch portion. . This secondary chamfering process was performed after the chamfering process so that the depth of the notch shown in Table 1 became the value shown in Table 1.

  Next, the silicon wafer subjected to the secondary chamfering process was transported to a surface grinding apparatus, and the surface of the silicon wafer was subjected to a surface grinding process to adjust the thickness to 785 μm (step S9).

Subsequently, a double-side polishing process was performed on the silicon wafer subjected to the surface grinding process (step S10). At that time, a carrier plate having a thickness of about 750 μm was used. Further, as the polishing pad, Nita Haas polishing cloth: LP57 was used, and as the polishing slurry, Nita Haas slurry: Nalco 2350 was used. In the double-side polishing treatment, the upper surface plate and the lower surface plate were rotated in opposite directions while the carrier plate was sandwiched between the upper and lower surface plates with a processing surface pressure of 300 g / cm ² by an elevator. The carrier plate was rotated at 20 to 30 rpm in the same direction as the upper surface plate by a gear mechanism, the front and back surfaces of the silicon wafer loaded in the carrier plate were polished, and the thickness was adjusted to 775 μm. The chamfer width at the notch portion after the double-side polishing treatment was adjusted to the value shown in Table 1.

  Next, a mirror chamfering process was performed on the silicon wafer subjected to the double-side polishing process using the chamfering apparatus used in step S6 (step S11). Specifically, first, a cylindrical urethane buff was rotated with respect to the peripheral portion of the silicon wafer, and the peripheral portion of the silicon wafer was brought into contact with the outer peripheral surface of the rotating buff to perform a mirror chamfering process. Next, the disk-shaped urethane buff was pressed against the notch portion while rotating it against the notch portion, and a mirror chamfering process was performed on the notch portion.

  Subsequently, the silicon wafer subjected to the mirror chamfering process was transported to a single-side polishing apparatus, and a final polishing process was performed on the main surface of the silicon wafer (step S12). This single-side polishing treatment was performed using a suede polishing cloth and an alkaline polishing liquid containing colloidal silica as the polishing liquid.

  Thereafter, the silicon wafer subjected to the finish polishing process was finally cleaned with a wafer cleaning apparatus, and the flatness in the vicinity of the notch portion was measured (step S13).

<Measurement of ESFQR>
For Invention Examples 1 to 9, Comparative Examples 1 to 9, and Conventional Example, ESFQR of the notch portion was measured. This measurement is performed using a flatness measuring apparatus (manufactured by KLA-Tencor: WaferSight 2). The measurement range is 298 mm excluding the 1 mm outer periphery of the wafer, and the outer periphery of the measurement range has a sector width of 5 ° and a sector. Each sector was divided into 72 sectors having a length of 30 mm. Further, the data of the notch portion sector was used as the value of the notch portion ESFQR without excluding the measurement of the data in the vicinity of the notch portion. The obtained results are shown in Table 1.

  The depth of the notch was measured using an edge profile monitor (manufactured by Kobelco Research Institute: LEP-2200). The chamfer width W at the notch was measured with an optical microscope. The depths of the notches and the chamfer widths at the notches were measured after the secondary chamfering process in step S9 and after the single-side polishing process in step S12. The obtained results are shown in Table 1.

  As shown in Table 1, the maximum value of ESFQR of Comparative Examples 2, 3, 5, 6, 8, and 9 was 45 nm or more, and the conventional example and Comparative Examples 1, 4, and 7 were not measurable due to measurement errors. On the other hand, the maximum value of ESFQR of Invention Examples 1 to 9 is 25 nm or less, and it can be seen that the flatness of the region near the notch is greatly improved.

  According to the present invention, it is possible to obtain a silicon wafer having a high flatness in the vicinity of the notch portion of the silicon wafer having the notch portion, which is useful for the semiconductor industry.

1 Silicon Wafer 11 Notch 12 Chamfer D D Notch Depth W Notch Chamfer Width

Claims (10)

After forming a notch in the outer periphery of a single crystal silicon ingot grown by a predetermined method, and then subjecting the single crystal silicon ingot to wafer processing, chamfering and flattening the resulting silicon wafer In the method of manufacturing a silicon wafer that performs processing and polishing processing,
The width in the wafer radial direction of the chamfered portion at the notch portion after the final polishing process is adjusted to 350 μm or more and 450 μm or less, and the depth of the notch portion and the notch portion after the final polishing process are adjusted. A method for producing a silicon wafer, comprising adjusting a sum of a chamfered portion and a width in a wafer radial direction to 900 μm or less.   The method for producing a silicon wafer according to claim 1, wherein the sum of the depth of the notch portion and the width of the chamfered portion of the notch portion in the wafer radial direction is adjusted to 400 μm or more and 900 μm or less. 3. The method for manufacturing a silicon wafer according to claim 1 , wherein a depth of the notch portion at a stage after the final polishing process is adjusted to 350 μm or more and 550 μm or less. The silicon wafer production according to any one of claims 1 to 3 , wherein the wafer radial direction cross section of the notch portion at the stage after the final polishing process is adjusted to have a symmetrical shape on the front and back sides of the wafer. Method. The silicon wafer production according to any one of claims 1 to 3 , wherein a wafer radial direction cross section of the notch portion at the stage after the final polishing process is adjusted to have an asymmetric shape on the front and back sides of the wafer. Method. In a silicon wafer having a chamfered portion that has a notch portion at the peripheral edge portion and that has been chamfered with respect to the peripheral edge portion,
The width in the wafer radial direction of the chamfered portion in the notch portion is 350 μm or more and 450 μm or less, and the sum of the depth of the notch portion and the width in the wafer radial direction of the chamfered portion in the notch portion is 900 μm or less. Silicon wafers. The silicon wafer according to claim 6 , wherein the sum of the depth of the notch and the width of the chamfered portion of the notch in the wafer radial direction is 400 μm or more and 900 μm or less. The silicon wafer according to claim 6 or 7 , wherein a depth of the notch portion is 350 µm or more and 550 µm or less. The silicon wafer according to any one of claims 6 to 8 , wherein a cross section in the wafer radial direction of the notch portion has a symmetrical shape on the front and back sides of the wafer. The silicon wafer according to any one of claims 6 to 8 , wherein a cross section in the wafer radial direction of the notch portion has an asymmetric shape on the front and back sides of the wafer.

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