JP3935977B2 - Notched semiconductor wafer - Google Patents
Notched semiconductor wafer Download PDFInfo
- Publication number
- JP3935977B2 JP3935977B2 JP14010695A JP14010695A JP3935977B2 JP 3935977 B2 JP3935977 B2 JP 3935977B2 JP 14010695 A JP14010695 A JP 14010695A JP 14010695 A JP14010695 A JP 14010695A JP 3935977 B2 JP3935977 B2 JP 3935977B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- notch
- semiconductor wafer
- chamfer
- surface side
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54493—Peripheral marks on wafers, e.g. orientation flats, notches, lot number
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- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
【0001】
【産業上の利用分野】
本発明は、ノッチ付き半導体ウェーハに関する。
【0002】
【従来の技術】
半導体素子の基板には主として高純度の単結晶シリコンが用いられているが、前記単結晶シリコンは主としてCZ法により製造される。CZ法においては、単結晶引き上げ装置のチャンバ内に設置したるつぼに多結晶シリコンを充填し、前記るつぼの周囲に設けたヒータによって多結晶シリコンを加熱溶解した上、シードチャックに取り付けた種結晶を融液に浸漬し、シードチャックおよびるつぼを互いに同方向または逆方向に回転しつつシードチャックを引き上げながら円柱状の単結晶シリコンを成長させる。
【0003】
上記CZ法などによって製造された単結晶シリコンインゴットの外周を所定寸法に研削した上、軸方向に直角に切断して薄板に分割し、ラッピング、エッチング、ポリシング等を施して少なくとも片面が鏡面に加工された単結晶シリコンウェーハ(以下ウェーハという)とする。前記単結晶シリコンインゴットの外周研削に先立って、結晶方位の判別を容易にするため外周の所定の位置にオリエンテーションフラット(以下オリフラという)またはノッチを設けている。また、たとえば両面に鏡面仕上げを施したウェーハ、そり方向指定ウェーハ(ウェーハ表面が凸面か凹面かを指定したウェーハ)、引き上げ方向指定ウェーハ等については、結晶方位判別とは別に表裏判別手段を必要とする。
【0004】
ウェーハの表裏判別を容易にするため、従来から主オリフラとは別に副オリフラを設けるか、またはレーザマーカを用いてノッチの近傍に所定のマークを入れている。主オリフラを設けることによりウェーハからデバイスを切り出す際の有効面積が減少するが、副オリフラカットにより前記有効面積は更に減少する。これに比べてウェーハの結晶方位判別手段としてノッチを設け、表裏判別手段にレーザマークを用いる方法は、ウェーハの有効面積減少の度合いが少なくて済むという利点がある。
【0005】
【発明が解決しようとする課題】
しかしながら、ウェーハの表裏判別手段にレーザマークを用いると、従来の加工工程の他にレーザマーク加工工程を付加しなければならず、コスト高となる。また、レーザマークによって印字された凹部に浮遊する塵埃等が入り込み、後工程で行われる洗浄の際に前記塵埃が発見されることがあるため、必ずしも好ましい識別手段とはいえない。更に、レーザマークを入れることにより、ノッチ加工のみのウェーハに比べて有効面積が減少するという欠点がある。
【0006】
本発明は上記従来の問題点に着目してなされたもので、オリフラやレーザマークの加工によるウェーハの有効面積減少、製造コスト上昇を最小限に抑え、かつ、レーザマークによる発塵等の品質的問題を起こさずにウェーハの表裏を容易に判別することが可能なノッチ付き半導体ウェーハを提供することを目的としている。
【0007】
【課題を解決するための手段】
上記目的を達成するため、本発明に係るノッチ付き半導体ウェーハの第1の発明では、半導体ウェーハの外周の所定位置に前記ウェーハの結晶方位を判別するノッチを設けたノッチ付き半導体ウェーハにおいて、ノッチの縁部に沿って設ける面取りの大きさをウェーハの表面側と裏面側とで異なる寸法とすることを特徴とする。また、第2の発明では、半導体ウェーハの外周の所定位置に前記ウェーハの結晶方位を判別するノッチを設けたノッチ付き半導体ウェーハにおいて、ノッチをウェーハ中心に対して左右いずれかの方向に傾けることを特徴とする。これにより、ウェーハの表裏判別を可能としている。
【0008】
【作用】
上記構成によれば、ウェーハの結晶方位判別手段であるノッチの縁部に設ける面取りを、ウェーハの表面側と裏面側とで異なる寸法としたので、面取り寸法の大小を目視で比較することによりウェーハの表裏を容易に判別することができる。また、ノッチの面取りを表裏で異なる寸法とする代わりに、ノッチ自体をウェーハ中心に対して左右いずれかに傾けた場合も、ウェーハの表裏判別は容易となる。いずれの場合も表裏判別のためのレーザマークは不要であり、ダブルオリフラカットに比べてウェーハ有効面積の損失が小さくなる。
【0009】
【実施例】
以下に、本発明に係るノッチ付き半導体ウェーハの実施例について、図面を参照して説明する。図1は、本発明の第1実施例に基づくウェーハのノッチ部分を拡大した模式的平面図で、ウェーハの表面を示す。図2は同じくウェーハのノッチ部分を拡大した模式的平面図で、ウェーハの裏面を示す。図3は図1のA−A断面図である。これらの図において、1は表裏両面に鏡面仕上げを施した円盤状のウェーハで、外周の所定の位置にV字状のノッチ2が設けられ、前記ウェーハ1の外周とこれに続くノッチ2の縁部にはなめらかな面取り3および4が施されている。ノッチ2の形状は、角度θ=90°、深さa=1mmである。また、ノッチ2の縁部に沿って設ける面取りの大きさは、表面側の面取り3がウェーハ1の外周の面取りと同じくC1 =100μmで、裏面側の面取り4のみC2 =600μmとなっている。前記面取り寸法C1 およびC2 は一例を示すものであり、これらの値に限定されるものではない。
【0010】
本実施例では、ノッチの縁部に沿って設ける面取りの大きさがウェーハの表面側と裏面側とで明らかに異なるため、ウェーハの表裏判別は目視により容易に行うことができる。また、ウェーハ外周の面取りは従来と同じく表裏同一寸法であるため、ウェーハの有効面積減少や強度の低下は起こらない。
【0011】
図4は、本発明の第2実施例に基づくウェーハのノッチ部分を拡大した模式的平面図で、ウェーハの表面を示す。ウェーハ1の外周には所定の位置にV字状のノッチ2が設けられているが、このノッチ2はウェーハ1の中心に対して右側に傾いている。すなわち、ウェーハ中心線5に対するノッチ2の左側の開き角θ1 と右側の開き角θ2 との関係は、θ1 ≪θ2 となっている。このように、ノッチ2に傾きを与えることにより、ウェーハの表裏を容易に目視判別することができる。なお、面取り3の大きさはウェーハ外周、ノッチ縁部を問わず、かつ、表裏ともすべて同じ寸法である。
【0012】
【発明の効果】
以上説明したように本発明によれば、なんらかの表裏判別手段を必要とするウェーハに対し、結晶方位判別手段として設けたノッチの縁部面取りをウェーハの表面側と裏面側とで異なる寸法としたので、前記面取り形状を目視比較するだけでウェーハの表裏を容易に判別することができる。また、前記ノッチをウェーハ中心に対して左右いずれかに傾けた場合も、ウェーハの表裏判別は容易である。本発明による表裏判別手段はレーザマーク加工を必要としないので、その分だけ製造コストが低減するとともに、レーザマークによる発塵という品質問題を回避することができる。更に、従来から行われているダブルオリフラカットに比べてウェーハ有効面積の損失が小さくなるので、デバイス取得率が向上する。
【図面の簡単な説明】
【図1】本発明の第1実施例に基づくウェーハのノッチ部分を拡大した模式的平面図で、ウェーハの表面を示す。
【図2】図1のウェーハの裏面を示す。
【図3】図1のA−A断面図である。
【図4】本発明の第2実施例に基づくウェーハのノッチ部分を拡大した模式的平面図で、ウェーハの表面を示す。
【符号の説明】
1 ウェーハ
2 ノッチ
3,4 面取り
5 ウェーハ中心線[0001]
[Industrial application fields]
The present invention relates to a notched semiconductor wafer.
[0002]
[Prior art]
High purity single crystal silicon is mainly used for the substrate of the semiconductor element, and the single crystal silicon is mainly manufactured by the CZ method. In the CZ method, the crucible installed in the chamber of the single crystal pulling apparatus is filled with polycrystalline silicon, the polycrystalline silicon is heated and melted with a heater provided around the crucible, and the seed crystal attached to the seed chuck is then added. It is immersed in a melt, and cylindrical single crystal silicon is grown while pulling up the seed chuck while rotating the seed chuck and the crucible in the same direction or in the opposite direction.
[0003]
After grinding the outer circumference of the single crystal silicon ingot manufactured by the CZ method etc. to a predetermined dimension, cut it at right angles to the axial direction, divide it into thin plates, and perform lapping, etching, polishing, etc. to process at least one side into a mirror surface A single crystal silicon wafer (hereinafter referred to as a wafer) is obtained. Prior to the peripheral grinding of the single crystal silicon ingot, an orientation flat (hereinafter referred to as an orientation flat) or a notch is provided at a predetermined position on the outer periphery in order to easily determine the crystal orientation. In addition, for example, wafers with mirror finish on both sides, warp direction designation wafers (wafers whose wafer surface is convex or concave), pulling direction designation wafers require front / back discrimination means separately from crystal orientation discrimination To do.
[0004]
Conventionally, a sub-orientation flat is provided separately from the main orientation flat or a predetermined mark is put in the vicinity of the notch using a laser marker in order to facilitate front / back discrimination of the wafer. By providing the main orientation flat, the effective area when a device is cut out from the wafer is reduced, but the effective area is further reduced by the secondary orientation flat cut. Compared with this, the method of providing a notch as the crystal orientation discriminating means of the wafer and using the laser mark as the front and back discriminating means has an advantage that the degree of reduction of the effective area of the wafer is small.
[0005]
[Problems to be solved by the invention]
However, if a laser mark is used as the wafer front / back discrimination means, a laser mark processing step must be added in addition to the conventional processing step, resulting in an increase in cost. Further, since dust or the like floating in the concave portion printed by the laser mark may enter and be found during cleaning performed in a later process, it is not necessarily a preferable identification means. In addition, the insertion of the laser mark has a drawback that the effective area is reduced as compared with a wafer notched only.
[0006]
The present invention has been made by paying attention to the above-mentioned conventional problems, minimizing the effective area of the wafer due to orientation flat and laser mark processing, minimizing the increase in manufacturing cost, and quality such as dust generation by the laser mark. An object of the present invention is to provide a notched semiconductor wafer capable of easily discriminating the front and back of a wafer without causing a problem.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, in a first invention of a notched semiconductor wafer according to the present invention, in a notched semiconductor wafer in which a notch for determining the crystal orientation of the wafer is provided at a predetermined position on the outer periphery of the semiconductor wafer, The size of the chamfering provided along the edge portion is different from that on the front surface side and the back surface side of the wafer. In the second invention, in the semiconductor wafer with a notch provided with a notch for discriminating the crystal orientation of the wafer at a predetermined position on the outer periphery of the semiconductor wafer, the notch is tilted in either the left or right direction with respect to the wafer center. Features. Thereby, the front and back of the wafer can be distinguished.
[0008]
[Action]
According to the above configuration, since the chamfering provided at the edge of the notch, which is the crystal orientation determination means of the wafer, has different dimensions on the front surface side and the back surface side of the wafer, the wafer size can be visually compared by comparing the chamfer dimensions. Can be easily distinguished. Further, when the notch is chamfered to the left or right with respect to the center of the wafer instead of making the chamfer of the notch different in size, it is easy to distinguish the front and back of the wafer. In either case, the laser mark for front / back discrimination is not required, and the loss of the effective area of the wafer is smaller than that of the double orientation flat cut.
[0009]
【Example】
Embodiments of a notched semiconductor wafer according to the present invention will be described below with reference to the drawings. FIG. 1 is a schematic plan view in which a notch portion of a wafer according to the first embodiment of the present invention is enlarged, and shows the surface of the wafer. FIG. 2 is an enlarged schematic plan view of the notch portion of the wafer, showing the back surface of the wafer. 3 is a cross-sectional view taken along the line AA in FIG. In these figures, reference numeral 1 denotes a disk-shaped wafer having a mirror-finished surface on both sides, and a V-
[0010]
In the present embodiment, since the chamfer size provided along the edge of the notch is clearly different between the front surface side and the back surface side of the wafer, the front / back discrimination of the wafer can be easily performed visually. Further, since the chamfering of the outer periphery of the wafer is the same size as the conventional one, the effective area of the wafer and the strength do not decrease.
[0011]
FIG. 4 is a schematic plan view in which the notch portion of the wafer according to the second embodiment of the present invention is enlarged, and shows the surface of the wafer. A V-
[0012]
【The invention's effect】
As described above, according to the present invention, the chamfered edge of the notch provided as the crystal orientation discriminating means for the wafer that requires some kind of front / back discriminating means is set to have different dimensions on the front side and the back side of the wafer. The front and back of the wafer can be easily discriminated simply by visually comparing the chamfered shapes. Further, even when the notch is tilted to the left or right with respect to the wafer center, the front / back discrimination of the wafer is easy. Since the front / back discriminating means according to the present invention does not require laser mark processing, the manufacturing cost is reduced correspondingly, and the quality problem of dust generation by the laser mark can be avoided. Furthermore, since the loss of the effective area of the wafer is reduced as compared with the conventional double orientation flat cut, the device acquisition rate is improved.
[Brief description of the drawings]
FIG. 1 is an enlarged schematic plan view of a notch portion of a wafer according to a first embodiment of the present invention, showing the surface of the wafer.
2 shows the back side of the wafer of FIG.
3 is a cross-sectional view taken along the line AA in FIG.
FIG. 4 is a schematic plan view in which a notch portion of a wafer according to a second embodiment of the present invention is enlarged, showing the surface of the wafer.
[Explanation of symbols]
1
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14010695A JP3935977B2 (en) | 1995-05-16 | 1995-05-16 | Notched semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14010695A JP3935977B2 (en) | 1995-05-16 | 1995-05-16 | Notched semiconductor wafer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH08316112A JPH08316112A (en) | 1996-11-29 |
JP3935977B2 true JP3935977B2 (en) | 2007-06-27 |
Family
ID=15261082
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14010695A Expired - Fee Related JP3935977B2 (en) | 1995-05-16 | 1995-05-16 | Notched semiconductor wafer |
Country Status (1)
Country | Link |
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JP (1) | JP3935977B2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4109371B2 (en) * | 1999-01-28 | 2008-07-02 | Sumco Techxiv株式会社 | Semiconductor wafer |
JP2002222746A (en) * | 2001-01-23 | 2002-08-09 | Matsushita Electric Ind Co Ltd | Nitride semiconductor wafer and its manufacturing method |
JP3580311B1 (en) * | 2003-03-28 | 2004-10-20 | 住友電気工業株式会社 | Rectangular nitride semiconductor substrate with front and back identification |
KR20070042594A (en) * | 2005-10-19 | 2007-04-24 | 삼성코닝 주식회사 | Single crystalline a-plane nitride semiconductor wafer having orientation flat |
TWI417431B (en) * | 2008-09-29 | 2013-12-01 | Sumco Corp | Silicon wafer and its manufacturing method |
JP5548173B2 (en) * | 2011-08-31 | 2014-07-16 | 株式会社東芝 | Semiconductor substrate and manufacturing method thereof |
JP2015018960A (en) | 2013-07-11 | 2015-01-29 | 三菱電機株式会社 | Semiconductor device manufacturing method |
KR102468793B1 (en) * | 2016-01-08 | 2022-11-18 | 삼성전자주식회사 | Semiconductor wafer, semiconductor structure and method of manufacturing the same |
JP6493253B2 (en) * | 2016-03-04 | 2019-04-03 | 株式会社Sumco | Silicon wafer manufacturing method and silicon wafer |
-
1995
- 1995-05-16 JP JP14010695A patent/JP3935977B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JPH08316112A (en) | 1996-11-29 |
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