JPH03177023A - Preparation of epitaxial wafer - Google Patents

Abstract

PURPOSE: To prevent an epitaxial crown from being generated by polishing the angle of the front and rear surfaces of a wafer outer-periphery edge part with a specific tool and making the length of the front surface inclined part to be longer than a rear-surface inclined part in the sectional shape of a wafer edge, where an inclined part is formed. CONSTITUTION: A wafer 10 is shaped by a tool 60, so that it has a front surface inclined part 50 with a length 52, a rear surface inclined part 54 with a length 56, and a nose part 58, and the length 52 of the front surface inclined part 50 is reduced, as compared with the length 56 of the rear surface inclined part 54. A groove 62 of the tool 60 consists of a side wall 70 with a length 72 and a sidewall 74 and a bottom part 78 with a length 76. A width 80 of the groove 62 is at least equal to a thickness 22 of the wafer, and a surface 82 is shorter than an adjacent surface 70 by a length 84. Then, the wafer 10 for which a corner has been polished by the tool 60 prior to epitaxial deposition does not cause an epitaxial crown, and has a uniform epitaxial layer 88 on a front surface 12, and a round epitaxial region 90 is formed at the inclined part 50 and the nose part 58, thus improving the yield of a device and an IC.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to means and methods for processing semiconductor wafers, and more particularly to the processing of semiconductor wafers prior to coating with an epitaxial layer.

BACKGROUND OF THE INVENTION In the field of electronics technology, it is common to polish the edges of semiconductor and other electronic substrate wafers to remove sharp corners where the major surface of the wafer meets the edge or side surface of the wafer. It will be held on. This is done to reduce the possibility of chipping or other damage to the wafer during subsequent processing, and is well known in abutment techniques.

Particular problems arise with wafers coated with epitaxial layers. The flow of reactive gases within the epitaxial reactor is different at the edge of the wafer than at the main surface of the wafer. As a result of these flow perturbations, a ridge or crown of epitaxial material is created at or near the edge of the wafer.
The "ridge" or "shrimp crown" is thicker than the rest of the epitaxial layer and protrudes from the epitaxial material on the major side of the wafer.

This ridge or crown of epitaxial material is an undesirable impediment to rough wafer processing.

In the prior art, various methods have been attempted to avoid this shrimp crown.

One is to improve the design of the epitaxial reactor,
There are ways to reduce the edge perturbation of the gas flow. However, this method has been only partially successful, and such reactors are more expensive and less flexible than conventional equipment. Therefore, other solutions are desired.

It is known that the size of the shrimp crown can be reduced by edge polishing of the wafer.

The sharper the angle at which the main surface of the wafer contacts the edge or side surface of the wafer, the more conspicuous the shrimp crown will appear. However, conventional edge polishing methods are time consuming and expensive, and cannot completely eliminate the shrimp/crown effect.

Therefore, there remains a need for improved means and methods for preparing wafers prior to the deposition of epitaxial layers thereon to reduce or eliminate shrimp crown formation during epitaxial layer growth. exist.

It is an object of the present invention to provide an improved means and method for preparing a wafer prior to epitaxial deposition of a layer on the wafer to reduce or eliminate the formation of shrimp crown during epitaxial layer growth. It is to provide.

Another object of the present invention is to provide an improved means and method for trimming the edges of a wafer prior to epitaxial growth to reduce or eliminate shrimp crown.

Still another object of the present invention is to provide an improved edge polishing apparatus and wafer preparation method for carrying out the above.

SUMMARY OF THE INVENTION The above and other objects and advantages include the step of providing a semiconductor wafer having a front surface and a back surface connected by an edge that joins the front surface and the back surface at a front angle and a back surface angle, respectively; asymmetrically removing material from the corner at a time; the step of removing removes material from the front corner for a first distance measured from the edge of the wafer along the first side; and removing material from the backside angle to a second distance measured from the edge of the wafer along the backside, the first distance being less than the second distance. Once the wafer is trimmed as described above, an epitaxial layer is formed on the first surface, with the shrimp material extending uniformly over the front face and front corners with substantially no ridges or crowns.

Preferably, the amount of material removed from the corner of the wafer is greatest near the corner and decreases to zero at the first and second distances, and the back corner is polished until it is substantially conical. approximately 36 mm to the wafer surface.
It is desirable to form any angle between 44 and 44. It is also desirable that the surface formed by polishing the front corners also be conical. However, the surface formed by corner polishing may also be curved, ie spheroidal, so that it intersects the front and back planes of the wafer gradually, rather than abruptly.

The polishing step described above includes first and second spaced apart polishing surfaces that asymmetrically polish the front and back corners and the front and back portions of the wafer near the corners, respectively; Conveniently, this is carried out with a single asymmetric polishing tool consisting of a groove with a second side connected and a third side forming the bottom of the groove. At this time, the second side is
It is longer from the bottom of the groove than from the surface. To create a conical corner surface, it is desirable that the side faces of the groove have a bevel angle of 36 to 44 degrees, and to create a spheroidal corner surface, the bevel angle should be set toward the opening of the groove. It is desirable that it taper down to 0 degrees. It is desirable that the bottom of the groove is a polished surface and curved, and that the first and second surfaces of the groove and the bottom are joined without having an acute angle. These and other objects, advantages and features of the present invention will be more fully understood from the accompanying drawings and the following description.

Examples: As used herein, the term "front surface" refers to the formation of an epitaxial layer suitable for a device or other intended purpose, where it is desirable to avoid or minimize the formation of shrimp crowns or ridges. Refers to the main side of the wafer.

Also, the term "back side" refers to that opposite side of the wafer.

Referring to FIGS. 18-1D, wafer portion 1
0 consists of a wafer front surface 12 and a wafer back surface 14 joined by an edge 16 at a front corner 18 and a back corner 20, respectively. Wafer 10 is usually 0
．． It has a thickness 22 of 5 to 0.8 mm (~20 to 3 QmilS) and a diameter of about 75 to 200 mm (~3 to 8 inches), although larger or smaller wafers may be used.

The wafer 10 is a semiconductor wafer (e.g. silicon, germanium, etc.) on which epitaxial growth will occur.
III-V, II-V, etc.) or other materials. Sapphire is a commonly used dielectric substrate as a base for epitaxial growth, but is not limited thereto. Other materials are also well known in the art. The term "semiconductor" or "semiconductor wafer", as used herein to refer to a starting wafer or substrate, is intended to include any material shaped by any method used as a substrate for epitaxial growth, with intermediate electrical conductivity. It's not limited to the materials you have.

FIG. 1A shows the starting wafer before edge shaping and epitaxial growth. Corner 18.20 is often an acute angle. As wafers are grabbed many times during processing and moved in and out of many baskets and boats, there is a great risk of edge chipping and other edge damage if the edges remain sharp.

These defects can be substantially reduced by rounding the wafer edges.

For example, U.S. Pat. No. 4,227, issued to Tamm
．． No. 347 describes an edge polishing apparatus and polishing tool for rounding the edges of semiconductor wafers. The wafer is held in a chuck and rotated in contact with a grooved polishing tool. This FIG. 1B shows the relationship between the polishing tool and the wafer edge shape as described by Tamm.

In FIG. 1B, wafer 10 has edge 16 polished into a hemispherical shape 24 by a cylindrical groove of polishing tool 28. In FIG.

In FIG. 1C, the wafer 10 is placed in a polishing mold or polishing plate 30.
In FIG. 1D, the wafer 10 is roughly polished by a polishing cloth to form a conical front surface 32. In FIG.
Further polishing is performed to form a rear corner circular prong surface 36.

Figures 2A-2C show how the shrimp crowns 40, 42, 44 form when the epitaxial decoy 48 is applied to the front side 12 of the wafer in the wafer edge form according to the conventional technique of Figures 1B-2C. 5 shows whether the front surface 32 and/or the edges 24 are formed on the front surface 32 and/or the edges 24. Epitaxial layer 48 typically has an average thickness of 20 to 200 micrometers, particularly 70 to 100 micrometers, over most of the wafer. However, thicker or thinner layers can also be used. The thicker the shrimp layer, the greater the chance of forming a pronounced shrimp crown.

Shrimp crowns are desirably absent, as they interfere with masking, imaging, and other critical operations that are typically subsequently desired to be performed on the front epitaxial layer 48. Corner 18 is shown in FIGS. 1B, 1C and/or
Or even when rounded as in FIG. 1D, a ridge or crown 40° 44.44 is observed to be formed on the wafer front surface 12 at or near the original corner 18.

Even with conventional shaping methods and tools, a significant amount of epitaxial material is formed at the wafer edge 16 and ridges 40, 42, 44. Generally speaking, conventional shaping methods include, for example, rounding the edges with tool 28 and/or then polishing first conical surface 32 with first tool 30 and polishing second conical surface 36 with second tool 34. , expensive, time consuming and undesirable. Additionally, controlling the precise shape and degree of wafer edge shaping is often difficult and inconsistent with traditional multi-tool methods.

These and other problems and limitations are overcome by the tools and methods of the present invention as illustrated in the first embodiment shown in FIGS. 3A and 3B. The results after epitaxial growth are shown in FIGS. 48 to 4B. Referring now to Figures 38 to 3B, it can be seen that originally
A wafer having the shape shown in the figure] O has a front slope 50 of length 52 adjacent corner 18 and front surface 12;
and a rear sloped portion 54 having a length 56 adjacent to the rear surface 14, and a curved nose portion 58 at the remaining edge 16 portion. A single tool 60 cuts the edge 16 in one motion.
Shape portions 50, 54, and 58 within. Front inclined part 50
The length 52 of should be shorter than the length 56 of the rear ramp 54.

When shaping brittle and/or hard materials, such as many semiconductor substrates, the cutting groove 6 of the tool 60
It is desirable that No. 2 has abrasive properties.

Diamond and silicon carbide are examples of solid abrasive materials that may be embedded within the grooves 62 of the tool 60, provided separately as a polishing slurry, or a combination thereof. Details of such polishing materials and procedures are well known in the art.

Groove 62 of tool 60 includes a first sidewall 70 of length 72 forming front ramp 50 . Length 7 forming rear inclined portion 54
6 forming a second side wall 74 and a nose portion 58
It consists of 8. Desirably, the bottom portion 78 is curved. The side walls 70.74 are preferably conical or planar, so that the resulting portions 50.54 are also conical. For example, if the tool 60 is a rotatable disc with a groove 62 extending around its circumference, the side walls 70, 74 will be conical. The tool 60 is stationary without rotation, and the wafer edge 16 is in the groove 62.
When rotated inward, the sides 170° 74 become flat. Either method is fine, but a rotary tool is preferred. The side walls 70° 74 of the groove 62 are preferably conical, but one or both are spherical and the angle 86 is approximately 1
From an initial value of less than 80 degrees, conveniently less than about 150 degrees, the sidewalls 70.74 may taper toward zero as they approach the opening on the exterior of the groove 62. good.

It is important that the width 80 of the groove 62 is greater than or equal to the wafer thickness 22 and that the wafer-facing surface 82 of the tool 60 is removed from the adjacent surface 70 by a quantity 84;
The side surface 70 is therefore shorter than the slope 54 (when measured radially across the wafer surface), creating a slope 50 that is not as deep. Thus, less material is removed from corner 18 when forming ramp 50 than from corner 20 when forming ramp 54. Quantity 84
is approximately 0.25 to 1.3 mm (~10 to 5 Qm
ilS) in the range of about 0.5 to 1
0. It is convenient if it is mm (20 to 4Qmils),
Usually about 0.9 mm (~35 Illits).

Side faces 70.74 have an included angle 86 of 30 to 60 degrees, conveniently this angle is about 32 to 52 degrees, and preferably about 36 to 44 degrees. The inclined portions 50, 54 form an angle of approximately half the size. For example, using a polishing tool 60 having an angle 86 of about 36 to 44 degrees, the surface 52.54 has an angle of about 18 to 22 degrees relative to the normally substantially parallel plane of the wafer surface 12.14. provided.

Referring now to FIG. 4A, wafers that have had their corners polished using tool 60 prior to performing epitaxial deposition on front surface 12 have little or no shrimp crown and are substantially uniform on front surface 12. It has a shrimp layer 88,
The ramp 50 and the nose 58 have a round, non-protruding shrimp region 90 oriented perpendicular to the surface 12 and extending from the outermost surface 89 of the shrimp layer 88 of the surface 12 . This is highly desirable and very practical since it eliminates a source of yield loss that is likely to occur during subsequent wafer processing during device and IC formation. Portion 92 of shrimp layer 88 may extend to back slope 54, but this has no adverse effect.

It can be seen that the presence and size of the posterior bevel 54 relative to the anterior bevel 50 is important in eliminating shrimp crown formation. If ramps 50.degree. 54 are substantially the same size, or if ramp 50 is larger than ramp 54, shrimp crown formation is likely to occur. However, the slope 50 (and the corresponding amount of material removed from corner 18.20)
is smaller than ramp 54, shrimp crown formation is minimized or avoided. this is,
This is an unexpected result.

FIG. 4B shows the results after shrimp growth according to another embodiment of the present invention. Here, the rear sloped portion 54 is maintained, but the front sloped portion 50 has a spheroidal shape, that is, the sloped portion 50 has a spheroidal curve extending from the nose portion 58. The nose portion 58 intersects the upper surface 12 without forming any particular angle. Such a shape may be obtained, for example, by making the side surface 70 curved extending from a curved bottom portion 78. In this example, the side surface 7
0 has an initial bevel angle of 86, so 180
Away from the sub-degree bottom 58, the bevel angle 86 tapers to a smaller value at the opening of the groove 62.

If either or both of the surfaces 50,54 are desired to be spheroidal, the half-opening angle for the spheroidal surfaces tapers to a small (final) value at the opening of the groove 62. . that is, usually less than 30 degrees, and preferably less than about 22 degrees, and about 1 to 10 degrees.
degree provides the smoothest transition. Although the final half-angle may be zero, it is desirable that the half-angle be greater than zero and/or that the width 80 be greater than the wafer thickness 22.

This prevents the outer edge of the groove 62 from polishing the ridge or notch that the wafer edge 16 abuts, even if there is a misalignment between the groove 62 and the wafer 10. The greater the final angle and width 80, the greater the tolerance for misalignment.

However, if the misalignment is too large, it becomes difficult to control the relative amount of material removed to form surface 50.54. The term "spheroidal" as used herein refers to other curvilinear shapes, and is not limited to ellipsoids or paraboloids.

Surface 82 must be ground down such that distance 72 is less than distance 76. It also results in more material being removed from corner 20 than from corner 18.

As seen in FIG. 4B, the shrimp layer 8B has a portion 100 that extends around the slope portion 50 and the nose portion 58, and a portion 102 that extends between the slope portion 54 on the rear surface, and is essentially a shrimp layer. The crown has not been made.

The method of the present invention includes the steps of providing the wafer 10 and the tool 60 with several alternative embodiments that result in the shapes of the grooves 62 described herein, creating relative motion between the edges 16 and the grooves 62; cutting or polishing the edges 16 and corners 18, 20 in a single operation to a shape corresponding to the shape of the groove 62, and forming an epitaxial layer 88 on the front side 12 of the wafer 10. As will be understood by those skilled in the art, it is desirable to perform intermediate cleaning operations to remove cutting debris, polishing debris, and other contaminants that may adversely affect the properties of the finished wafer. Means and methods for carrying out the individual steps mentioned above are well known in the art.

The tool 60 is preferably disk-shaped with grooves 62 on the edge and rotates against the wafer edge 16;
Preferably, wafer 10 is also rotated. It is desirable to subject the cut surface to Il, II during the polishing operation. Materials and equipment for performing such steps are known.

Referring to FIG. 5, in the preferred embodiment, the tool 60 consists of two identical grooves 62, 62' located in mirror images on opposite sides of the central plane 104 of the circle 1105.

These grooves are located equidistant 106, 106' from the opposite surface 108, 108' of the disc and are carved into the surface 825.
82'. For example, if the polishing surface in the groove 62 is worn to the replacement position, the disk 105 can be removed from the spindle, turned over, and reinstalled to restart polishing. There is no need to re-prepare the rank of ゛. This is very convenient in manufacturing. Although the grooves 62, 62' in the wheel 105 are shown with conical sides for ease of illustration, one or both sides of the groove may have a spheroidal shape as described above. But that's fine. The side surfaces of the spheroid are arranged in mirror symmetry with respect to the central plane 104.

Having thus described the invention, those skilled in the art will appreciate the information provided herein and believe that the invented apparatus has been modified to provide an edge polishing tool and an epitaxial bottom to the target wafer or major surface. It will be appreciated that this provides improved wafer processing for receiving wafers. Shrimp crown is minimized or avoided, and edge polishing is much easier and faster. This is because the desired wafer edge shape is obtained in a single operation and using a single shaping tool. Manufacturing convenience is provided by providing a polishing tool with two mirror-symmetrically arranged grooves. These are important practical benefits that improve quality and lower costs.

Although the invention has been described with respect to specific materials and methods of implementation,
Those skilled in the art will appreciate, based on the above discussion, that other materials and modifications may be used and the method may be applied to other wafers and other environments where edge polishing is important. Dew. Accordingly, the claims are intended to include modifications that occur to those skilled in the art based on this explanation.

[Brief explanation of drawings]

18-1D are schematic side views of wafer edge shaping steps and tools according to various prior art techniques. Figures 28-2C are schematic side views of wafers shaped by the tool of Figures 1B-1D after epitaxial growth has been performed thereon. Figures 38-3B are schematic side views of a wafer and mating wafer edge shaping tool, respectively, in accordance with a preferred embodiment of the present invention. Figures 48-4B are schematic side views of wafers with edges shaped by edge polishing tools according to some embodiments of the present invention after epitaxial growth has been performed. and FIG. 5 is a partial, schematic side view of a rough development of the polishing tool of the invention. [Explanation of main symbols] 10, Wafer, 12, Front, 14, Rear, 16, Edge, 50, Front inclined part, 54, Rear inclined part, 58,... Nose part, 0 2 70° 8 8 9 0 4 Tool, cutting groove 1 0. sidewall, bottom, epitaxial layer, surface, epitaxial region.

Claims (3)

[Claims] (1) A method of processing a semiconductor wafer, comprising: providing a semiconductor wafer having first and second major surfaces connected by a bonding surface at first and second corners, respectively; and a single operation. asymmetrically removing material from the first and second corners at the wafer, the removing step including removing material from the first corner for a first distance measured from a side of the wafer along the first surface; ,
removing from a corner relative to a second distance measured from a side of the wafer along a second surface;
A method of processing a semiconductor wafer, comprising: removing material at a distance smaller than the distance. (2) A method of processing a semiconductor wafer using edge polishing, comprising: a semiconductor wafer having substantially flat first and second surfaces and a side surface extending intermediate therebetween; providing a semiconductor wafer bonded to a surface by a first corner and bonded to a second surface by a second corner; and polishing both the first and second corners in one operation. providing a third substantially conical surface extending laterally from the untreated portion of the second side, the third surface extending laterally from the untreated portion of the second side; and about 3
a fourth surface intersecting at an included angle of less than 0 degrees and extending laterally from the untreated portion of the first surface and having a radial width less than the radial width of the third surface; The fourth surface is about 30 degrees from the plane of the untreated portion of the second surface.
The first and second portions intersect at a bevel angle of less than
A method for processing a semiconductor wafer using edge polishing, the method comprising: polishing a corner; (3) An apparatus for processing a semiconductor wafer, wherein: between the first and second main surfaces of the semiconductor wafer and the connecting edge of the semiconductor wafer,
Edge polishing means for simultaneously tapering corners, said edge polishing means comprising first and second spaced apart polishing sides polishing first and second corners; a groove having a third side surface that connects and forms the bottom of the groove, the second side surface extending longer from the bottom of the groove than the first side surface, the polishing means comprising; Semiconductor wafer processing equipment.