JP2873285B1 - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JP2873285B1 JP2873285B1 JP3797898A JP3797898A JP2873285B1 JP 2873285 B1 JP2873285 B1 JP 2873285B1 JP 3797898 A JP3797898 A JP 3797898A JP 3797898 A JP3797898 A JP 3797898A JP 2873285 B1 JP2873285 B1 JP 2873285B1
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- semiconductor wafer
- outer peripheral
- peripheral portion
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
【要約】
【課題】 半導体ウエハーの表裏面の判別を容易ならし
めると共にエピタキシャル成長膜の形状や純度を向上、
安定化させる。
【解決手段】 両面鏡面研磨仕上げした半導体ウエハ
ー、特に矩形のウエハーであって、ウエハーの裏面のみ
の外周部の一部または全部に面取り加工を施し、該ウエ
ハーの表面には面取り加工部を設けないようにした半導
体ウエハー。Abstract: PROBLEM TO BE SOLVED: To facilitate discrimination of front and back surfaces of a semiconductor wafer and to improve the shape and purity of an epitaxially grown film.
Stabilize. SOLUTION: A semiconductor wafer which has been mirror-polished on both sides, particularly a rectangular wafer, is subjected to chamfering on a part or all of an outer peripheral portion of only a back surface of the wafer, and a chamfered portion is not provided on a surface of the wafer. Semiconductor wafer.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電子工業用、特に液
相エピタキシャル成長用半導体ウエハーに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer for use in the electronics industry, particularly for liquid phase epitaxial growth.
【０００２】[0002]
【従来の技術】電子工業に用いられる半導体ウエハーの
うち、特にエピタキシャル成長用半導体ウエハーは矩形
のものが一般的である。これには鏡面仕上を表裏両面に
施したものと、表面のみに施したものの２通りがある。
このうち後者、すなわち表面のみに鏡面仕上を施したも
のは、粗面である裏面に塵埃等が付着し易く、また破壊
強度が低いという欠点がある。したがって、このような
欠点を嫌う場合には前者、すなわち鏡面仕上を表裏両面
に施した半導体ウエハーが使用される。また、赤外線検
出器用ＣｄＴｅまたはＣｄＺｎＴｅのようにウエハー裏
面より赤外線を導入し、表面側に形成された検出部に導
くようなデバイス構造には、必然的に表裏両面に鏡面仕
上を施した半導体ウエハーが使用される。2. Description of the Related Art Among semiconductor wafers used in the electronics industry, in particular, semiconductor wafers for epitaxial growth are generally rectangular. There are two types of mirror finishes: mirror finish on both sides and mirror finish.
Among them, the latter, that is, the mirror-finished surface only, has the drawbacks that dust and the like easily adhere to the rough rear surface and that the breaking strength is low. Therefore, when such disadvantages are disliked, the former, that is, a semiconductor wafer having a mirror-finished surface on both the front and back surfaces is used. Also, for a device structure such as CdTe or CdZnTe for an infrared detector that introduces infrared rays from the back surface of the wafer and guides it to a detection unit formed on the front surface side, a semiconductor wafer having mirror-finished surfaces on both front and back sides is inevitable. used.
【０００３】一般に半導体ウエハーは強度的に脆い材料
が多く、しばしば加工工程中に機械的衝撃を受け、チッ
ピングや割れが発生するというトラブルを起こすことが
ある。このための対策として単結晶インゴットからウエ
ハーを切り出した後、外周部をテーパー状にあるいは曲
線状に削るといった面取りを施してから研磨加工を進め
ていくのが一般的である。この面取り部は研磨加工が進
み厚さが薄くなっていくに従ってその部分が研磨されて
小さくなっていくが、最終研磨後も幅０．３〜１．０ｍ
ｍ程度残ることが多い。[0003] In general, semiconductor wafers are often made of a material that is brittle in terms of strength, and are often subjected to a mechanical shock during a processing step, which may cause troubles such as chipping and cracking. As a countermeasure for this, it is common to cut a wafer from a single-crystal ingot, then perform chamfering such that the outer peripheral portion is tapered or curved, and then proceed with polishing. This chamfered portion is polished and becomes smaller as the polishing process proceeds and the thickness becomes thinner, but the width is 0.3 to 1.0 m even after the final polishing.
m often remain.
【０００４】ところが、上記のような従来の半導体ウエ
ハーには次のような問題があった。まず、両面が鏡面で
あると肉眼でウエハーの表裏を判別するのは困難であ
り、しばしば取り扱いに間違えるという問題を生じた。
円形のウエハーの場合には、その外周にオリエンテーシ
ョンフラットと称する直線部を複数個設け、その相互の
位置関係により表裏の判別を可能ならしめていたが、矩
形ウエハーの場合はそのような対処ができない。また、
面取り部は種々の面方位よりなる結晶面の集合なので、
この半導体ウエハーにエピタキシャル成長した場合、成
長速度の高い面方位の方向に選択的にエピ膜が成長し、
エピタキシャル成長後のウエハーエッジ部は特定方向に
盛り上がったいわゆるクラウン状になってしまい、その
後のデバイス作成工程に悪影響を与える。However, the conventional semiconductor wafer as described above has the following problems. First, when both surfaces are mirror surfaces, it is difficult to distinguish the front and back of the wafer with the naked eye, and there has been a problem that handling is often mistaken.
In the case of a circular wafer, a plurality of linear portions called orientation flats are provided on the outer periphery thereof, and it is possible to discriminate between the front and back sides by their mutual positional relationship. However, such a measure cannot be taken in the case of a rectangular wafer. Also,
Since the chamfer is a set of crystal planes with various plane orientations,
When epitaxial growth is performed on this semiconductor wafer, an epitaxial film is selectively grown in a direction of a plane orientation having a high growth rate,
The wafer edge portion after the epitaxial growth becomes a so-called crown shape which rises in a specific direction, which adversely affects the subsequent device fabrication process.
【０００５】さらに、加工工程において面取りされたウ
エハーエッジ部は、その後工程である研磨（ラッピング
およびポリシング）では上記のように十分除去されてい
ないことが多い。このため、研磨後のエッジ部には不純
物などの汚染物質が残存し易くなる。ウエハー表面およ
びこれに連接する表側エッジ部は液相エピタキシャル成
長時に、先ず液相によりメルトバックされてから成長を
開始するが、上記のようにエッジ部に残存する汚染物質
はメルトバック時に液相中に溶け出して汚染原因とな
る。このため、ウエハー表面にその後成長するエピタキ
シャル層も汚染されてしまうという問題があった。Further, the wafer edge portion chamfered in the processing step is often not sufficiently removed by polishing (lapping and polishing), which is a subsequent step, as described above. Therefore, contaminants such as impurities are likely to remain at the polished edge. During liquid phase epitaxial growth, the wafer surface and the front side edge portion connected to the wafer are first melted back by the liquid phase and then start growing, but as described above, the contaminants remaining at the edge portion are in the liquid phase during the melt back. Melts out, causing contamination. For this reason, there has been a problem that the epitaxial layer that is subsequently grown on the wafer surface is also contaminated.
【０００６】[0006]
【発明が解決しようとする課題】本発明は、表裏両面を
鏡面にした矩形の半導体ウエハーの場合でも肉眼でウエ
ハーの表裏を容易に判別できるようにし、またウエハー
の表面の面取り部における特定方向に盛り上がるクラウ
ン状のエピタキシャル成長膜の成長を防止し、さらに表
側エッジ部の汚染物質に起因するエピタキシャル成長層
の汚染を効果的に防止することを課題とする。SUMMARY OF THE INVENTION The present invention makes it possible to easily discriminate the front and back of the wafer with the naked eye even in the case of a rectangular semiconductor wafer having both front and rear surfaces mirrored, and to provide a specific direction in a chamfered portion on the front surface of the wafer. An object of the present invention is to prevent the growth of a crown-shaped epitaxially grown film that rises, and to effectively prevent the contamination of the epitaxially grown layer due to the contaminants on the front edge portion.
【０００７】[0007]
【課題を解決するための手段】以上の問題点に対し、本
発明は以下のようにして解決を図った。 １．両面鏡面仕上げした半導体ウエハーであって、該ウ
エハーの裏面のみの外周部の一部または全部に面取り部
を備えていることを特徴とする半導体ウエハー ２．液相エピタキシャル成長用矩形ウエハーであること
を特徴とする上記１記載の半導体ウエハー ３．矩形のＣｄＴｅまたはＣｄxＺｎ1-xＴｅ（ｘ＜１）
ウエハーであることを特徴とする上記１記載の半導体ウ
エハーIn order to solve the above problems, the present invention has solved the following problems. 1. 1. A semiconductor wafer which has been mirror-polished on both sides and has a chamfered portion on a part or all of an outer peripheral portion of only the back surface of the wafer. 2. The semiconductor wafer as described in 1 above, which is a rectangular wafer for liquid phase epitaxial growth. Rectangular CdTe or Cd x Zn 1-x Te (x <1)
2. The semiconductor wafer according to the above 1, wherein the semiconductor wafer is a wafer
【０００８】[0008]
【発明の実施の形態】本発明においては、鏡面仕上げし
た面のうち裏面のみの外周部の一部または全部に面取り
部を設ける、すなわち最終研磨仕上げ後の状態でウエハ
ーエッジ部の面取りはウエハーの裏面のみに施し、エピ
タキシャル成長する表面には面取り部が無い状態とす
る。これによって、ウエハーは外周部の面取りの有無に
より、その表裏を容易に判別できるので、取り扱い時に
表裏を誤ることがなくなる。なお、このような面取り部
は、必ずしもウエハー外周部の全部である必要はなく外
周部の一部であってもよい。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a chamfered portion is provided on a part or all of an outer peripheral portion of only a back surface of a mirror-finished surface, that is, a chamfer of a wafer edge portion after final polishing is performed. It is applied only to the back surface, and there is no chamfered portion on the surface for epitaxial growth. Thereby, the front and back of the wafer can be easily distinguished by the presence or absence of chamfering of the outer peripheral portion, so that the front and back are not mistaken during handling. Note that such a chamfered portion does not necessarily need to be the entire outer peripheral portion of the wafer, and may be a part of the outer peripheral portion.
【０００９】また、本発明においてはエピタキシャル成
長するウエハーの表面側に面取り部が無いので、上記に
述べたようなエピタキシャル成長時の外周部の特定方向
への異常成長やメルトバック時の汚染が無いという特徴
を有している。なお、従来の面取り加工の目的の一つで
あったウエハー加工時のチッピングや割れ等のウエハー
破損の低減効果については、ウエハー表面側に面取り部
を設けなければ無くなるわけであるが、これには次のよ
うな解決手段がある。すなわち、ウエハー表面側の面取
り深さを、後の研磨加工で除去される量と同程度にして
おくことにより解決できる。このようにすると研磨等の
操作中には面取り部が存在しているので、チッピング等
のウエハー破損が防止できる。そして最終仕上げ時点で
は該ウエハー表面側に面取り部が存在していないので、
上記にのべた本発明の機能を全てもつことができる。Further, in the present invention, since there is no chamfer on the surface side of the wafer to be epitaxially grown, there is no abnormal growth of the outer peripheral portion in a specific direction during the epitaxial growth and no contamination at the time of meltback as described above. have. The effect of reducing wafer damage such as chipping and cracking during wafer processing, which was one of the purposes of conventional chamfering, would be eliminated unless a chamfered portion was provided on the wafer surface side. There are the following solutions. That is, the problem can be solved by setting the chamfering depth on the wafer surface side to be substantially equal to the amount removed in the subsequent polishing. In this way, since the chamfered portion exists during the operation such as polishing, the damage of the wafer such as chipping can be prevented. And at the time of the final finish, there is no chamfer on the wafer surface side,
It can have all the functions of the present invention described above.
【００１０】[0010]
【実施例および比較例】本発明の実施例および比較例を
以下に示す。ＶＧＦ法により育成したＣｄ0.97Ｚｎ0.03
Ｔｅ単結晶より厚さ１０００μｍ、面方位（１１１）の
３０ｘ５０ｍｍ2 ウエハー１０枚を切り出し、外周部を
面取り加工した。これらのウエハー１０枚の面取り深さ
は裏面側は全て２００μｍとし、そして表面側はウエハ
ー５枚について１００μｍ（本発明の実施例）に、他の
ウエハー５枚については２００μｍ（比較例）とした。
この後、ウエハーの両面をラッピングおよび次いでポリ
シング加工し、表面および裏面共に１００μｍ（合計で
２００μｍ）を鏡面研磨仕上げした。これにより、最終
仕上げ後本発明の実施例ウエハーの５枚の表面側外周部
には面取り部がなくなり、裏面側外周部のみに１００μ
ｍの面取り部が存在する。これに対し、比較例であるウ
エハーの５枚については表面側および裏面側の外周部の
双方に面取り部がそれぞれ１００μｍ存在する。Examples and Comparative Examples Examples and comparative examples of the present invention are shown below. Cd 0.97 Zn 0.03 grown by VGF method
Ten 30 × 50 mm 2 wafers having a thickness of 1000 μm and a plane orientation (111) were cut out from a Te single crystal, and the outer peripheral portion was chamfered. The chamfering depth of the ten wafers was 200 μm on the back side, 100 μm on the front side of five wafers (Example of the present invention), and 200 μm on the other five wafers (Comparative Example).
Thereafter, both sides of the wafer were lapped and then polished, and both the front and back surfaces were mirror-polished to 100 μm (200 μm in total). As a result, after the final finishing, the chamfered portions are eliminated from the outer peripheral portions of the five front side wafers of the example wafer of the present invention, and
There are m chamfers. On the other hand, with respect to the five wafers of the comparative example, the chamfered portions exist on both the outer peripheral portions on the front surface side and the rear surface side, respectively, at 100 μm.
【００１１】次に、上記実施例ウエハーの５枚および比
較例ウエハーの５枚について、表面に厚さ２μｍのＨｇ
ＣｄＴｅを液相エピタキシャル成長させた後、ｖａｎ
ｄｅｒ Ｐａｗｖ法によりキャリア濃度を評価した。こ
の結果を表１に示す。Next, with respect to the five wafers of the above-described example and the five wafers of the comparative example, the surface of Hg having a thickness of 2 μm was formed.
After liquid phase epitaxial growth of CdTe, van
The carrier concentration was evaluated by the der Pawv method. Table 1 shows the results.
【００１２】[0012]
【表１】 [Table 1]
【００１３】表１に示すように、ウエハーの表面側外周
部に面取り部がない本発明の実施例は、表面側外周部に
面取り部が１００μｍ存在する比較例ウエハーに比べキ
ャリア濃度が平均的に低く、ばらつきも小さい。これは
不純物が少ないエピタキシャル膜が安定して得られてい
ることを示している。また、エピタキシャル成長膜も比
較例のウエハーでは外周部が隆起したクラウン状となっ
ていたのに対し、本発明の実施例では厚さの一様な良好
なエピタキシャル成長膜が得られた。さらに本発明の実
施例では表面研磨加工の最終段階まで表面側外周部に面
取り部が存在していたので、比較例と同様にチッピング
や割れ等のウエハー破損がなかった。なお、ウエハーの
裏面側の面取り部については特に問題となることはな
く、本発明の目的のためには、ウエハーの裏面側の面取
り部は外周部全面でもまたはその一部のいずれでもよ
い。As shown in Table 1, the carrier concentration of the embodiment of the present invention in which the chamfered portion is not present on the outer peripheral portion on the front side of the wafer is more average than that of the comparative wafer having the chamfered portion on the outer peripheral portion of the front surface of 100 μm. Low and small variation. This indicates that an epitaxial film with few impurities is stably obtained. Also, the epitaxial growth film had a crown shape in which the outer peripheral portion was raised in the wafer of the comparative example, while the epitaxial growth film having a uniform thickness and a good thickness was obtained in the example of the present invention. Further, in the example of the present invention, the chamfered portion was present on the outer peripheral portion on the front surface side until the final stage of the surface polishing, so that the wafer was not damaged such as chipping or cracking as in the comparative example. The chamfered portion on the back side of the wafer is not particularly problematic, and for the purpose of the present invention, the chamfered portion on the back side of the wafer may be the entire outer peripheral portion or a part thereof.
【００１４】[0014]
【発明の効果】以上のように、本発明は両面鏡面仕上げ
半導体ウエハー、特に矩形ウエハーの外周部の面取りを
裏面のみに施すことによって、表裏面の判別を容易なら
しめると共に成長後のエピタキシャル膜の形状や純度を
向上させ、安定化させる優れた効果を有する。As described above, according to the present invention, the outer peripheral surface of a double-sided mirror-finished semiconductor wafer, in particular, a rectangular wafer, is chamfered only to the rear surface, thereby facilitating the discrimination between the front and rear surfaces and the growth of the epitaxial film after growth. It has an excellent effect of improving and stabilizing the shape and purity.
Claims (3)
って、該ウエハーの裏面のみの外周部の一部または全部
に面取り部を備えていることを特徴とする半導体ウエハ
ー。1. A semiconductor wafer having a double-sided mirror-finished surface, wherein a chamfered portion is provided on a part or all of an outer peripheral portion of only the back surface of the wafer.
であることを特徴とする請求項１記載の半導体ウエハ
ー。2. The semiconductor wafer according to claim 1, which is a rectangular wafer for liquid phase epitaxial growth.
（ｘ＜１）ウエハーであることを特徴とする請求項１記
載の半導体ウエハー。3. A rectangular CdTe or Cd x Zn 1-x Te
2. The semiconductor wafer according to claim 1, wherein (x <1) a wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3797898A JP2873285B1 (en) | 1998-02-05 | 1998-02-05 | Semiconductor wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3797898A JP2873285B1 (en) | 1998-02-05 | 1998-02-05 | Semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2873285B1 true JP2873285B1 (en) | 1999-03-24 |
| JPH11224836A JPH11224836A (en) | 1999-08-17 |
Family
ID=12512668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3797898A Expired - Lifetime JP2873285B1 (en) | 1998-02-05 | 1998-02-05 | Semiconductor wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2873285B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116034186A (en) * | 2020-09-17 | 2023-04-28 | 日本碍子株式会社 | Group III nitride semiconductor substrate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4846915B2 (en) * | 2000-03-29 | 2011-12-28 | 信越半導体株式会社 | Manufacturing method of bonded wafer |
-
1998
- 1998-02-05 JP JP3797898A patent/JP2873285B1/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116034186A (en) * | 2020-09-17 | 2023-04-28 | 日本碍子株式会社 | Group III nitride semiconductor substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11224836A (en) | 1999-08-17 |
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