JP3491523B2 - Processing method of semiconductor wafer - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor wafer,
In particular, the present invention relates to an improvement in a method for etching and removing a work-affected layer on the surface of a wafer that occurs in the manufacturing process of a single crystal silicon wafer.

[0002]

2. Description of the Related Art Conventionally, a process for producing a semiconductor mirror-finished wafer usually comprises a step of slicing a single crystal rod of silicon or the like and subjecting the obtained semiconductor wafer to at least chamfering, lapping, acid etching, mirror-polishing and washing. ing. Depending on the purpose, some of these steps may be replaced, repeated a plurality of times, or other steps such as heat treatment and grinding may be added or replaced to perform various steps. Here, among the above, acid etching is performed for the purpose of removing the surface-altered layer introduced during mechanical processing such as slicing, chamfering, and lapping,
For example, it is a step of etching the surface from several to several tens of μm with a mixed acid aqueous solution containing hydrofluoric acid, nitric acid, acetic acid, and water, but the following problems have been pointed out.

That is, 1) TTV after wrapping
[Total Thickness Variation] (μm), LTVmax
The flatness of the wafer, which shows the variation in thickness expressed by [Local Thickness Variation] (μm) and the like, is deteriorated as the etching margin increases. 2) Irregularities called mm undulations and peels occur on the etching surface. 3) Etching produces harmful NOx. Therefore, alkali etching may be used in consideration of these problems.

The advantages and disadvantages of this alkaline etching are listed as follows. First, a) flatness after lapping is maintained after etching, b) generation of harmful gas is suppressed, and the like. A) The surface after etching has a depth of several μm locally.
Since there are pits with a size of several to ten and several μm, if foreign matter enters the pits, it may cause particles or contamination in the subsequent process. (B) There are deep pits or surface roughness. Since (Ra) becomes large, mirror polishing in the subsequent process (mechanochemical polishing)
It is necessary to increase the polishing allowance in C. Since the unevenness of the surface after etching has a sharper shape than that of acid etching, the unevenness itself is a source of particles.

Therefore, the etching process removes the mechanically processed strained layer and improves the surface roughness while maintaining the flatness after lapping, and in particular, makes the local deep pits shallower after the etching, and further If the concavo-convex shape can be made smooth, it is possible to reduce the generation of particles in the subsequent process and the polishing allowance in the mirror polishing process.

[0006]

Therefore, the present invention has been made in view of the above problems, and the mechanically processed strained layer is removed and the surface roughness is maintained while maintaining the flatness of the wafer after lapping. In particular, a semiconductor wafer processing method for producing a chemically-etched wafer (CW) having an etching surface in which local deep pits are shallower, smooth unevenness is formed, and particles and contamination are unlikely to occur is improved. The main purpose is to provide.

[0007]

In order to solve the above-mentioned problems, the invention described in claim 1 of the present invention is a semiconductor wafer obtained by slicing a single crystal ingot, at least chamfering, lapping, etching, mirror polishing and In the method for processing a semiconductor wafer comprising a cleaning step, the etching step is a reaction rate-controlled acid etching, and then a diffusion rate-controlled acid etching is performed. It is a method for processing a semiconductor wafer, which is characterized in that it is larger than an etching allowance of acid etching.

As described above, in the etching step, the wafer after lapping is first subjected to reaction rate-controlled acid etching to remove the mechanically processed strained layer while maintaining the flatness after lapping, and then to the diffusion rate-controlled type. By performing the acid etching, it is possible to improve the local deep pits remaining after the reaction rate-controlled acid etching, the surface roughness, and the sharp uneven shape.

At this time, it is necessary to make the etching allowance of the reaction-controlled acid etching larger than the etching allowance of the diffusion-controlled acid etching. The main reason for this is the local deepness remaining after the reaction-controlled acid etching. In order to reduce the depth of the pit, it is necessary to take a large reaction rate-controlled acid etching allowance, and the value is the rate of diffusion-controlled acid etching that causes defects such as stains due to etching unevenness called stains. It is larger than the etching allowance required to reduce the flatness.

Further, as described in claim 2, the etching allowance is 10 in reaction-controlled acid etching.
˜30 μm, 5-2 in diffusion-controlled acid etching
It is preferably 0 μm. In the reaction rate-controlled acid etching, the depth of local deep pits remaining after etching tends to become shallower as the etching allowance increases, and on the contrary, the surface roughness tends to deteriorate, but the above range is an appropriate value. . In the diffusion-controlled acid etching, the flatness is deteriorated as the etching margin is increased, but the stain generation rate is greatly reduced, so the above range is appropriate.

According to a third aspect of the present invention, the reaction-controlled acid etching solution and the diffusion-controlled acid etching solution are solutions in which silicon is dissolved in a mixed acid aqueous solution containing hydrofluoric acid, nitric acid, acetic acid, and water. In addition, the reaction-controlled acid etching solution had a higher silicon concentration than the diffusion-controlled acid etching solution. By using such an etching solution, the etching treatment effect can be reliably exhibited in both the reaction rate-controlled acid etching and the diffusion-controlled acid etching, and the etching allowance can be controlled relatively easily, and the cost is low. It should be noted that the specific numerical values of the etching allowances in the present invention are all total values obtained by adding the etching allowances of both surfaces of the wafer.

In this case, as described in claim 4, the reaction-controlled acid etching solution has a silicon concentration of 20 to 20.
30 g / L, and the silicon concentration of the diffusion-controlled acid etching solution is preferably 5 to 15 g / L. If the silicon concentration of the reaction-controlled acid etching solution is less than 20 g / L, it becomes a diffusion-controlled acid, so that the flatness is deteriorated, and if it exceeds 30 g / L, the etching rate is lowered and the silicon for dissolving the solution is dissolved. It will take a long time, so 20
It is preferable to adjust to a range of -30 g / L. When such a reaction-controlled acid etching solution is used, the etching treatment effect is reliably exhibited, and the control of the etching allowance can be performed relatively easily and at low cost. In addition, it is preferable to dissolve a small amount of silicon even in a diffusion-controlled acid in order to prevent a change in etching rate due to a change in liquid composition. If the amount of silicon dissolved is less than 5 g / L, the etching rate changes greatly due to changes in the liquid composition.
When it exceeds g / L, the etching rate decreases, the surface state of the wafer after etching becomes close to that of a reaction-controlled acid, and the roughness increases, so 5 to 15 g / L is preferable.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings, but the present invention is not limited thereto. Here, FIG. 1, FIG. 2, FIG. 3 and FIG.
Is an etching allowance for a wafer that has been subjected to reaction rate-controlled acid etching after lapping an 8-inch wafer, and a local deep pit depth (Fig. 1), TTV (Fig. 2), surface roughness [R
a] (FIG. 3) and LTVmax (FIG. 4). FIGS. 5 and 6 show the relationship between the etching allowance due to general diffusion rate-controlled acid etching and the ratio of defects such as stains caused by etching unevenness called TTV (FIG. 5) and stain (FIG. 6). ing.

The inventors of the present invention have variously studied a semiconductor wafer processing method, particularly an etching method, for maintaining the flatness of the wafer after lapping and producing a chemical etching wafer having an etching surface in which particles and contamination are unlikely to occur. As a result, first, reaction rate-controlled acid etching is performed to remove the strained layer while maintaining flatness after lapping, and diffusion-controlled acid etching is performed to improve the deep pits and surface roughness left there. Based on this idea, the processing conditions were investigated and the present invention was completed.

First, the reaction-controlled acid etching will be described in detail. As an etching solution for this reaction-controlled acid etching, a mixed acid aqueous solution, for example, [HF (50 vol.%):
HNO ₃ (70 vol.%): CH ₃ COOH (99 vol.
%) = 1: 2: 1], and a solution having 20 to 30 g of silicon dissolved in 1 L of the mixed acid aqueous solution is used. The etching solution was found during research on the etching function of the above-mentioned mixed acid aqueous solution, and has a function substantially similar to that of ordinary alkali etching. The etching solution is a reaction rate-controlling acid, since the reaction rate of a mixed acid aqueous solution which is a normal acid etching solution is a diffusion rate-controlling acid, whereas the reaction rate-controlling acid is dominant. This mixed acid aqueous solution is called a diffusion-controlled acid.

The advantages and disadvantages of the reaction rate-controlling acid etching function are listed as follows. First, a) the flatness after lapping is maintained after etching. B) Alkaline etching is usually performed at around 80 ° C. Etching with the reaction-controlled acid can be performed at about room temperature, and the problem is a) that the surface after etching has a depth of several μm locally.
Since there are pits with a size of several to ten and several μm, if foreign matter enters the pits, it may cause particles or contamination in the subsequent process. (B) There are deep pits or surface roughness. Since (Ra) becomes large, mirror polishing in the subsequent process (mechanochemical polishing)
It is necessary to increase the polishing allowance in C. Since the surface irregularities after etching have a sharper shape than in diffusion-controlled acid (normal mixed acid) etching, the irregularities themselves are the source of particle generation. And so on.

When the liquid temperature during etching is lower than 20 ° C., the etching rate decreases, and when it exceeds 45 ° C., the diffusion rate control becomes dominant and the flatness deteriorates, so that the etching temperature is 20 to 45 ° C. Is preferred.
Also, the amount of silicon dissolved in the mixed acid aqueous solution is 20 g / L.
If it is less than 30%, it becomes a diffusion-controlled type and the flatness deteriorates.
If it exceeds, the etching rate will decrease and it will take a long time to dissolve the silicon for producing the liquid.
It is preferable to adjust it in the range of 0 to 30 g / L.

In FIG. 1, after lapping an 8-inch wafer with lapping abrasive grains of # 1200, mixed acid [HF (50 (50
vol.%): HNO ₃ (70 vol.%): CH ₃ COOH
(99 vol.%) = 1: 2: 1], silicon 26 g /
4 shows the relationship between the etching allowance of a wafer etched by a reaction-controlled acid etchant dissolved in L and the depth of a local deep pit. In addition, FIG.
3 shows the relationship with the surface roughness (Ra) in FIG. 3, and FIG. 4 shows the relationship with LTVmax.

Here, the local deep pit is a pit formed by lap abrasive grains sticking to the wafer surface at the time of lapping, the size and depth of which are increased by reaction rate-controlled acid etching. is there. When the concentration of silicon is low, the pit depth tends to increase, while when the concentration of silicon is high, the pit depth can be made shallower, but this requires a large etching allowance. ,ineffective. The depth of this pit is determined by the depth of focus of the optical microscope, but in order to remove this pit, it is necessary to polish it in a mirror polishing step which is a post-step. Therefore, the amount of mirror polishing needs to be equal to or greater than the maximum value of such a deep pit depth, and therefore it is desirable to make the pits as shallow as possible.

TTV [Total Thickness Variation]
(Μm) is a numerical value indicating the difference in thickness between the thickest part and the thinnest part in one wafer, and is an index of the flatness of the wafer. In addition, LTV [Local Thickness Variatio
n] (μm) is a wafer of one wafer (usually 20 ×
20 mm or 25 x 25 mm), and the LTV of each cell is LTVcbc, the maximum value in one wafer, which is the numerical value of the difference in thickness between the thickest part and the thinnest part in the cell. It is called LTVmax and is an index of wafer flatness. Ra (μm) is called center line average roughness and is one of the most commonly used surface roughness parameters.

From FIG. 1, in order to make the depth of the local deep pit shallow, an etching allowance of 10 μm or more is required by the reaction rate-controlled acid etching, and TTV (FIG. 2) is 1 μm.
m or less, Ra (Fig. 3) 0.30 µm or less, LTVmax
In order to reduce (FIG. 4) to 0.50 μm or less, the etching allowance should be 30 μm or less. Therefore, as a sum of these, the etching allowance for the reaction-controlled acid etching is:
A suitable range is 10 to 30 μm. Especially, the depth of the local deep pit is close to the minimum value (about 10 μm),
About 20 μm is a condition that V and Ra do not deteriorate so much.
Is preferred.

Next, the etching allowance of diffusion-controlled acid etching was examined. Even in a diffusion-controlled acid, it is preferable to dissolve a small amount of silicon in order to prevent a change in etching rate due to a change in liquid composition. If the amount of silicon dissolved is less than 5 g / L, the change in etching rate due to a change in liquid composition is large, and if it exceeds 15 g / L, the etching rate decreases, and the surface state of the wafer after etching becomes a reaction-controlled acid. Since it is close to the surface and the roughness is large, it is preferably 5 to 15 g / L. In FIG. 5, after lapping an 8-inch wafer with # 1200 lap abrasive grains,
Mixed acid in which 10 g / L of silicon was dissolved [50% hydrofluoric acid: 7
0% nitric acid: 99% acetic acid = 1: 2: 1 (volume ratio)] was etched as a diffusion-controlled acid, and the relationship between the average value of the etching allowance and the value of TTV after etching is shown. FIG. 6 shows the etching allowance of a chemical etching wafer by general diffusion-controlled acid etching and the ratio of defects such as stains caused by uneven etching called stain. The presence or absence of stain was visually determined under light collection.

From FIG. 6, it is necessary that the diffusion-controlled acid etching allowance is at least 5 μm or more to avoid the stain, and the etching allowance of 10 μm or more is required to surely eliminate the stain. On the other hand, from FIG. 5, an etching allowance of 20 μm or less is appropriate in order to reduce TTV to 1 μm or less. Therefore, as a total amount of these, as an etching allowance of the diffusion-controlled acid etching, 5 to 20 μm is an appropriate range, and particularly preferably about 10 μm.

As described above, the relationship between the etching allowance and the etching effect of the reaction-controlled acid etching and the diffusion-controlled acid etching has been clarified separately. And diffusion-controlled acid etching are used together, but the reaction-controlled acid etching is preceded, and then the diffusion-controlled acid etching is performed. I was able to demonstrate it.

That is, in the case of the reaction rate-controlled acid etching + diffusion rate-controlled acid etching, first, the mechanical processing strain layer is removed by the reaction rate-controlled acid etching while maintaining the flatness after lapping, and then the diffusion rate-controlled acid etching. By performing the mold acid etching, it is possible to make the local deep pits remaining after the reaction rate-controlled acid etching and the sharp asperities on the surface into a smooth shape, improve the surface roughness, and suppress the stain occurrence rate. At that time, it is necessary to make the etching allowance of the reaction-controlled acid etching larger than the etching allowance of the diffusion-controlled acid etching. The main reason for this is the depth of the local deep pits remaining after the reaction-controlled acid etching. In order to reduce the depth, it is necessary to take a large amount of reaction-controlled acid etching, and this value is larger than the etching amount required to reduce the stain generation rate and flatness in diffusion-controlled acid etching. It depends.

[0026]

EXAMPLES Hereinafter, the present invention will be specifically described with reference to examples, but the present invention is not limited thereto. (Example) The following etching treatment was performed using a silicon lap wafer (lap abrasive grain count: # 1200) having a diameter of 8 inches. First, the reaction-controlled acid etching
The etching allowance was set to 20 μm, and the mixed acid [HF (50 vol.%): HNO ₃ (70 vol.
%): CH ₃ COOH (99 vol.%) = 1: 2: 1]
Then, etching was performed with a reaction-controlled acid etchant in which 26 g / L of silicon was dissolved. Then 50% hydrofluoric acid:
Diffusion-controlled acid etching was carried out by dissolving 10 g / L of silicon in a mixed acid consisting of 70% nitric acid: 99% acetic acid = 1: 2: 1 (volume ratio) to obtain a diffusion-controlled acid, and setting an etching allowance target of 10 μm. . With respect to the etched product, the flatness, surface roughness and pit depth were measured to investigate the effect of the etching. The results are shown in Table 1.

The actual results for the etching cost target are as follows. Reaction-controlled acid etching charge; target: 2
0 μm, sample number: 50, average value: 20.1 μm, average value ± 3σ: 18.1 to 22.1 μm. The diffusion controlled acid etching allowance is 10 μm, 50 sheets, 9.8 μm,
It was 8.3 to 11.3 μm. Also, the flatness (TT
V, LTV) measurement was performed using a flatness measuring instrument (U / G9500, U / S9600) manufactured by ADE, and surface roughness (Ra) measurement was performed by Kosaka Laboratory Ltd. universal surface shape measuring instrument (SE). -3C type) was used.

[0028]

[Table 1]

(Comparative Example 1) First, the reaction rate-controlled acid etching was performed under the same conditions as those of the examples except that the etching rate target was 4 μm, and then immediately subjected to the diffusion rate-controlled acid etching with the etching rate target of 26 μm. . The results are also shown in Table 1.

Comparative Example 2 Only 30 μm reaction rate-controlled acid etching was carried out aiming at the etching margin used in the example. The results are also shown in Table 1.

As is clear from this table, only by the reaction-controlled acid etching (Comparative Example 2), the flatness of the wafer was good, but the surface roughness and especially the depth of the deep local pits became deep, and the reaction-controlled rate was increased. When the diffusion rate-controlled acid etching (Comparative Example 1) is performed after the type-controlled acid etching, since the diffusion-controlled acid etching amount is large, on the contrary, the flatness of the wafer is significantly deteriorated. On the other hand, if etching is performed by setting the reaction rate-controlled acid etching rate and the diffusion-controlled rate etching rate to appropriate values (Example), the flatness, surface roughness, and local deep pit depth are A well-balanced result was obtained. Further, as a result of observing the uneven shape of each surface with a microscope, it was found that the example has an extremely smooth uneven shape as compared with the comparative example 2, and is at substantially the same level as the comparative example 1.

The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, has substantially the same configuration as the technical idea described in the scope of the claims of the present invention, and has any similar effect to the present invention. It is included in the technical scope of the invention.

For example, in the above-described embodiment, the reaction rate-controlled acid etching solution and the diffusion rate-controlled acid etching solution are exemplified by a solution of silicon in a mixed acid aqueous solution of hydrofluoric acid, nitric acid, acetic acid, and water. However, even if the mixed acid aqueous solution is a mixed acid aqueous solution mainly composed of a ternary system of hydrofluoric acid, nitric acid, and water, and acetic acid, phosphoric acid, or sulfuric acid is added to the mixed acid aqueous solution, the present invention is similarly applicable. You can

Further, for example, in the above embodiment, the semiconductor wafer has been described by taking the case of semiconductor silicon as an example, but the present invention is not limited to this, and other semiconductor materials such as Ge, GaAs, and GaP are used. The present invention can be similarly applied to a compound semiconductor single crystal such as InP or InP.

[0035]

As described above, according to the present invention,
The flatness of the wafer after lapping can be maintained, the waviness of the wafer surface after etching can be reduced,
It is possible to suppress the occurrence of local deep pits and the deterioration of surface roughness, and it is possible to fabricate a chemical etching wafer that has an etching surface that does not easily cause contamination such as particles and stains, so the stock removal in mirror polishing is reduced. The flatness can be improved.

[Brief description of drawings]

FIG. 1 is a graph showing the relationship between the etching allowance of a reaction rate-controlled acid-etched wafer after lapping and the local deep pit depth.

FIG. 2 is a graph showing the relationship between the etching allowance and the TTV (flatness) of a reaction rate-controlled acid-etched wafer after lapping.

FIG. 3 is a graph showing a relationship between an etching allowance and a surface roughness (Ra) of a wafer which has been subjected to reaction rate-controlled acid etching after lapping.

FIG. 4 is a graph showing the relationship between the etching allowance of a wafer that has been subjected to reaction rate-controlled acid etching after lapping and LTVmax (flatness).

FIG. 5 is a graph showing the relationship between the etching allowance and the TTV (flatness) of a wafer subjected to diffusion-controlled acid etching after lapping.

FIG. 6 is a graph showing the relationship between the etching rate by diffusion-controlled acid etching and the occurrence rate of stain after lapping.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-92777 (JP, A) JP-A-9-266193 (JP, A) JP-A-6-45314 (JP, A) JP-A-7- 106297 (JP, A) JP-A-5-291238 (JP, A) JP-A-3-1537 (JP, A) JP-A-6-333897 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21 / 304,21 / 306,21 / 308

Claims (4)

(57) [Claims] 1. A semiconductor wafer obtained by slicing a single crystal rod is at least chamfered, lapped, etched,
In a semiconductor wafer processing method comprising a mirror polishing and washing step, after the reaction rate-controlled acid etching in the etching step, a diffusion rate-controlled acid etching is performed, in which case the etching allowance of the reaction-controlled acid etching is A method for processing a semiconductor wafer, which is characterized in that it is larger than an etching allowance of diffusion-controlled acid etching. 2. The method of processing a semiconductor wafer according to claim 1, wherein the etching allowance is 10 to 30 μm in the reaction-controlled acid etching and 5 to 20 μm in the diffusion-controlled acid etching. 3. The reaction-controlled acid etching solution and the diffusion-controlled acid etching solution are solutions of silicon in a mixed acid aqueous solution of hydrofluoric acid, nitric acid, acetic acid, and water, and 3. The method of processing a semiconductor wafer according to claim 1, wherein the silicon concentration is higher than the silicon concentration of the diffusion-controlled acid etching solution. 4. The reaction-controlled acid etching solution has a silicon concentration of 20 to 30 g / L, and the diffusion-controlled acid etching solution has a silicon concentration of 5 to 15 g / L. 3. The method for processing a semiconductor wafer according to item 3.