JP2005032804A - Semiconductor wafer processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer processing method capable of preventing chipping failure from occurring in the corner of a wafer at which an OF cleavage plane forms a right angle with the front and rear of the wafer in a both-side lapping operation. <P>SOLUTION: A semiconductor single crystal ingot is sliced into wafers 1. The wafer 1 is sequentially subjected to a both-side lapping process D, a scribing process B of forming a cleavage plane, and a chamfering process C of chamfering the periphery 6 of the wafer except the cleavage plane 4. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor wafer processing method, and more particularly to a processing method in which a wafer having a cleavage plane serving as an orientation flat portion or an index flat portion is used as a mirror surface wafer.
[0002]
[Prior art]
Compound semiconductors are used to fabricate Schottky gate field effect transistors (MESFET), high electron mobility transistors (HEMT), heterojunction bipolar transistors (HBT), various light receiving and light emitting devices. The active layer of these elements is formed on the surface of a mirror wafer by molecular beam epitaxy (MBE), metal organic vapor phase epitaxy (MOVPE), ion implantation, or the like.
[0003]
In a compound semiconductor wafer used as a substrate for a semiconductor laser, an orientation or index flat portion may be formed by a cleaved surface without chamfering. When manufacturing a laser, etc., after forming an epitaxial layer on the wafer, it is necessary to accurately cut the chip along the cleavage plane, and the orientation flat or index flat formed on the cleavage plane is used as a reference. This is because angle adjustment is performed.
[0004]
The above mirror wafer (semiconductor wafer) is generally manufactured through the following series of manufacturing processes (parts of which are shown in FIG. 2). That is, after the outer periphery of a single crystal ingot manufactured by the VGF method or the boat method is performed, slicing is performed with an inner peripheral saw or a wire saw to obtain a slice wafer 1 (slicing step A).
[0005]
Next, for example, an orientation flat (OF) portion 5 for positioning in the crystal direction is formed on the slice wafer 1 using the cleavage plane of the crystal. That is, a crystal is cleaved by scratching and scribing the wafer using a diamond pen, and the cleavage plane is used as an OF portion (scribing step B).
[0006]
After grinding the wafer outer periphery excluding the cleavage surface 4 of this wafer into a circle and chamfering this circular outer periphery 6 by beveling (chamfering step C), uniform thickness and parallelism by double-sided lapping processing, Finish until flatness and some surface roughness (double-sided lapping step D). Specifically, lapping is performed to improve flatness and thickness accuracy, and grinding is performed for 30 to 50 μm to obtain a lapped wafer. The lap is lapped on a casting surface plate or a glass surface plate using # 1000-1500 alumina abrasive grains.
[0007]
The wrapped wafer obtained as described above is subjected to etching with acid or alkali to remove the processing strain and remove the processing damage layer (etching process), and then mirror finished by mechanochemical polishing (single side) Primary mirror polishing process, single-sided mirror polishing process).
[0008]
However, if the cleaved surface of the wafer is used as it is for orientation flattening and alignment as it is without processing the cleaved surface of the wafer, the corner where the cleaved surface of the wafer makes a right angle with the front and back surfaces of the wafer is easily missing during the wafer processing process. That is, there is a problem that chipping is likely to occur, and the wafer is liable to break due to this chipping (chip), the defect rate of the wafer is increased, and the yield is lowered.
[0009]
In order to prevent such a problem from occurring, a method of grinding the entire circumference of the wafer including the cleaved surface of the wafer is known. However, since this is a method of grinding the entire circumference of the wafer including the cleavage plane at the same time, it depends on the state of the grinding machine and the skill of the operator, compared to the case where the orientation plane is left as it is without machining the cleavage plane. There is a problem that the accuracy of discrimination and alignment of the crystal orientation of the wafer by the orientation flat deteriorates.
[0010]
Further, when the wafer is used for a semiconductor laser or the like, the chamfered surface is used as the resonance surface because the resonance surface needs to have good flatness. Cannot be used for such applications.
[0011]
Therefore, as shown in FIGS. 3A and 3B, after cleaving surface 12 is formed on the outer periphery of wafer 10 to form the orientation flat, the chamfering of the corner portion of the orientation flat is performed using a chamfering apparatus. It has been proposed to form the chamfered portion 14 by processing (see Patent Document 1). In this chamfering process, a chamfering process is performed by using a jig having an angle between the surface of the wafer 10 and the chamfered part 14 of 22 degrees so that the cleaved surface 12 remains with a thickness of 300 μm.
[0012]
In this way, if the chamfered corners where the cleaved surface of the wafer is perpendicular to the front and back surfaces of the wafer are chamfered, the wafer is in the process of processing without reducing the crystal orientation and alignment accuracy of the wafer by the orientation flat. In addition, it is possible to prevent wafer damage such as chipping and cracking, and to reduce the wafer defect rate.
[0013]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-052448 [0014]
[Problems to be solved by the invention]
However, as disclosed in Patent Document 1, in a method of chamfering a corner where the cleaved surface of the wafer is perpendicular to the front and back surfaces of the wafer, the predetermined thickness remaining on the cleaved surface is less than the thickness of the semiconductor wafer. It is necessary to perform chamfering so that the thickness is 1/2 to 9/10. For example, it is necessary to perform chamfering using a jig whose angle between the surface of the wafer 10 and the chamfered portion 14 is 22 degrees so that the portion of the cleaved surface 12 remains with a thickness of 300 μm.
[0015]
Therefore, it is desirable to provide a method for preventing wafer damage such as chipping and cracking during the wafer processing process and reducing the wafer defect rate without chamfering the corners of the wafer cleavage surface.
[0016]
Now consider the method of FIG. 2 described above. When a compound semiconductor wafer is used for a semiconductor laser or the like, the resonance surface needs to have a good flatness, the crystal orientation is discriminated, alignment, focusing, etc. Use the surface. For this reason, the orientation flat (OF) part (or index flat (IF) part) of the product for laser use has a cleavage specification. The cleavage of the OF portion is formed by using a diamond pen as described above and scratching and scribing the wafer (scribing step B). The scribing operation is usually performed after slicing, and then chamfering is performed except for the cleaved surface (chamfering step C), and then the double-sided lapping operation is performed (double-sided lapping step D). That is, the slicing process A → the scribing process B → the chamfering process C → the double-sided lapping process D is performed in this order.
[0017]
However, the problem with this sequence is that in the double-sided lapping operation (double-sided lapping process D), the corner where the OF cleaved surface is perpendicular to the front and back surfaces of the wafer is damaged by a surface plate, abrasive, foreign matter, etc. In response to this, chipping (missing) occurs at a rate of about 7% (reference value), which is a major factor in yield reduction.
[0018]
Accordingly, an object of the present invention is to solve the above-mentioned problem and, on the premise that the corner portion of the wafer cleavage surface is not chamfered, the corner portion where the OF cleavage surface forms a right angle with the front and back surfaces of the wafer in a double-sided lapping operation. It is an object of the present invention to provide a method for processing a semiconductor wafer that can prevent chipping defects occurring in the semiconductor wafer.
[0019]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured as follows.
[0020]
According to a first aspect of the present invention, there is provided a semiconductor wafer processing method comprising: a double-sided lapping step, a scribing step for forming a cleaved surface, and a wafer outer peripheral portion excluding the cleaved surface portion of a wafer sliced from a semiconductor single crystal ingot. It processes in the order of a chamfering process, It is characterized by the above-mentioned.
[0021]
The invention of claim 2 includes a step of slicing a semiconductor single crystal ingot into a wafer, and a step of finishing the sliced wafer into a lapped wafer having uniform thickness, parallelism, flatness, and a certain degree of surface roughness by double-sided lapping. Scribing the wrapped wafer to cleave the crystal, making the cleaved surface an orientation flat part or an index flat part, and chamfering the wafer outer periphery excluding the cleaved part of the wafer by beveling; A method for processing a semiconductor wafer, comprising:
[0022]
According to a third aspect of the present invention, in the semiconductor wafer processing method according to the first or second aspect, the semiconductor wafer is a group IV semiconductor, or a group III-V compound comprising any one of GaAs, conductive GaAs, and InP. It is a semiconductor or a II-VI group compound semiconductor.
[0023]
<Key points of the invention>
The present invention is a method of processing a semiconductor wafer having a cleavage plane in the order of [double-sided lapping → cleavage plane scribing → chamfering] (see FIG. 1). The usual processing method is [cleaved surface scribe → chamfering → double-sided lapping] (see FIG. 2).
[0024]
In a double-sided lapping operation for a wafer having a cleavage plane, the OF cleavage plane is likely to be chipped (notched) at the corners perpendicular to the front and back surfaces of the wafer. As a method for preventing this, in the present invention, processing is performed in the order of double-sided lapping → cleavage surface scribe → chamfering. According to this method, since the cleavage plane is formed by scribing after double-sided lapping in which chipping occurs, chipping can be completely prevented.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described based on the illustrated embodiments.
[0026]
In the semiconductor wafer processing method according to the present invention, as shown in FIG. 1, a semiconductor single crystal ingot is sliced into a wafer (slice process A), and double-sided lapping is performed on the slice wafer 1 (double-sided lapping process D). Then, a cleaved surface is formed by scribing (scribing step B), and the wafer outer peripheral portion excluding the cleaved surface portion is chamfered (chamfering step C). Conventional processing methods that are conventionally performed include a slicing step A, a cleavage surface scribing step B, a chamfering step C, and a double-sided lapping step D (see FIG. 2). The semiconductor wafer processing method according to the present invention is different from the conventional method in that the double-sided lapping step D is performed before the cleavage plane scribing step B.
[0027]
In detail, in the slicing step A of FIG. 1, the semiconductor single crystal ingot is sliced into a wafer to obtain a slice wafer 1.
[0028]
A semiconductor single crystal ingot manufactured by the VGF method or the boat method is sliced with an inner peripheral saw or a wire saw to obtain an as-sliced wafer 1.
[0029]
Next, double-sided lapping is performed on the slice wafer 1 (double-sided lapping process D). In this double-sided lapping process D, the slice wafer 1 is finished to a wafer (wrapped wafer 2) having a uniform thickness, parallelism, flatness and a certain degree of surface roughness by double-sided lapping. Specifically, in order to improve the flatness and thickness accuracy, 30-50 μm is ground to obtain a wrapped wafer. The lap is lapped on a casting surface plate or a glass surface plate using # 1000-1500 alumina abrasive grains.
[0030]
Next, in the scribing step B, the wrapped wafer 2 is scribed at the position of the dotted line 3 in FIG. 1 to cleave the crystal, and the cleavage plane 4 is used as an orientation flat (OF) portion.
[0031]
Next, in the chamfering step C, the outer peripheral portion of the wafer is ground into a circle while leaving the cleaved surface 4 of this wafer, and further, the circular outer peripheral portion 6 of the wafer excluding this cleaved portion (orientation flat portion 5), To be precise, chamfering is performed on the ridgeline between the wafer outer peripheral portion 6 and the front and back surfaces of the wafer by beveling with a grinding wheel.
[0032]
<Example 1>
After etching 500 conductive GaAs single crystal as-sliced wafers, they were processed in the order of double-sided lapping process D → scribing process B → chamfering process C. When the corner part of the wafer's OF cleaved surface 4 perpendicular to the front and back surfaces of the wafer was observed with a 50 × microscope and a fluorescent lamp, the scribing process B was performed after the double-sided lapping process D. No chipping was observed on both the front and back surfaces of the wafer. There were no other OF orientation deviations, cracks, etching unevenness, scratch defects, or the like.
[0033]
Next, after etching, the wafer was attached to a sticking plate having a surface flatness finished with high accuracy using wax, primary polishing and finish polishing were performed, and then the wafer was removed and the wax was removed and cleaned. After that, all 500 wafer cleaved parts were inspected by visual observation under a 50 × microscope and a fluorescent lamp. However, no chipping defects and other OF orientation misalignments, cracks, etching unevenness, scratch defects, etc. were found. .
[0034]
【The invention's effect】
As described above, in the present invention, in a conventional double-sided lapping operation for a wafer having a cleavage plane, as a means for preventing chipping (chips) that are likely to occur at corners where the OF cleavage plane is perpendicular to the front and back surfaces of the wafer, Machining in the order of double-sided wrapping → cleavage scribe → chamfering. That is, according to the processing method of the present invention, since the cleavage surface is formed by the scribing process after the double-sided lapping process in which chipping occurs, the chipping that has occurred in the conventional double-sided lapping work can be completely prevented. .
[0035]
The effects of the present invention are summarized as follows.
[0036]
(1) By using the processing method of the present invention, it is possible to completely prevent chipping defects on the wafer cleavage plane.
[0037]
(2) By using the processing method of the present invention, it becomes possible to discriminate, align and focus the crystal orientation with high accuracy, and to increase the production yield of the element.
[Brief description of the drawings]
FIG. 1 is a diagram showing a method for processing a semiconductor wafer according to the present invention.
FIG. 2 is a view showing a conventional method for processing a semiconductor wafer.
FIG. 3 is a view showing another processing method of a conventional semiconductor wafer.
[Explanation of symbols]
1 As-sliced wafer 2 Wrapped wafer 3 Dotted line (scribe position)
4 Cleaved surface 5 Orientation flat part 6 Outer part

Claims (3)

A semiconductor characterized in that a wafer sliced from a semiconductor single crystal ingot is processed in the order of a double-sided lapping step, a scribing step for forming a cleavage plane, and a chamfering step for the outer periphery of the wafer excluding the portion of the cleavage plane. Wafer processing method. Slicing a semiconductor single crystal ingot into a wafer;
Finishing this slice wafer into a lapped wafer having a uniform thickness, parallelism, flatness and a certain degree of surface roughness by double-sided lapping,
Scribing the wrapped wafer to cleave the crystal, and making the cleavage plane into an orientation flat part or an index flat part,
And a step of chamfering the wafer outer peripheral portion excluding the cleavage portion of the wafer by beveling. In the processing method of the semiconductor wafer of Claim 1 or 2,
A semiconductor wafer characterized in that the semiconductor wafer is a group IV semiconductor, a group III-V compound semiconductor made of GaAs, conductive GaAs or InP, or a group II-VI compound semiconductor. Processing method.

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