JP7131724B1 - Semiconductor wafer manufacturing method - Google Patents

Abstract

A semiconductor wafer manufacturing method capable of suppressing the deterioration of the surface roughness of the wafer notch portion due to the polishing rate of the wafer notch portion in a mirror chamfering process in semiconductor wafer manufacturing. A chamfering step of grinding a peripheral edge portion of a wafer to form a chamfered portion including a wafer edge portion and a wafer notch portion, a double-side polishing step, a mirror chamfering step, and a mirror polishing step, wherein the wafer is mirror-finished. The chamfering step includes a first mirror chamfering process of polishing the wafer notch portion before the double-sided polishing step, and a second mirror chamfering process of polishing the wafer notch portion and the wafer edge portion after the double-sided polishing step. In the mirror chamfering process, all of the first inclined part, the second inclined part and the end part of the end surface of the wafer notch part are polished, and the polishing rate of the wafer notch part is set to that of the wafer notch part in the first mirror chamfering process. A method of manufacturing a semiconductor wafer, characterized in that the polishing rate is lower than the polishing rate. [Selection drawing] Fig. 4

Description

The present invention relates to a method of manufacturing a semiconductor wafer.

As a method of manufacturing semiconductor wafers, a slicing process for cutting out thin wafers from a single crystal ingot, a chamfering process for preventing chips and cracks at the peripheral edge of the wafer, a lapping process for eliminating thickness variations and flattening the wafer, or double-sided A grinding process, an etching process to remove wafer distortion and contaminants introduced by lapping and double-side grinding as described above, and an etching process on both front and back surfaces to obtain high-precision wafer flatness quality and nanotopography quality. It is common to carry out a double-side polishing step of simultaneously polishing, a mirror-beveling step of mirror-finishing the chamfered portion, and a mirror-polishing step of mirror-finishing the main surface of the wafer, etc., in the above order.

As the degree of integration of semiconductor devices improves, finer processing is required for the mirror surface chamfering of the wafer peripheral edge. This is a necessary step for improving the yield of semiconductor devices by suppressing .

Polishing of the notch portion of the wafer is performed in the above-described mirror chamfering process. The purpose of the mirror-beveling process is to mirror-finish the wafer notch and wafer edge, and the processing conditions are adjusted for that purpose. It depends on the rotational speed of the polishing cloth and the pressing pressure of the polishing cloth.

In order to maintain the productivity of the mirror-beveling machine in the above-mentioned mirror-beveling process, a condition with a relatively high polishing rate is used, which causes deterioration of the roughness. According to Patent Document 1, the roughness after processing deteriorates as the load during processing or the polishing rate increases. Further, polishing is performed a plurality of times and the polishing rate is successively decreased to improve the roughness.

In the mirror surface chamfering process, the wafer notch portion and the wafer edge portion are usually processed in the same mirror surface chamfering machine regardless of the order in consideration of productivity. Therefore, setting the polishing time for the wafer notch portion to greatly exceed the processing time for polishing the wafer edge portion leads to an increase in the residence time of the wafer in the mirror beveling machine, resulting in deterioration of productivity.

Therefore, conventionally, the polishing time of the wafer notch portion is about the same as the polishing time of the wafer edge portion. Sufficiently improved notch roughness is not obtained.

Patent No. 3846706 Patent No. 6825733 Japanese Patent Application Laid-Open No. 2001-300837

The present invention has been made to solve the above problems, and can suppress the deterioration of the surface roughness of the wafer notch portion due to the polishing rate of the wafer notch portion in the mirror chamfering process in the manufacture of semiconductor wafers. It is an object of the present invention to provide a method for manufacturing a semiconductor wafer.

In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor wafer, comprising:
A chamfering step of grinding at least a peripheral edge portion of a wafer having a wafer notch portion to form a chamfered portion including the wafer edge portion and the wafer notch portion, and a double-side polishing step of polishing both main surfaces of the wafer; A mirror surface beveling step of polishing the chamfered portion to a mirror surface, and a mirror surface polishing step of mirror polishing at least one of the two main surfaces,
The mirror chamfering step is
a first mirror chamfering process for polishing the wafer notch portion of the chamfered portion before the double-sided polishing step;
a second mirror chamfering process for polishing the wafer notch portion and the wafer edge portion after the double-sided polishing step;
The end surface of the wafer notch portion is
a first inclined portion continuous from one main surface of the wafer and inclined from the one main surface;
a second inclined portion continuous from the other main surface of the wafer and inclined from the other main surface;
and an end portion constituting the outermost peripheral portion of the wafer,
polishing all of the first inclined portion, the second inclined portion and the end portion of the end face of the wafer notch portion in the second mirror chamfering process;
A method for manufacturing a semiconductor wafer is provided, wherein the polishing rate of the wafer notch portion in the second mirror-chamfering process is set to be lower than the polishing rate of the wafer notch portion in the first mirror-chamfering process.

According to the semiconductor wafer manufacturing method of the present invention, it is possible to suppress the deterioration of the surface roughness of the wafer notch portion due to the polishing rate of the wafer notch portion in the mirror chamfering process in semiconductor wafer manufacturing while maintaining productivity. can be done.

For example, the semiconductor wafer can be a silicon wafer.

A semiconductor wafer that can be manufactured by the method for manufacturing a semiconductor wafer of the present invention is not particularly limited, but for example, a silicon wafer can be manufactured.

In polishing the wafer notch portion in the first and second mirror chamfering processes, it is preferable to perform polishing by inserting a circular polishing cloth into the wafer notch portion perpendicularly to the wafer surface.

In this way, the wafer notch portion can be reliably polished in the mirror chamfering process, and the desired shape, surface state, and roughness can be achieved.

As described above, according to the method for manufacturing a semiconductor wafer of the present invention, when manufacturing a semiconductor wafer, the main surface is mirror-beveled before and after the double-side polishing process, and the second mirror-surface polishing is performed after the double-side polishing process. By polishing all of the first inclined portion, the second inclined portion, and the end portion of the end surface of the wafer notch portion in the processing step, and reducing the polishing rate during the second mirror chamfering after the double-sided polishing step, It is possible to suppress deterioration of the surface roughness of the wafer notch portion due to a high polishing rate while maintaining productivity and obtaining a sufficient removal amount. Therefore, it is possible to manufacture a semiconductor wafer having a wafer notch portion with excellent surface roughness.

1 is a schematic plan view showing an example of a semiconductor wafer that can be manufactured by the semiconductor wafer manufacturing method of the present invention; FIG. It is a typical schematic diagram explaining the wafer notch shape after a chamfering process. FIG. 4 is a cross-sectional view showing an example of a wafer notch portion after a chamfering process; 1 is a flowchart showing an example of a method for manufacturing a semiconductor wafer according to the present invention; FIG. 5 is a graph showing the surface roughness of the wafer notch portion of semiconductor wafers obtained in Examples and Comparative Examples.

As described above, in the mirror-beveling process, the wafer notch and the wafer edge are mirror-finished, and the processing conditions are adjusted for that purpose. , the processing time, the rotation speed of the polishing cloth, and the pressing pressure of the polishing cloth.

The original purpose of the mirror chamfering process is to remove scratches and the like from the chamfered portion and improve the roughness. In order to remove scratches and the like, a polishing allowance of a certain level or more is required, and the more the removal allowance is increased, the less the scratches after processing. Therefore, if mirror surface chamfering is performed under conditions with a high polishing rate, it is possible to obtain the effect of removing scratches and the like in a short time. In the wafer manufacturing method, it was difficult to achieve both removal of scratches and sufficient improvement of roughness.

That is, in the mirror chamfering process, the surface roughness of the wafer notch may deteriorate depending on the polishing rate of the wafer notch. Therefore, there is a need for a wafer manufacturing method capable of solving these problems.

The inventor of the present invention has made intensive studies in order to achieve the above object. As a result, under the condition that the mirror surface beveling process is performed before and after the double-sided polishing process, the first inclined part and the second inclined part of the end face of the wafer notch part are obtained in the second mirror-polishing process performed after the double-side polishing process. The polishing rate of the notch portion of the wafer in the first mirror-beveling process performed before the double-side polishing process is compared with the polishing rate of the notch part of the wafer in the second mirror-polishing process performed after the double-side polishing process. The present inventors have found that the above problems can be solved by reducing the polishing rate, and have completed the wafer manufacturing method of the present invention.

That is, the present invention is a method of manufacturing a semiconductor wafer, comprising:
A chamfering step of grinding at least a peripheral edge portion of a wafer having a wafer notch portion to form a chamfered portion including the wafer edge portion and the wafer notch portion, and a double-side polishing step of polishing both main surfaces of the wafer; A mirror surface beveling step of polishing the chamfered portion to a mirror surface, and a mirror surface polishing step of mirror polishing at least one of the two main surfaces,
The mirror chamfering step is
a first mirror chamfering process for polishing the wafer notch portion of the chamfered portion before the double-sided polishing step;
a second mirror chamfering process for polishing the wafer notch portion and the wafer edge portion after the double-sided polishing step;
The end surface of the wafer notch portion is
a first inclined portion continuous from one main surface of the wafer and inclined from the one main surface;
a second inclined portion continuous from the other main surface of the wafer and inclined from the other main surface;
and an end portion constituting the outermost peripheral portion of the wafer,
polishing all of the first inclined portion, the second inclined portion and the end portion of the end face of the wafer notch portion in the second mirror chamfering process;
In the semiconductor wafer manufacturing method, the polishing rate of the wafer notch portion in the second mirror-chamfering process is set to be lower than the polishing rate of the wafer notch part in the first mirror-chamfering process.

Patent documents 1 and 2 disclose techniques for polishing the chamfered portion of a wafer. Further, Japanese Patent Laid-Open Publication No. 2002-200000 discloses a technique relating to a method and an apparatus for polishing a notch portion of a wafer. However, in each of Patent Documents 1 to 3, the chamfered portion of the wafer is mirror-finished before and after the double-side polishing process for both main surfaces of the wafer, and the wafer notch portion in the mirror-beveling process performed before the double-side polishing process. It neither describes nor suggests that the polishing rate of the wafer notch portion in the mirror surface chamfering performed after the double-side polishing process is made smaller than the polishing rate.

Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.

[Semiconductor wafer]
First, an example of a semiconductor wafer that can be produced by the method for producing a semiconductor wafer of the present invention will be described.

FIG. 1 is a schematic plan view showing an example of a semiconductor wafer that can be manufactured by the semiconductor wafer manufacturing method of the present invention.

A semiconductor wafer W shown in FIG. 1 has a first main surface 11 which is a mirror surface and a second main surface 12 on the back side thereof. A chamfered portion 1 is formed on a peripheral portion 13 of the semiconductor wafer W. As shown in FIG. The chamfered portion 1 includes a wafer edge portion 3 formed along a peripheral edge portion 13 and a wafer notch portion 2 formed in a portion of the wafer edge portion 3 .

Here, details of the shape of the wafer notch portion will be described with reference to FIGS. 2 and 3. FIG. FIG. 2 shows the peripheral portion of the wafer notch portion 2 viewed from the main surface 11 direction of the wafer W. As shown in FIG. The wafer notch portion 2 is roughly divided into a bottom portion 2a and a straight portion 2b. Here, the notch bottom portion 2a is the deepest portion of the wafer notch portion 2 and has a curved contour, and the notch linear portion 2b is a portion having a linear contour located at both ends of the bottom portion. FIG. 3 shows a cross-sectional view of the end face of the wafer notch portion 2 in the wafer thickness direction. Here, the end surface corresponds to a portion located at the outermost periphery of the wafer W and approximately perpendicular to the main surfaces 11 and 12 of the wafer W. As shown in FIG. The cross-sectional shape has a first inclined portion 21 continuous from the first main surface 11 which is one main surface of the wafer and inclined from the first main surface 11 . Moreover, this chamfered cross-sectional shape has a second inclined portion 22 which is continuous from the second main surface 12 which is the other main surface of the wafer W and which is inclined from the second main surface 12 . Furthermore, it has an edge 23 forming the outermost edge of the wafer W. As shown in FIG. The edge 23 portion conventionally has a slight slope. These cross-sectional shapes are common to the bottom portion 2a and straight portion 2b of the wafer notch portion 2 and the wafer edge portion 3 shown in FIG.

[Semiconductor wafer manufacturing method]
Next, the method for manufacturing a semiconductor wafer according to the present invention will be described with an example with reference to FIG. In the following description, the semiconductor wafer shown in FIGS. 1 to 3 will be referred to again.

FIG. 4 is a flowchart showing an example of the method for manufacturing a semiconductor wafer according to the present invention.

The semiconductor wafer manufacturing method of this example includes a chamfering step of grinding a peripheral edge portion 13 of the wafer 1 having the wafer notch portion 2 to form the chamfered portion 1 including the wafer edge portion 3 and the wafer notch portion 2; A first mirror chamfering process for polishing the wafer notch portion 2 of 1, a double-side polishing step for polishing both main surfaces 11 and 12 of the wafer 1, and a second polishing step for polishing the wafer notch portion 2 and the wafer edge portion 3. It includes a mirror chamfering process and a mirror polishing process for mirror-polishing at least one of both main surfaces 11 and 12 . That is, before the double-sided polishing process of the main surfaces 11 and 12, the first mirror chamfering process for polishing the wafer notch part 2 of the chamfered part 1 is performed, and after the double-sided polishing process of the main surfaces 11 and 12, the wafer of the chamfered part 1 A second mirror chamfering process is performed to polish both the notch portion 2 and the wafer edge portion 3 . In the second mirror chamfering process, all of the first inclined portion 21, the second inclined portion 22 and the end portion 23 of the end surface of the wafer notch portion 2 are polished. Then, the polishing rate of the wafer notch portion 2 in the second mirror chamfering process of the chamfered portion is made smaller than the polishing rate of the wafer notch portion 2 in the first mirror chamfering process. The first and second specular chamfering processes are included in the specular chamfering step of polishing the chamfered portion to provide a mirror finish.

With such a semiconductor wafer manufacturing method, if a sufficient polishing allowance for the wafer notch portion 2 can be obtained in the first mirror-chamfering process before the double-side polishing process, the polishing rate in the second mirror-chamfering process can be reduced to Even if it is made smaller, it is possible to finally obtain a sufficient polishing allowance for the wafer notch portion 2, so that the polishing rate of the wafer notch portion 2 in the second mirror chamfering process can be reduced.

Further, the polishing rate of the wafer notch portion 2 during the second mirror chamfering process is made smaller than the polishing rate of the wafer notch portion 2 in the first mirror chamfering process, and the first inclined portion 21 of the end surface of the wafer notch portion 2, The surface roughness of the wafer notch portion 2 can be improved by polishing all of the second inclined portion 22 and the edge portion 23 .

In the first mirror chamfering process, the processing time, polishing cloth rotation speed, and pressing pressure during processing can be set arbitrarily. .

In the second mirror chamfering process as well, the processing time, polishing cloth rotation speed, and pressing pressure during processing can be set arbitrarily. Therefore, it is desirable to reduce these in the second mirror chamfering process. By making these conditions in the second mirror-chamfering process smaller than the conditions in the first mirror-chamfering process, the polishing rate of the wafer notch portion 2 in the second mirror-chamfering process is equal to the polishing rate in the first mirror-chamfering process. can be smaller than It is preferable to reduce the polishing rate of the wafer notch portion 2 in the second mirror chamfering process to the extent that it is possible to prevent the process from taking a long time and reducing the productivity.

The processing conditions set for the first mirror-chamfering process and the second mirror-chamfering process must be such that the polishing rate of the wafer notch portion 2 is smaller in the second mirror-chamfering process. Arbitrary conditions may be set for each. This is because the purpose of the first mirror surface chamfering is to remove surface scratches and the like, while the purpose of the second mirror surface chamfering is to reduce the roughness immediately after the first mirror surface chamfering. This is because the purpose is to improve them, and the processing conditions may be arbitrary as long as those purposes are achieved.

Each of the first mirror chamfering process and the second mirror chamfering process may be performed once, or may be performed in multiple steps.

As a specific polishing method for the wafer notch portion 2, in the first mirror chamfering process, the wafer W is set perpendicular to the polishing surface of the circular polishing cloth, and the polishing cloth is inserted to the deepest part of the notch. Polishing is performed while traversing in the plane direction of W, and in the second mirror-beveling process, polishing is performed by the same mechanism under a processing condition smaller than the polishing rate in the first mirror-beveling process. can be reliably polished to a desired shape, surface condition, and roughness.

Moreover, the present invention can be particularly suitably used in a wafer manufacturing method in which the wafer edge portion 13 is mirror-beveled before and after the double-side polishing process of the main surfaces 11 and 12 . By polishing the wafer notch portion 2 and the wafer edge portion 3 in the first mirror chamfering process, adhering foreign matter can be removed and the occurrence of scratches in the double-side polishing process can be suppressed. In addition, scratches on the wafer edge portion 13 caused by contact with the inner wall of the carrier hole generated in the double-sided polishing process can also be removed by the second mirror chamfering process. In this process, the present invention can be used particularly efficiently in terms of productivity, and both the yield improvement and the surface roughness improvement effect of the wafer notch portion 2 can be obtained.

The wafer manufacturing method of the present invention can be particularly suitably used in a method for manufacturing a single crystal silicon wafer obtained from a single crystal silicon ingot.

Hereinafter, the present invention will be described in more detail by showing specific examples with reference to the drawings. 1 to 4 will be referred to again in the following description.

In this example, first, a single crystal ingot is sliced to obtain a sliced wafer W having a wafer notch portion 2 . As the single crystal ingot at this time, it is possible to use a single crystal silicon ingot having grooves formed in the peripheral portion thereof to become the wafer notch portion 2 later. The wafer manufacturing method of the present invention can be particularly suitably used in a method for manufacturing a semiconductor wafer, particularly a single crystal silicon wafer obtained from a single crystal silicon ingot.

Next, a chamfering process (chamfering step) is performed to form the chamfered portion 1 including the wafer edge portion 3 and the wafer notch portion 2 by grinding the peripheral portion of the wafer obtained in the above step. The chamfering process is not particularly limited and any process that is generally performed can be applied. An example of the wafer notch shape after this chamfering is the shape shown in FIGS. 2 and 3 described above.

After performing the chamfering process as described above, the main surfaces 11 and 12 of the wafer W can be subjected to lapping or double-sided grinding. Lapping and double-sided grinding are not particularly limited and can be applied to any process that is generally performed.

Next, the wafer W subjected to the above-described processing can be etched in order to remove the processing distortion introduced by processing such as chamfering and lapping. Etching is not particularly limited, and any process that is commonly used can be applied.

Next, in the present invention, a first mirror chamfering process is performed in order to secure a sufficient polishing allowance for the wafer notch portion 2 . It is desirable to bring a circular polishing cloth into contact with at least the bottom portion 2a and straight portion 2b of the wafer notch portion 2 to mirror-polish the chamfered portion.

In such a first mirror chamfering process, for example, a mechanism for inserting a circular polishing cloth into the wafer notch portion 2 at an angle perpendicular to the main surfaces 11 and 12 of the wafer W is used. A circular polishing cloth having a predetermined rotation speed and rotation direction is inserted into the wafer notch portion 2 while supplying polishing slurry to the wafer notch portion 2, and is pressed against the bottom portion 2a of the wafer notch portion 2 for polishing. I do. During processing, the circular polishing cloth traverses the main surfaces 11 and 12 of the wafer W in the in-plane direction, so that the linear portion 2b of the wafer notch portion 2 is sufficiently polished. Furthermore, by inclining the wafer W at a predetermined angle during processing, it is possible to sufficiently polish all of the first and second inclined portions 21 and 22 and the end portion 23 shown in FIG. The polishing rate of the wafer notch portion 2 in the first mirror chamfering process can be, for example, 0.20 μm/second or more and 0.30 μm/second or less.

In the first mirror chamfering process, mirror polishing of the wafer edge portion 3 is optional and may or may not be performed.

After performing the first mirror chamfering process, a double-sided polishing step of polishing both main surfaces 11 and 12 of the wafer W is performed. The double-side polishing process is not particularly limited and can be any process that is generally performed.

After performing the double-side polishing process, a second mirror chamfering process is performed for the purpose of improving the surface roughness of the wafer notch portion 2 and mirror-finishing the wafer edge portion 3 . The second mirror chamfering process can be performed using the same mechanism as the first mirror chamfering process. 21, the second slope 22 and the edge 23 are all polished. Also, in the second mirror-chamfering process, the polishing rate of the wafer notch portion 2 is made smaller than the polishing rate of the wafer notch part 2 in the first mirror-chamfering process. For example, the processing time, the number of revolutions of the polishing cloth, and the pressing pressure to the wafer are all made smaller than the conditions for the first mirror chamfering processing. As a result, the load during processing and the polishing rate can be reduced. The polishing rate of the wafer notch portion 2 in the second mirror chamfering process can be, for example, 0.10 μm/second or more and 0.18 μm/second or less. The same conditions as in the prior art can be used for the mirror surface chamfering of the wafer edge portion 3 .

The first and second specular chamfering processes described above are included in the specular chamfering step in the semiconductor wafer manufacturing method of the present invention.

Finally, a mirror-polishing step of mirror-polishing at least one of the main surfaces 11 and 12 of the wafer W is performed. This step may be performed by a general method.

Through the steps described above, the wafer W as a product is manufactured. With such a method for manufacturing the wafer W, it is possible to obtain the effect of improving the surface roughness of the notch portion by a small polishing rate, while maintaining the productivity and sufficiently securing the polishing allowance in the mirror chamfering process. , a higher quality wafer can be produced.

In addition, in the present invention, at the step of the chamfering step, it is sufficient to perform processing incorporating the amount of shape change in the mirror chamfering step, and various steps other than the above may be included. For example, if necessary, a washing step, a heat treatment step, or the like may be performed before or after each of the above steps by a normal method.

EXAMPLES The present invention will be specifically described below using Examples and Comparative Examples, but the present invention is not limited to these.

(Example)
A first mirror chamfering process was performed on a wafer having a wafer notch obtained by sequentially performing slicing, chamfering, lapping and etching processes. The chamfering step formed a chamfer including a wafer edge and a wafer notch, the wafer notch having the shape shown schematically in FIGS. In the first mirror chamfering process, only the notch portion of the wafer was polished in two stages, stage 1 and stage 2, under the condition of ensuring sufficient machining allowance to remove scratches and the like. Specifically, the first mirror chamfering was performed under the conditions shown in Table 1 below.

After the first mirror chamfering process, double-sided polishing was performed to polish both main surfaces of the wafer. Specifically, double-sided polishing was performed under the conditions shown in Table 2 below.

Subsequently, a second mirror chamfering process was performed. The purpose of the second mirror-beveling process is to improve the roughness of the wafer notch portion compared to that immediately after the first mirror-beveling process. went step by step. Specifically, using the same mechanism as the first mirror chamfering process, the first mirror chamfering shown in FIG. and the second inclined portions 21 and 22 and the end portion 23 were polished, and the processing time, the number of revolutions of the polishing cloth, and the pressing pressure of the polishing cloth were all set smaller than the conditions for the first mirror chamfering. Specifically, the second mirror chamfering was performed under the conditions shown in Table 1 below. The mirror surface chamfering of the wafer edge portion, which is essential in the conventional manufacturing process, was performed by this second mirror surface chamfering using the same mechanism and under the same conditions as the conventional one.

Finally, the main surface of the wafer was subjected to a mirror-polishing process.

After completion of the mirror-polishing process, the surface roughness of the wafer notch portion was measured. LSM manufactured by Kobelco Research Institute was used for roughness measurement. Roughness includes macroscopic roughness and microscopic roughness. The roughness in the present invention is assumed to be microscopic roughness, and when analyzing the obtained measurement data, the macroscopic roughness component is removed and only the microscopic roughness component is evaluated. did. Although there are multiple evaluation criteria for roughness, in the present invention, the sum of roughness in an arbitrarily selected area divided by the area of the selected area was used. Here, the arbitrarily selected area indicates a range that is sufficiently affected by polishing, and evaluation between wafers is performed in areas of the same position and the same area. The evaluation areas were the first and second slopes 21 and 22 and the edge 23 at the bottom of the wafer notch shown in FIG.

As a result of the roughness measurement, the surface roughness at the bottom of the wafer notch was 6.85 nm at the first slope 21 and 9.42 nm at the second slope 22, as shown in FIG. 5 and Table 5 below. , and 4.26 nm at the edge 23 .

(Comparative example 1)
As in the conventional semiconductor wafer manufacturing, each process of slicing, chamfering, lapping, etching, double-sided polishing of the main surface, second mirror-beveling, and mirror-polishing of the main surface is sequentially performed to produce four wafers. got That is, in the comparative example, no mirror chamfering was performed before double-side polishing. In the mirror chamfering process of the comparative example, in order to secure a machining allowance that can sufficiently remove scratches and the like, and to manufacture a semiconductor wafer in the same amount of time as in the example, the processing time, As shown in Table 3 below, the number of rotations of the polishing cloth and the pressing pressure of the polishing cloth were set to the same conditions as those of the first mirror-chamfering process in the example, and the mirror-chamfering process was performed. The slicing, chamfering, lapping and etching processes were performed under the same conditions as in the example. Further, double-side polishing of the main surfaces was also performed under the conditions shown in Table 2 as in Example 1.

For the four wafers thus obtained, the wafer notch roughness was measured in the same manner as in the example, and the average roughness was calculated. The method of calculating roughness from the obtained measurement data was the same as in the example, and the selection area was selected at the same position and the same area as in the example.

(Comparative example 2)
In Comparative Example 2, as shown in Table 4 below, four wafers were prepared in the same manner as in Example except that the conditions for the second mirror chamfering process were the same as the conditions for the first mirror chamfering process. Obtained. For the four wafers thus obtained, the wafer notch roughness was measured in the same manner as in the example, and the average roughness was calculated. The method of calculating roughness from the obtained measurement data was the same as in the example, and the selection area was selected at the same position and the same area as in the example.

Table 5 below shows the first inclined portion 21, the second inclined portion 22, and the end portion 23 shown in FIG. Indicates surface roughness.

In the manufacturing process of Comparative Example 1, the polishing rate and the load in the mirror chamfering process performed after the double-sided polishing of the main surface in the manufacturing process are higher than those in the example, so the roughness after processing is large (FIG. 5 and Table 5). As a result, as shown in FIG. 5 and Table 5, the surface roughness of the wafer notch portion after processing in Comparative Example 1 was 13.02 nm at the first inclined portion 21 shown in FIG. 17.58 nm at the edge 23 and 12.54 nm at the end 23, both of which are larger than those of the example. We were able to fabricate wafers with improved

In the manufacturing process of Comparative Example 2, the conditions for the second mirror-chamfering process performed after the double-side polishing process of the main surface were the same as the conditions for the first mirror-chamfering process performed before the double-side polishing process. As a result, as shown in FIG. 5 and Table 5, the surface roughness of the wafer notch portion after processing in Comparative Example 2 was 10.77 nm at the first inclined portion 21 shown in FIG. 10.07 nm at the edge 23 and 5.25 nm at the edge 23, both of which are larger than those of the example. rice field.

It should be noted that the present invention is not limited to the above embodiments. The above-described embodiment is an example, and any device having substantially the same configuration as the technical idea described in the claims of the present invention and exhibiting the same effect is the present invention. is included in the technical scope of

DESCRIPTION OF SYMBOLS 1... Chamfered part 2... Wafer notch part 2a... Bottom part of wafer notch part 2b... Straight part of wafer notch part 3... Wafer edge part 11... First main surface 12... Second main surface Reference numerals 13: Peripheral edge of wafer, 21: First inclined portion, 22: Second inclined portion, 23: Edge, W: Wafer.

Claims (3)

A method of manufacturing a semiconductor wafer, comprising:
A chamfering step of grinding at least a peripheral edge portion of a wafer having a wafer notch portion to form a chamfered portion including the wafer edge portion and the wafer notch portion, and a double-side polishing step of polishing both main surfaces of the wafer; A mirror surface beveling step of polishing the chamfered portion to a mirror surface, and a mirror surface polishing step of mirror polishing at least one of the two main surfaces,
The mirror chamfering step is
a first mirror chamfering process for polishing the wafer notch portion of the chamfered portion before the double-sided polishing step;
a second mirror chamfering process for polishing the wafer notch portion and the wafer edge portion after the double-sided polishing step;
The end surface of the wafer notch portion is
a first inclined portion continuous from one main surface of the wafer and inclined from the one main surface;
a second inclined portion continuous from the other main surface of the wafer and inclined from the other main surface;
and an end portion constituting the outermost peripheral portion of the wafer,
polishing all of the first inclined portion, the second inclined portion and the end portion of the end face of the wafer notch portion in the second mirror chamfering process;
A method for manufacturing a semiconductor wafer, wherein a polishing rate of the wafer notch portion in the second mirror-chamfering process is set to be lower than a polishing rate of the wafer notch part in the first mirror-chamfering process. 2. The method of manufacturing a semiconductor wafer according to claim 1, wherein said semiconductor wafer is a silicon wafer. 2. The wafer notch portion is polished in the first and second mirror chamfering processes by inserting a circular polishing cloth into the wafer notch portion perpendicularly to the surface of the wafer. 3. The method for manufacturing a semiconductor wafer according to claim 1 or 2.

Images