JP2000331898A - Notched semiconductor wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the front and back surfaces easily identifiable by specifying the front surface chamfer quantity of a notched part and the back surface chamfer quantity of a notched semiconductor wafer. SOLUTION: A GaAs compd. semiconductor crystal is sliced into a semiconductor wafer by referring to its (100) plane. The periphery of the wafer is chamfered. One end of the periphery of the wafer is cut (notched) in the (010) direction and a notched part is chamfered continuously by the same machine. The chamfer quantity is set so that the front surface chamfer quantity A is twice or more the back surface chamfer quantity B, A>=2B for easily visually identifying the chamfer quantity difference of the notched part where the front surface chamfer quantity of the notched semiconductor wafer 1 is A and the back surface chamfer quantity is B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a notched semiconductor wafer in which a notch is formed at one end of the outer periphery of a semiconductor wafer in order to identify the crystal orientation of the semiconductor wafer.

[0002]

2. Description of the Related Art In order to maximize the performance of a semiconductor device, it is necessary to manufacture a semiconductor device based on an optimum crystal orientation of a semiconductor wafer as a material. Therefore, the semiconductor wafer is cut to identify the crystal orientation.

FIG. 2 is a plan view showing a first example of a conventional semiconductor wafer. Reference numeral 11 denotes a semiconductor wafer, and 12 denotes an orientation flat. One end of the semiconductor wafer 11 is processed linearly along the reference crystal orientation,
The processed part is called an orientation flat. Hereinafter, it may be abbreviated as an orientation flat. Normal orientation flat 12
Is processed so as to have a length of about に 対 し of the outer diameter of the semiconductor wafer 11.

Now, with the increasing integration of semiconductor devices,
When high flatness is required for the semiconductor wafer 11, it is necessary to perform mirror processing (mirror surface processing) on the front and back surfaces of the semiconductor wafer 11. This mirror processing is performed simultaneously on the front surface and the back surface of the semiconductor wafer 11. When mirror processing is performed on the front and back surfaces of the semiconductor wafer 11 as described above, it is difficult to distinguish the front and back of the semiconductor wafer 11 by using only the orientation flat 12.

FIG. 3 is a plan view showing a second example of a conventional semiconductor wafer. This is provided with an index flat 13 so that the front and back of the semiconductor wafer 11 can be easily identified. The index flat 13
Sometimes it is called a secondary orientation flat.

In recent years, in order to obtain a large number of semiconductor devices from one semiconductor wafer and reduce the chip cost of the semiconductor devices, the diameter of the semiconductor wafer has been increased. As a result, it is inevitable that the weight of the semiconductor wafer increases as the diameter of the semiconductor wafer increases. For this reason, a problem occurred during the high-speed rotation of the semiconductor wafer during a device manufacturing process such as a spin coater.

That is, since the orientation flat 12 and the index flat 13 are provided for the circular semiconductor wafer, an eccentric load is generated during the high-speed rotation of the semiconductor wafer, and the semiconductor wafer vacuum-adsorbed to the rotor. There is a danger that she will leave and fly away.

FIG. 4 is a plan view of a conventional notched semiconductor wafer which solves the above-mentioned problem. As a crystal orientation identification method that replaces the orientation flat 12, notch processing is performed in which a notch is formed at one end of the outer periphery of a semiconductor wafer. The cut depth of the notch 15 is about 1 mm.

FIG. 5 shows a conventional notched semiconductor wafer 14.
It is sectional drawing which shows the chamfered shape of the notch part. A 'is the chamfer amount on the front surface of the notched semiconductor wafer 14, and B' is the chamfer amount on the back surface of the notched semiconductor wafer 14. The chamfer amount is substantially the same for both the front and back surfaces.

[0010]

The conventional notched semiconductor wafer has the following problems.

Although the notch 15 is chamfered in the same manner as the other outer peripheral portions, the same amount of chamfering is performed on the front and rear surfaces. Therefore, when mirror processing is performed on both the front surface and the rear surface, there is a problem that it is not easy to identify the front and back of the notched semiconductor wafer 14 with only the notch 15.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a notched semiconductor wafer in which the above-mentioned drawbacks of the prior art are solved and the front and back surfaces of the notched semiconductor wafer can be easily distinguished.

[0013]

According to the present invention, there is provided a semiconductor wafer having a notch formed by cutting one end of an outer periphery of a semiconductor wafer in order to identify a crystal orientation of the semiconductor wafer. In the above, when the chamfer amount of the front surface of the notch portion is A and the chamfer amount of the back surface is B, the relationship of A ≧ 2 · B is satisfied.

[0014]

FIG. 1 is a sectional view showing an embodiment of a notched semiconductor wafer according to the present invention. Reference numeral 1 denotes a notched semiconductor wafer. The portion with a notch is shown. A is the chamfer amount on the front surface of the notched semiconductor wafer 1, and B is the chamfer amount on the back surface of the notched semiconductor wafer 1. In order to easily visually identify the difference in the amount of chamfering in a portion having a notch, the amount of chamfering on the front surface was set to twice or more than twice the amount of chamfering on the back surface.

Using a 6 inch GaAs (gallium arsenide) compound semiconductor crystal, a notched semiconductor wafer was actually manufactured on a trial basis. From GaAs compound semiconductor crystal (10
0) Based on the plane, slice the crystal to a thickness of 875 μm,
A semiconductor wafer was used.

Next, the outer peripheral portion of the semiconductor wafer was chamfered. 100% thickness on both front and back sides for mirror finishing
μm, and the thickness of the final semiconductor wafer is 675 μm,
In order to set the chamfer amount to 300 μm, the chamfer amount during the chamfering process was set to 550 μm for both the front and back surfaces.

Then, the same apparatus was used to continuously perform notch processing in the [010] direction and chamfering of a portion having the notch. The chamfer amount was 650 μm on the front surface of the semiconductor wafer and 450 μm on the back surface of the semiconductor wafer.

Subsequently, the upper and lower surfaces were polished by 100 μm each by simultaneous double-sided lap and double-sided polishing. Here, when the amount of chamfering in a portion having a notch was visually checked, a difference in the amount of chamfering between the front surface and the back surface could be easily identified. When the chamfer amount was actually measured, the surface was 400 μm,
The back surface was 200 μm. This makes it possible to easily identify the front and back of the notched semiconductor wafer.

[0019]

According to the notched semiconductor wafer of the present invention, the chamfer amount of the front surface is set to twice or more than the chamfer amount of the back surface with respect to the chamfer amount of a portion having a notch, so that the front and back surfaces can be easily formed. This makes it possible to prevent a simple mistake of mistaking the notched semiconductor wafer during the wafer handling during the process, thereby improving the device yield.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a notched semiconductor wafer of the present invention.

FIG. 2 is a plan view showing a first example of a conventional semiconductor wafer.

FIG. 3 is a plan view showing a second example of a conventional semiconductor wafer.

FIG. 4 is a plan view of a conventional notched semiconductor wafer.

FIG. 5 is a sectional view of the notched semiconductor wafer of FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Notch semiconductor wafer 11 Semiconductor wafer 12 Orientation flat 13 Index flat 14 Notch semiconductor wafer 15 Notch A, A 'The chamfer of the surface of the notch B, B' The chamfer of the back of the notch

Claims (1)

[Claims] 1. A notch at one end of an outer periphery of a circular semiconductor wafer for identifying a crystal orientation of the semiconductor wafer.
In a notched semiconductor wafer that has been processed, the notch portion has a chamfer amount on the front surface of A, and a chamfer amount on the back surface of the semiconductor wafer has a chamfer amount of B, so that A ≧ 2 · B is satisfied. A semiconductor wafer with a notch, characterized in that: