JP2000031127A - Method and device for flattening wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve the problems of the expansion and the increase of the COP(crystal-originated particle) present in CZ silicon, when etching amount is increased in local plasma etching (PACE) and to improve the thin-film forma tion of an SOI(silicon on insulator) wafer and the flattening technology of the silicon wafer. SOLUTION: In this flattening method, the part of a nozzle 1 is grounded, and conventional isotropic etching can be made to be anisotropic etching by applying high-frequency electric power on a stage 3 through a blocking capacitor. Furthermore, when the flattening of a wafer 2 is performed at a low pressure (10-3-1 Torr) at which the anisotropic etching becomes dominant, the improving effect of the flatness is obtained without expanding or increasing the COP.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a wafer flattening method and apparatus for obtaining a required wafer flatness by locally plasma etching a wafer surface such as a silicon wafer.
By performing isotropic etching in which radical etching is dominant in E) and anisotropic etching in which ion etching is dominant, COP (Crystal Ori) is obtained.
SOI (Silicon On Ins) without increasing or increasing the size of a grated particle.
The present invention relates to a wafer flattening method and apparatus capable of improving thinning of a wafer and flattening technology of a silicon wafer.

[0002]

2. Description of the Related Art On an oxide film insulating layer formed on a silicon wafer, a single crystal silicon layer of higher quality, that is, SOI (Silicon On Insulato) is used.
r) An SOI wafer having a structure in which an active layer is formed uniformly makes it easy to separate elements, so that high integration, low power consumption, and high speed of devices can be expected, and practical use of some of them is progressing. In.

The thickness of the SOI active layer of an SOI wafer is
It depends on the element structure.
1 μm or less, 0.5 to 0.5 μm for Bi-CMOS
1.0 μm, 1 to 5 μm for bipolar, and several μm or more for high power and sensors.

Various methods for manufacturing SOI wafers have been proposed. Typical SOI wafers include a bonded SOI substrate and a SIMOX (Separa).
Tion by Implanted Oxygen)
There is a wafer.

In the bonding method, a bond wafer serving as an SOI active layer is thermally oxidized to form an oxide film, and after bonding at room temperature to a base wafer having no oxide film, bonding annealing is performed in an oxidizing atmosphere to increase the bonding strength. After that, the bonded SOI wafer is manufactured by thinning the bond wafer by grinding and polishing.

Since the bonded bond wafer is thinned by grinding and polishing, it can be obtained stably when the SOI active layer is relatively thick, but it is difficult to control the thickness to 0.1 μm or less. And has been.

[0007] Therefore, PACE (plasma assisted chem) for performing etching using local plasma in a technique for thinning the Si active layer of an SOI wafer.
(Japanese Patent Laid-Open No. 5-16)
0074, JP-A-5-190499, JP-A-9-252
100 etc.).

More specifically, the thickness unevenness of the surface obtained by the conventional grinding and polishing method is obtained by utilizing interference fringes of visible light.
Since high-speed measurement is possible by combination with a two-dimensional CCD, the SOI
The thickness distribution of the active layer is input to a computer, and according to the size of the thickness unevenness, for example, the moving speed of the wafer is adjusted with respect to the head nozzle in which the plasma is confined in a low vacuum, and the diameter of the head nozzle Is appropriately selected from the precision and productivity. Conversely, the head nozzle can be moved on the wafer.

[0009]

The plasma etching by PACE increases and increases the COP existing in CZ silicon as the etching amount increases.
There is a problem similar to the state where the so-called SC1 cleaning is repeatedly performed.

As shown in FIG. 2, the PACE plasma etching conditions are as follows: a high frequency power supply 5 is connected to the head nozzle 1 via a matching box 4;
The stage 3 on which is mounted is grounded 9, and high-frequency power is applied to the head nozzle 1, and radical etching is dominant in isotropic etching.

Regarding the PACE etching conditions, Japanese Patent Application Laid-Open No. 6-5571 proposes a method for realizing isotropic etching and anisotropic etching conditions by defining the ratio of gas pressure to RF power density. Under the conditions, it is stated that the shape of the protrusion can be reduced with etching.

In Japanese Patent Application Laid-Open No. 6-5571, it is preferable that the stage on which the wafer is placed is grounded. However, an appropriate device configuration for realizing both etching conditions is shown. Absent.
Further, the effect is not shown for a depression such as COP.

According to the present invention, the local plasma etching (P
In ACE), a wafer flattening method that solves the problem of expanding and increasing the COP existing in CZ silicon when the etching amount increases, and that can improve the thinning of SOI wafers and the technology of flattening silicon wafers. The purpose is to provide the device.

[0014]

Means for Solving the Problems The inventors of the present invention have applied a high-frequency power application condition for the purpose of converting isotropic etching in which radical etching is dominant in PACE into anisotropic etching in which ion etching is dominant. As a result of various studies, the conventional isotropic etching can be made anisotropic etching by grounding the nozzle and applying high-frequency power to the stage through a blocking capacitor. The present inventors have found that flattening the wafer at a low pressure (10 ^{−3 to 1} Torr) at which the reactive etching is dominant provides an effect of improving the flatness, and completed the present invention.

Further, the present inventors have made it possible to relatively move a head for generating local plasma by introducing a reaction gas into the inside thereof and a stage on which a wafer is mounted, so that the surface of the wafer can be moved by the local plasma from the head. In a wafer flattening apparatus for obtaining a required wafer flatness by etching, a high-frequency power can be applied to a stage via a blocking capacitor, and the wafer is characterized in that it is configured to be grounded on a nozzle side. A flattening device is proposed.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION
The wafer is flattened by performing anisotropic plasma etching. As shown in FIG. 1, a high frequency power supply 5 is connected to a stage 3 on which a wafer 2 is mounted via a blocking capacitor 6 as shown in FIG. Connect and ground 7
The head nozzle 1 has a cathode coupling configuration grounded 8 via a matching box 4.

With this configuration, the stage 3 on which the wafer 2 is placed is charged negatively by accumulating electrons in the plasma. This negative voltage is called a self-bias, and its magnitude is determined by the surface area of the stage 3 where the plasma is generated and the surface area of the nozzle 1 which is the counter electrode.

Therefore, the self-bias increases as the surface area decreases. Naturally, the larger the self bias is, the more the anisotropic etching becomes dominant. Anisotropic etching is
This can be realized by the fact that the longitudinal etching by ions accelerated by the self-bias becomes dominant. In the conventional configuration, since the stage is grounded and the stage is not negatively charged, anisotropic etching is not realized.

The lower the pressure during the etching, the longer the mean free path of the ion species contributing to the etching and the smaller the loss of ion energy due to collision, so that the anisotropic etching becomes dominant. Therefore, 10
A low pressure of ^{-3 to 1} Torr is a desirable condition, and a high plasma density at a low pressure is most desirable.

[0020]

EXAMPLES Using the apparatus consists of a conventional anode coupling shown in FIG. 2, a method of planarizing a wafer by PACE, against 8 inches wafer, the etching gas SF _6, a reaction chamber pressure 2～3Torr, High frequency power 30
９０90 W, 30-45 min, Si layer 2-3
μm etching was performed.

After the etching, when the LPD of 0.2 μm or more was measured, 200 to 300 LPDs were observed on an 8-inch wafer. When observing the shape with AFM,
It was found that all particles having a size of 0.7 μm or less were pits and not particles. That is, under the conventional conditions, since the etching is isotropic, the COP is increased and expanded.

On the other hand, a PACE wafer flattening apparatus according to the present invention having the cathode coupling configuration shown in FIG. 1 and applying a high-frequency power to the stage via a blocking capacitor is used for an 8-inch wafer. , Reaction chamber pressure 0.5-1 Torr, high frequency power 30
実 施 90 W, 45 to 60 minutes, Si layer 2-3
μm etching was performed.

After the etching, LPDs having a size of 0.2 μm or more were measured. The number of LPDs was 100 or less. As a result of shape observation by AFM, pits having a size of 0.4 μm or less were found to be pits. Therefore, the flattening of the wafer by the PACE of the present invention can suppress the increase and expansion of the COP existing in the silicon wafer.

[0024]

According to the present invention, anisotropic etching in which ion etching is dominant is realized by using isotropic etching in which radical etching is dominant in conventional PACE and cathode coupling in the apparatus. Therefore, the technology for thinning the SOI wafer and flattening the silicon wafer can be improved without increasing or increasing the COP.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing the configuration of a wafer flattening apparatus according to the present invention.

FIG. 2 is an explanatory view showing a configuration of a conventional wafer flattening apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Head nozzle 2 Wafer 3 Stage 4 Matching box 5 High frequency power supply 6 Blocking capacitor 7, 8, 9 Grounding

Claims (3)

[Claims] In a wafer flattening method for obtaining a required wafer flatness by etching a wafer surface moving relative to a head nozzle with plasma generated by introducing a reaction gas into a nozzle, a nozzle portion is provided. A flattening method for performing anisotropic etching by applying high-frequency power to a stage on which a wafer is mounted via a blocking capacitor, and performing anisotropic etching. 2. The method according to claim 1, wherein the pressure during the etching is low (10 ^{−3 to 1} Torr). 3. A head that introduces a reaction gas into the interior to generate local plasma and a stage on which a wafer is mounted can be relatively moved, and the surface of the wafer is etched by local plasma from the head to obtain a required surface. A flattening apparatus for a wafer which obtains flatness of the wafer, wherein high-frequency power can be applied to a stage via a blocking capacitor and a nozzle portion is grounded.