JP2000196048A - Manufacture of soi wafer - Google Patents
Manufacture of soi waferInfo
- Publication number
- JP2000196048A JP2000196048A JP11353608A JP35360899A JP2000196048A JP 2000196048 A JP2000196048 A JP 2000196048A JP 11353608 A JP11353608 A JP 11353608A JP 35360899 A JP35360899 A JP 35360899A JP 2000196048 A JP2000196048 A JP 2000196048A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- oxide film
- soi wafer
- layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＳＯＩ(Silicon-O
n-Insulator)ウェーハの製造方法に関し、特に半導体層
の厚さの均一度を向上させることができるＳＯＩウェー
ハの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI (Silicon-O
More particularly, the present invention relates to a method for manufacturing an SOI wafer capable of improving the uniformity of the thickness of a semiconductor layer.
【０００２】[0002]
【従来の技術】近年、半導体素子の高集積化及び高性能
化に伴い、バルクシリコンからなる単結晶シリコンウェ
ーハの代わりに、ＳＯＩウェーハを用いた半導体集積技
術が注目されている。これは、ＳＯＩウェーハに集積さ
れた半導体素子が、通常の単結晶シリコンウェーハに集
積された半導体素子と比較して、接合容量(Junction Ca
pacitance)の減少による高速化、しきい電圧(Threshold
Voltage)の減少による低電圧化、及び完全な素子分離
によるラッチ-アップ(Latch-Up)の減少などの利点を持
つためである。2. Description of the Related Art In recent years, as semiconductor devices become more highly integrated and higher in performance, semiconductor integrated technologies using SOI wafers instead of single-crystal silicon wafers made of bulk silicon have attracted attention. This is because a semiconductor device integrated on an SOI wafer has a larger junction capacitance (Junction Ca) than a semiconductor device integrated on a normal single crystal silicon wafer.
pacitance), threshold voltage (Threshold
This is because there are advantages such as lowering of voltage due to reduction of voltage, and reduction of latch-up due to complete element isolation.
【０００３】前述したＳＯＩウェーハは、支持手段のベ
ース基板と、前記ベース基板上に配置されてボンディン
グ媒介体としての機能を行う埋め込み酸化膜と、前記埋
め込み酸化膜上に配置されて活性領域を提供する半導体
層との積層構造からなる。前記ＳＯＩウェーハを製造す
る為に、従来はＳＩＭＯＸ(seperation by implantedox
ygen)法及びボンディング法が利用されている。The SOI wafer described above provides a base substrate for supporting means, a buried oxide film disposed on the base substrate to function as a bonding medium, and an active region provided on the buried oxide film. It has a laminated structure with a semiconductor layer to be formed. Conventionally, in order to manufacture the SOI wafer, SIMOX (seperation by implantedox)
ygen) method and bonding method are used.
【０００４】ＳＩＭＯＸ法は、シリコンウェーハ内に酸
素イオンを注入し、次に、酸素イオンとシリコンが反応
するように熱処理を行うことにより、前記シリコンウェ
ーハの表面から所定深さに前記シリコンウェーハをベー
ス基板と半導体層に分離させる埋め込み酸化膜を形成す
る。その結果、ベース基板、埋め込み酸化膜、及び半導
体層の積層構造からなるＳＯＩウェーハが得られる。ボ
ンディング法は、二枚のシリコン基板、例えばベース基
板と半導体基板を、前記基板の何れか一つに形成された
埋め込み酸化膜の介在下でボンディングし、次に、前記
半導体基板の一部厚さを研磨工程にて除去して素子が形
成される半導体層が得られ、その結果、ベース基板、埋
め込み酸化膜、及び半導体層の積層構造からなるＳＯＩ
ウェーハが得られる。In the SIMOX method, oxygen ions are implanted into a silicon wafer, and then heat treatment is performed so that the oxygen ions react with the silicon, so that the silicon wafer is formed at a predetermined depth from the surface of the silicon wafer. A buried oxide film to be separated into a substrate and a semiconductor layer is formed. As a result, an SOI wafer having a laminated structure of the base substrate, the buried oxide film, and the semiconductor layer is obtained. In the bonding method, two silicon substrates, for example, a base substrate and a semiconductor substrate are bonded together with a buried oxide film formed on any one of the substrates interposed therebetween. Is removed by a polishing process to obtain a semiconductor layer on which an element is formed. As a result, an SOI having a stacked structure of a base substrate, a buried oxide film, and a semiconductor layer is obtained.
A wafer is obtained.
【０００５】ところが、ＳＩＭＯＸ法はイオン注入によ
って形成されるため、半導体層の厚さを調節するのが難
しく、かつ、工程時間が長いという欠点があるために、
最近はボンディング法が主に用いられている。However, since the SIMOX method is formed by ion implantation, it is difficult to adjust the thickness of the semiconductor layer and the process time is long.
Recently, the bonding method has been mainly used.
【０００６】図１乃至図４はボンディング法を用いた従
来技術によるＳＯＩウェーハの製造方法を説明するため
の工程断面図である。図１を参照すれば、ベース基板１
を備え、熱酸化工程あるいは化学気相蒸着(Chemical Va
por Deposition：以下、ＣＶＤ)工程による酸化膜２を
前記ベース基板１上に形成する。FIGS. 1 to 4 are process sectional views for explaining a conventional method of manufacturing an SOI wafer using a bonding method. Referring to FIG. 1, a base substrate 1
With thermal oxidation process or chemical vapor deposition (Chemical Vapor Deposition).
An oxide film 2 is formed on the base substrate 1 by a por deposition (CVD) process.
【０００７】図２を参照すれば、バルクシリコンからな
る半導体基板３を備え、ホウ素イオン層４を、前記半導
体基板３内に公知のイオン注入法によるホウ素イオンの
注入により、前記半導体基板３の一側面から所定深さに
形成する。ここで、前記ホウ素イオン層４は後続工程で
エッチング停止層として用い、特に素子が形成される半
導体層の厚さの均一度が確保される機能を行う。Referring to FIG. 2, a semiconductor substrate 3 made of bulk silicon is provided, and a boron ion layer 4 is formed in the semiconductor substrate 3 by implanting boron ions by a known ion implantation method. It is formed to a predetermined depth from the side. Here, the boron ion layer 4 is used as an etching stop layer in a subsequent process, and particularly, performs a function of ensuring uniformity of the thickness of a semiconductor layer on which an element is formed.
【０００８】図３を参照すれば、ベース基板１と半導体
基板３は、前記ベース基板１上に形成された酸化膜２と
前記半導体基板３の一側面がコンタクトされるようにボ
ンディングされ、次に、それら間のボンディング強度が
増大するように熱処理される。続いて、前記半導体基板
３の他側面はホウ素イオン層４に隣接した部分まで研削
され、次に、研削された半導体基板３の他側面は前記ホ
ウ素イオン層４が露出するまでエッチングされる。前記
ホウ素イオン層４は、前述したように、エッチング停止
層としての機能を行い、前記ホウ素イオン層４によって
研削及びエッチング工程を行った半導体基板３における
厚さの均一度が確保される。Referring to FIG. 3, a base substrate 1 and a semiconductor substrate 3 are bonded so that an oxide film 2 formed on the base substrate 1 and one side of the semiconductor substrate 3 are in contact with each other. Then, heat treatment is performed to increase the bonding strength between them. Subsequently, the other side of the semiconductor substrate 3 is ground to a portion adjacent to the boron ion layer 4, and then the other side of the ground semiconductor substrate 3 is etched until the boron ion layer 4 is exposed. As described above, the boron ion layer 4 functions as an etching stop layer, and the boron ion layer 4 ensures uniformity of the thickness of the semiconductor substrate 3 that has been subjected to the grinding and etching processes.
【０００９】図４を参照すれば、ホウ素イオン層４を含
んだ前記半導体基板３は、所定厚さの半導体層３ａが得
られるように、化学機械研磨(Chemical Mechanical Pol
ishing：以下、ＣＭＰ)工程により研磨され、その結
果、ベース基板１、埋め込み酸化膜としての機能を行う
酸化膜２、及び半導体層３ａの積層構造からなるＳＯＩ
ウェーハ１０が製造される。Referring to FIG. 4, the semiconductor substrate 3 including the boron ion layer 4 is subjected to chemical mechanical polishing (Chemical Mechanical Polishing) so that a semiconductor layer 3a having a predetermined thickness is obtained.
ishing: hereinafter, polished by a CMP) process. As a result, an SOI having a laminated structure of a base substrate 1, an oxide film 2 serving as a buried oxide film, and a semiconductor layer 3a
A wafer 10 is manufactured.
【００１０】[0010]
【発明が解決しようとする課題】前記ＳＯＩウェーハに
おいて、半導体層は素子の形成される活性領域を提供す
るため、その厚さの均一度が確保されるべきである。と
ころが、従来の方法では、前記半導体層の厚さの均一度
はある程度確保されたが、それでも限界があり、かつＣ
ＭＰ工程により前記半導体層の表面にスクラッチ(Scrat
ch)が発生するため、前記半導体層の厚さの均一度が低
減するという問題点がある。In the SOI wafer, since the semiconductor layer provides an active region in which a device is formed, uniformity of its thickness should be ensured. However, in the conventional method, the uniformity of the thickness of the semiconductor layer is ensured to some extent, but there is still a limit and C
The surface of the semiconductor layer is scratched by an MP process.
ch) occurs, and thus the uniformity of the thickness of the semiconductor layer is reduced.
【００１１】本発明の目的は、ＣＭＰ工程の代りに酸化
工程とウェットエッチング工程を用いることにより、半
導体層の厚さの均一度を一層向上できるＳＯＩウェーハ
の製造方法を提供することにある。An object of the present invention is to provide a method of manufacturing an SOI wafer which can further improve the uniformity of the thickness of a semiconductor layer by using an oxidation step and a wet etching step instead of the CMP step.
【００１２】[0012]
【課題を解決するための手段】前記目的を達成するため
に、本発明は、ベース基板及び半導体基板を提供する段
階；前記ベース基板上に絶縁膜を形成する段階；前記半
導体基板内にその一側面より所定深さにホウ素イオン層
を形成する段階；前記絶縁膜と半導体基板の一側面がコ
ンタクトされるように、前記ベース基板と半導体基板を
ボンディングする段階；前記半導体基板の他側面を前記
ホウ素イオン層に隣接した部分まで研削する段階；前記
ホウ素イオン層が露出するように、研磨された半導体基
板の他側面をエッチングする段階；前記ホウ素イオン層
を含めた半導体基板の一部を熱酸化させて酸化膜を形成
する段階；及び前記酸化膜をエッチングして半導体層を
形成する段階を含むことを特徴とする。To achieve the above object, the present invention provides a base substrate and a semiconductor substrate; a step of forming an insulating film on the base substrate; Forming a boron ion layer at a predetermined depth from a side surface; bonding the base substrate and the semiconductor substrate so that the insulating film contacts one side surface of the semiconductor substrate; Grinding the portion adjacent to the ion layer; etching the other side of the polished semiconductor substrate so that the boron ion layer is exposed; thermally oxidizing a part of the semiconductor substrate including the boron ion layer; Forming an oxide film by etching; and etching the oxide film to form a semiconductor layer.
【００１３】本発明及びその実施の形態は、以下の説明
及び図面を参照することによって理解できる。The present invention and its embodiments can be understood by referring to the following description and drawings.
【００１４】[0014]
【発明の実施の形態】以下、添付図面に基づき、本発明
の好適実施例を詳細に説明する。図５乃至図１０は本発
明の実施例によるＳＯＩウェーハの製造方法を説明する
ための工程断面図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. 5 to 10 are cross-sectional views illustrating a method of manufacturing an SOI wafer according to an embodiment of the present invention.
【００１５】図５を参照すれば、ベース基板１１を備
え、ＳＯＩウェーハで埋め込み酸化膜として機能を行う
酸化膜１２が前記ベース基板１１の一側面を熱酸化させ
ることにより、１，０００〜２０，０００Å厚さで形成
される。前記酸化膜１２は熱酸化工程の代りにＢＰＳＧ
膜、ＳＯＧ膜、Ｏ3-ＴＥＯＳ酸化膜、高密度プラズマ酸
化膜から選択される一つのＣＶＤ酸化膜を蒸着して形成
してもよい。Referring to FIG. 5, an oxide film 12 having a base substrate 11 and functioning as a buried oxide film on an SOI wafer is formed by thermally oxidizing one side surface of the base substrate 11 so as to have a thickness of 1,000 to 20,000. It is formed with a thickness of 000 mm. The oxide film 12 is BPSG instead of a thermal oxidation process.
One CVD oxide film selected from a film, an SOG film, an O 3 -TEOS oxide film, and a high-density plasma oxide film may be formed by vapor deposition.
【００１６】図６を参照すれば、バルクシリコンからな
る半導体基板２１を備え、前記半導体基板２１内にホウ
素イオンを注入してから熱処理させることで、前記半導
体基板２１の一側面から所定深さにホウ素イオン層２２
を形成する。前記ホウ素イオンは５０〜５００ｋｅＶの
エネルギーと１．０×１０15〜３．０×１０16ドーズ/
ｃｍ2でイオン注入する。Referring to FIG. 6, a semiconductor substrate 21 made of bulk silicon is provided. Boron ions are implanted into the semiconductor substrate 21 and then heat-treated to a predetermined depth from one side surface of the semiconductor substrate 21. Boron ion layer 22
To form The boron ions have an energy of 50 to 500 keV and a dose of 1.0 × 10 15 to 3.0 × 10 16 dose /
Ions are implanted in cm 2 .
【００１７】図７を参照すれば、ベース基板１１と半導
体基板２１は、各基板１１、２１のボンディング面に存
在するパーティクル(particle)が除去され、かつ、前記
ボンディング面が親水性を持つように、ＮＨ4ＯＨ：Ｈ2
Ｏ2 ：Ｈ2 Ｏが１：４：２０の体積比で混合された第１
溶液、またはＨ2ＳＯ4：Ｈ2 Ｏが４：１の体積比で混合
された第２溶液から選択される一つの溶液により洗浄さ
れたり、あるいは第１溶液と第２溶液により順次洗浄さ
れる。続いて、ベース基板１１と半導体基板２１は、前
記ベース基板１１上に形成された酸化膜１２と前記半導
体基板２１の一側面がコンタクトされるように、７．５
×１０-1〜７．５×１０-4Ｔｏｒｒの真空下でボンディ
ングされ、次に、ボンディングされたベース基板１１と
半導体基板２１は、それら間のボンディング強度が増大
するように、窒素(Ｎ2)又は酸素(Ｏ2)雰囲気下で７００
〜１，２００℃で３０〜１２０分の間に熱処理される。Referring to FIG. 7, the base substrate 11 and the semiconductor substrate 21 are formed such that particles existing on the bonding surfaces of the substrates 11 and 21 are removed and the bonding surfaces are hydrophilic. , NH 4 OH: H 2
A first mixture of O 2 : H 2 O in a volume ratio of 1: 4: 20.
The solution is washed with one solution selected from a solution or a second solution in which H 2 SO 4 : H 2 O is mixed at a volume ratio of 4: 1, or is washed sequentially with the first solution and the second solution. . Subsequently, the base substrate 11 and the semiconductor substrate 21 are connected to each other so that the oxide film 12 formed on the base substrate 11 is in contact with one side surface of the semiconductor substrate 21.
The base substrate 11 and the semiconductor substrate 21 which have been bonded under a vacuum of × 10 -1 to 7.5 × 10 -4 Torr are bonded with nitrogen (N 2) so that the bonding strength between them is increased. ) Or oxygen (O 2 ) atmosphere
Heat treated at ~ 1200C for 30-120 minutes.
【００１８】図８を参照すれば、半導体基板２１の他側
面は、ホウ素イオン層２２に隣接した部分まで研削さ
れ、次に、研削された半導体基板２１の他側面は前記ホ
ウ素イオン層２２が露出するように、前記ホウ素イオン
層２２をエッチング停止層とするウェットエッチング工
程によりエッチングされる。ここで、前記ウェットエッ
チング工程はＮＨ4ＯＨ：Ｈ2Ｏ2 ：Ｈ2 Ｏが１〜２：
０．０１〜０．０２：１〜５の体積比で混合された溶液
で行う。また、ＮＨ4ＯＨ溶液の代りにＫＯＨ溶液を用
いる事も出来る。Referring to FIG. 8, the other side of the semiconductor substrate 21 is ground to a portion adjacent to the boron ion layer 22, and then the other side of the ground semiconductor substrate 21 is exposed to the boron ion layer 22. Thus, the etching is performed by a wet etching process using the boron ion layer 22 as an etching stop layer. Here, the wet etching process is NH 4 OH: H 2 O 2 : H 2 O is 1 to 2:
It is performed with a solution mixed at a volume ratio of 0.01 to 0.02: 1 to 5. Also, a KOH solution can be used instead of the NH 4 OH solution.
【００１９】図９を参照すれば、ホウ素イオン層を含め
た半導体基板２１の一部は水素及び酸素雰囲気下で８０
０〜９５０℃で所定時間の間に熱酸化されることで、熱
酸化膜３０が形成される。前記熱酸化工程は半導体基板
の残存部分が後続工程で形成される半導体層と同じ厚さ
となるまで行われる。Referring to FIG. 9, a part of the semiconductor substrate 21 including the boron ion layer is exposed to hydrogen under an atmosphere of hydrogen and oxygen.
The thermal oxide film 30 is formed by being thermally oxidized at a temperature of 0 to 950 ° C. for a predetermined time. The thermal oxidation process is performed until the remaining portion of the semiconductor substrate has the same thickness as a semiconductor layer formed in a subsequent process.
【００２０】図１０を参照すれば、熱酸化膜はフッ酸
(ＨＦ)溶液を用いたウェットエッチング工程により除去
され、その結果、ベース基板１１、埋め込み酸化膜とし
て機能を行う酸化膜１２、及び半導体層２１ａの積層構
造からなるＳＯＩウェーハ４０が製造される。ここで、
前記半導体層２１ａは向上された厚さの均一度を持つ。
詳しくは、熱酸化膜は、通常均一な厚さで形成されるた
め、前記熱酸化膜を除いた残りの半導体基板部分の厚さ
は均一になる。よって、熱酸化膜の除去により得られる
半導体層２１ａの厚さの均一度はＣＭＰ工程により得ら
れるそれと比較して向上し、かつ前記半導体層の表面に
スクラッチが発生することも防止する。従って、前記半
導体層２１ａは滑らかな表面を持つことになり、厚さの
均一度は一層向上する。Referring to FIG. 10, the thermal oxide film is made of hydrofluoric acid.
An SOI wafer 40 having a stacked structure of the base substrate 11, the oxide film 12 functioning as a buried oxide film, and the semiconductor layer 21a is manufactured by the wet etching process using the (HF) solution. here,
The semiconductor layer 21a has improved thickness uniformity.
More specifically, since the thermal oxide film is usually formed with a uniform thickness, the thickness of the remaining semiconductor substrate portion excluding the thermal oxide film becomes uniform. Therefore, the uniformity of the thickness of the semiconductor layer 21a obtained by removing the thermal oxide film is improved as compared with that obtained by the CMP process, and the generation of scratches on the surface of the semiconductor layer is also prevented. Therefore, the semiconductor layer 21a has a smooth surface, and the uniformity of the thickness is further improved.
【００２１】続いて、ＳＯＩウェーハ４０は、前記半導
体層２１ａの表面及びその内部に残っているホウ素イオ
ンを除去させ、そして、前述したエッチング工程時に発
生し得る結晶欠陥を回復するため、水素雰囲気下で６０
０〜１，２００℃で３０〜１２０分の間に熱処理され
る。Subsequently, the SOI wafer 40 is removed under a hydrogen atmosphere in order to remove boron ions remaining on the surface of the semiconductor layer 21a and the inside thereof and to recover crystal defects that may be generated during the above-described etching process. At 60
Heat treatment is performed at 0 to 1200C for 30 to 120 minutes.
【００２２】尚、本発明は本実施例に限られるものでは
ない。本発明の趣旨から逸脱しない範囲内で多様に変更
実施することが可能である。The present invention is not limited to this embodiment. Various modifications can be made without departing from the spirit of the present invention.
【００２３】[0023]
【発明の効果】以上のように、半導体層はＣＭＰ工程の
代りに熱酸化工程とウェットエッチング工程によって得
られるため、前記半導体層の厚さの均一度が向上する。
また、表面スクラッチによる半導体層の不均一度も改善
される。従って、ＳＯＩウェーハの信頼性は勿論、向上
された厚さの均一度を持つ半導体層に形成された半導体
素子の信頼性も向上する。As described above, since the semiconductor layer is obtained by the thermal oxidation process and the wet etching process instead of the CMP process, the uniformity of the thickness of the semiconductor layer is improved.
Further, the non-uniformity of the semiconductor layer due to surface scratches is also improved. Therefore, not only the reliability of the SOI wafer but also the reliability of the semiconductor device formed on the semiconductor layer having the improved thickness uniformity are improved.
【図１】従来におけるＳＯＩウェーハの製造方法を説明
するための工程断面図である。FIG. 1 is a process cross-sectional view for explaining a conventional SOI wafer manufacturing method.
【図２】従来におけるＳＯＩウェーハの製造方法を説明
するための工程断面図である。FIG. 2 is a process cross-sectional view for explaining a conventional SOI wafer manufacturing method.
【図３】従来におけるＳＯＩウェーハの製造方法を説明
するための工程断面図である。FIG. 3 is a process cross-sectional view for describing a conventional method for manufacturing an SOI wafer.
【図４】従来におけるＳＯＩウェーハの製造方法を説明
するための工程断面図である。FIG. 4 is a process cross-sectional view for explaining a conventional SOI wafer manufacturing method.
【図５】本発明の実施例によるＳＯＩウェーハの製造方
法を説明するための工程断面図である。FIG. 5 is a process sectional view illustrating a method of manufacturing an SOI wafer according to an embodiment of the present invention.
【図６】本発明の実施例によるＳＯＩウェーハの製造方
法を説明するための工程断面図である。FIG. 6 is a process sectional view illustrating a method for manufacturing an SOI wafer according to an embodiment of the present invention.
【図７】本発明の実施例によるＳＯＩウェーハの製造方
法を説明するための工程断面図である。FIG. 7 is a process sectional view illustrating a method of manufacturing an SOI wafer according to an embodiment of the present invention.
【図８】本発明の実施例によるＳＯＩウェーハの製造方
法を説明するための工程断面図である。FIG. 8 is a process sectional view illustrating a method of manufacturing an SOI wafer according to an embodiment of the present invention.
【図９】本発明の実施例によるＳＯＩウェーハの製造方
法を説明するための工程断面図である。FIG. 9 is a process cross-sectional view illustrating a method of manufacturing an SOI wafer according to an embodiment of the present invention.
【図１０】本発明の実施例によるＳＯＩウェーハの製造
方法を説明するための工程断面図である。FIG. 10 is a cross-sectional view illustrating a method of manufacturing an SOI wafer according to an embodiment of the present invention.
１１ ベース基板 １２ 酸化膜 ２１ 半導体基板 ２１ａ 半導体層 ２２ ホウ素イオン層 ３０ 熱酸化膜 ４０ ＳＯＩウェーハ DESCRIPTION OF SYMBOLS 11 Base substrate 12 Oxide film 21 Semiconductor substrate 21a Semiconductor layer 22 Boron ion layer 30 Thermal oxide film 40 SOI wafer
Claims (7)
階；前記ベース基板上に絶縁膜を形成する段階；前記半
導体基板内に、その一側面より所定深さにホウ素イオン
層を形成する段階；前記絶縁膜と半導体基板の一側面が
コンタクトされるように、前記ベース基板と半導体基板
をボンディングする段階；前記半導体基板の他側面を前
記ホウ素イオン層に隣接した部分まで研削する段階；前
記ホウ素イオン層が露出するように、研磨された半導体
基板の他側面をエッチングする段階；前記ホウ素イオン
層を含めた半導体基板の一部を熱酸化させて酸化膜を形
成する段階；及び、前記酸化膜をエッチングして半導体
層を形成する段階を含むことを特徴とするＳＯＩウェー
ハの製造方法。Providing a base substrate and a semiconductor substrate; forming an insulating layer on the base substrate; forming a boron ion layer in the semiconductor substrate at a predetermined depth from one side thereof; Bonding the base substrate and the semiconductor substrate such that an insulating film is in contact with one side surface of the semiconductor substrate; grinding the other side surface of the semiconductor substrate to a portion adjacent to the boron ion layer; Etching the other side of the polished semiconductor substrate so that the oxide film is exposed; thermally oxidizing a part of the semiconductor substrate including the boron ion layer to form an oxide film; and etching the oxide film. Forming a semiconductor layer by forming the SOI wafer.
エッチングは、 ＮＨ4 ＯＨ：Ｈ2 Ｏ2 ：Ｈ2Ｏが１〜２：０．０１〜
０．０２：１〜５の体積比で混合された溶液で行うこと
を特徴とする請求項１記載のＳＯＩウェーハの製造方
法。2. The etching for exposing the boron ion layer is performed using NH 4 OH: H 2 O 2 : H 2 O of 1-2: 0.01-
2. The method for manufacturing an SOI wafer according to claim 1, wherein the method is performed with a solution mixed at a volume ratio of 0.02: 1 to 5.
エッチングは、 ＫＯＨ、Ｈ2 Ｏ2 及びＨ2 Ｏの混合溶液で行うことを特
徴とする請求項２記載のＳＯＩウェーハの製造方法。3. The method as claimed in claim 2, wherein the etching for exposing the boron ion layer is performed using a mixed solution of KOH, H 2 O 2 and H 2 O.
特徴とする請求項１記載のＳＯＩウェーハの製造方法。4. The method according to claim 1, wherein the thermal oxidation for forming the oxide film is performed at 800 to 950 ° C. in an atmosphere of hydrogen and oxygen.
徴とする請求項１記載のＳＯＩウェーハの製造方法。5. The method according to claim 1, wherein the etching of the oxide film is performed by wet etching using a hydrofluoric acid solution.
処理を行う段階をさらに含むことを特徴とする請求項１
記載のＳＯＩウェーハの製造方法。6. The method of claim 1, further comprising performing a heat treatment after the step of etching the oxide film.
The manufacturing method of the SOI wafer described in the above.
１,２００℃で３０〜１２０分の間に行うことを特徴と
する請求項６記載のＳＯＩウェーハの製造方法。7. The heat treatment is performed in a hydrogen atmosphere at 600 to
7. The method for manufacturing an SOI wafer according to claim 6, wherein the method is performed at 1,200 [deg.] C. for 30 to 120 minutes.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1998/P57983 | 1998-12-24 | ||
| KR1019980057983A KR100291515B1 (en) | 1998-12-24 | 1998-12-24 | Method for manufacturing silicon on insulator wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000196048A true JP2000196048A (en) | 2000-07-14 |
Family
ID=19565199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11353608A Pending JP2000196048A (en) | 1998-12-24 | 1999-12-13 | Manufacture of soi wafer |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2000196048A (en) |
| KR (1) | KR100291515B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003068996A (en) * | 2001-08-22 | 2003-03-07 | Sumitomo Mitsubishi Silicon Corp | Method for manufacturing laminated silicon substrate |
| US20140008604A1 (en) * | 2011-03-17 | 2014-01-09 | Fudan University | Super-Long Semiconductor Nano-Wire Structure and Method of Making |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8268705B2 (en) * | 2006-04-24 | 2012-09-18 | Shin-Etsu Handotai Co., Ltd. | Method for producing SOI wafer |
| KR100952250B1 (en) * | 2007-12-26 | 2010-04-09 | 주식회사 동부하이텍 | Method for manufacturing silicon wafer |
-
1998
- 1998-12-24 KR KR1019980057983A patent/KR100291515B1/en not_active IP Right Cessation
-
1999
- 1999-12-13 JP JP11353608A patent/JP2000196048A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003068996A (en) * | 2001-08-22 | 2003-03-07 | Sumitomo Mitsubishi Silicon Corp | Method for manufacturing laminated silicon substrate |
| US20140008604A1 (en) * | 2011-03-17 | 2014-01-09 | Fudan University | Super-Long Semiconductor Nano-Wire Structure and Method of Making |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100291515B1 (en) | 2001-06-01 |
| KR20000041954A (en) | 2000-07-15 |
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