JPH0870111A - Semiconductor substrate and its production - Google Patents

Abstract

PURPOSE: To obtain a semiconductor substrate in which the lamination defect is suppressed in the epitaxial layer, the surface of the epitaxial layer is planarized sufficiently, the generation of void is suppressed after sticking, and the deterioration of quality is prevented in high temperature process, along with a method for producing the substrate with high productivity and good film thickness distribution. CONSTITUTION: The method for producing a semiconductor substrate comprises a step for making porous 102 a single crystal substrate 101, a step for causing a first epitaxial growth 103 on the porous substrate by feeding deposition atoms while controlling the temperature of the substrate and irradiating the substrate with tons having controlled energy, a step for causing a second epitaxial growth 104 by CVD, a step for sticking the substrate to a second substrate 105, and a step for removing the part including the porous layer but excluding the epitaxial film from the substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate and the manufactured semiconductor substrate. More specifically, the present invention relates to an electronic device or an integrated circuit manufactured by dielectric isolation or a single crystal semiconductor layer on an insulator. The present invention relates to a method for manufacturing a semiconductor substrate suitable for.

[0002]

2. Description of the Related Art The formation of a single crystal Si semiconductor layer on an insulator is widely known as a silicon-on-insulator (SOI) technique, and has many advantages that cannot be reached by a bulk Si substrate for producing an ordinary Si integrated circuit. Much research has been done because the devices using the SOI technology have. That is, by using SOI technology, 1. 1. Dielectric isolation is easy and high integration is possible. 2. It has excellent radiation resistance. 3. Stray capacitance is reduced and high speed is possible. 4. The well process can be omitted, Latch-up can be prevented, 6. It is possible to obtain a complete depletion type field effect transistor by thinning the film.

In order to realize the many advantages in device characteristics as described above, a method for forming an SOI structure has been researched for several decades. The contents are summarized in the following documents, for example. Special
Issue: “Single-crystal sil
icon on non-single-crysta
l insulators ”; edited by
G. W. Cullen, Journal of Cry
stal Growth, volume 63, no
3, pp 429-590 (1983).

SOS (silicon on sapphire), which is formed by heteroepitaxially forming Si on a single crystal sapphire substrate by CVD (chemical vapor deposition), has been known for a long time, and has been successful as the most mature SOI technology. However, due to lattice mismatch between the Si layer and the underlying sapphire substrate interface, a large amount of crystal defects, aluminum from the sapphire substrate was mixed into the Si layer, and above all, the cost of the substrate and the delay in increasing the area Has hindered its widespread application.

Further, the single crystal layer Si is directly formed by the CVD method.
Lateral epitaxial growth, amorphous Si deposition, and solid phase lateral epitaxial growth by heat treatment, electron beam on the amorphous or polycrystalline Si layer,
A method of growing a single crystal layer on SiO ₂ by fusion recrystallization by converging and irradiating an energy beam such as a laser beam, and a method of scanning a fusion zone in a band shape with a rod heater (Zone melting recrystal).
is known. Each of these methods has advantages and disadvantages, but their controllability, productivity,
There are still many problems in uniformity and quality, and none have been industrially put to practical use. For example, the CVD method requires sacrificial oxidation to achieve a flat thin film, and the solid phase growth method has poor crystallinity. In the beam annealing method,
There are problems in the processing time by convergent beam scanning, the degree of beam overlap, and the controllability such as focus adjustment. Of these, Z
oneMelting Recrystallizat
The ion method is the most mature, and relatively large-scale integrated circuits have been prototyped. However, many crystal defects such as sub-grain boundaries still remain, leading to the production of minority carrier devices. Absent.

Further, an oxide film is formed on a Si single crystal substrate in which V-shaped grooves are anisotropically etched on the surface, and a polycrystalline Si layer is deposited on the oxide film as thick as the Si substrate.
There is a method of forming a Si single crystal region surrounded by V grooves and dielectrically separated on a thick polycrystalline Si layer by polishing from the back surface of the i substrate. In this method, the crystallinity is good. There is a problem in terms of controllability and productivity in the step of depositing polycrystalline Si to a thickness of several hundreds of microns and the step of polishing the single crystal Si substrate from the back surface to leave only the separated Si active layer.

A method for forming an SOI structure by dielectric isolation by oxidation of porous Si (FIPOS: Full I)
solation by Porous Oxidiz
edSilicon) is N-type on the surface of P-type Si single crystal substrate.
Type Si layer with proton ion implantation, (Imai et al., J. Cr
ystal Growth, vol 63, 547 (1
983)), or an island shape is formed by epitaxial growth and patterning, and only the P-type Si substrate is made porous by anodization in a HF solution so as to surround the Si island from the surface, and then N-type is formed by accelerated oxidation. This is a method of dielectrically separating Si islands. In this method, the separated Si region is determined before the device process, and there is a problem that the degree of freedom in device design may be limited, and there is a problem of stress due to the oxidation process.

CYMOX (SI), which is currently considered to be the most mature method because it has good compatibility with the Si process.
MOX: Separation by ion imp
There is a method of forming a SiO ₂ layer by ion implantation of oxygen in a Si single crystal substrate called lented oxygen). However, in order to form a SiO ₂ layer, it is necessary to implant oxygen ions at a dose of 10 ¹⁸ ions / cm ² or more, but the implantation time is long and the productivity cannot be said to be high. The cost is high. Furthermore,
Many crystal defects remain, and from an industrial viewpoint, the quality is not sufficient to produce a minority carrier device.

Recently, an SOI manufacturing method in which two substrates are directly bonded to each other and one surface of which is ground by polishing is actively used, and the crystallinity is good, but the substrate is thinned by polishing the back surface by several hundreds of microns. There is a problem in terms of controllability and productivity in the process of leaving only the Si active layer.

On the other hand, there is a method proposed as a new SOI manufacturing method. This is a method in which a substrate is made porous and then epitaxially grown, the substrate is bonded to a second substrate, and then the substrate on the porous side is removed up to the porous layer to produce an SOI structure. This method is expected to overcome the problem of thinning the Si active layer by polishing.

[0011]

However, in the epitaxial growth on the porous body, which is the main process of the above-mentioned method, a problem caused by the deposition method of the CVD method is that stacking faults are formed in the epitaxial layer on the porous body. Is easily present, and the flatness of the surface of the epitaxial layer is insufficient, so that a void is likely to be formed after the bonding.

Further, according to the CVD method, it is necessary to raise the H ₂ cleaning temperature to flatten the porous holes, which is not preferable for the deterioration of the porous layer.

On the other hand, a high-performance bias sputtering method, which is a new epitaxial growth method (Japanese Patent Laid-Open No. 03-18799)
Problems when the deposition method of 6) is used include productivity problems in terms of growth rate and CV with respect to film thickness distribution.
There are disadvantages compared to the D method.

[Object of the Invention] In the growth of an epitaxial layer on a porous semiconductor substrate, the object of the present invention is to prevent stacking faults from being present in the epitaxial layer, to ensure that the surface of the epitaxial layer is sufficiently flat. Voids are less likely to occur after bonding, there is no deterioration due to high temperature process, high productivity,
It is to provide a manufacturing method having a favorable film thickness distribution and a semiconductor substrate by the manufacturing method.

[0015]

Means and Actions for Solving the Problems In the method for manufacturing a semiconductor substrate of the present invention, as a means for solving the above problems, a step of making a single crystal substrate porous, A step of performing a first epitaxial growth by supplying deposited atoms while simultaneously irradiating ions whose energy is controlled while controlling the temperature of the substrate, and then performing a second epitaxial growth by a CVD method,
The present invention provides a method for manufacturing a semiconductor substrate, which comprises:

In the step of making the first single crystal substrate porous, the deposited atoms are supplied onto the porous substrate while controlling the temperature of the substrate and simultaneously irradiating the ions whose energy is controlled. The step of performing the first epitaxial growth, the step of performing the second epitaxial growth by the CVD method, the step of attaching the first substrate to the second substrate, and the porous layer other than the epitaxial film of the first substrate. It is also a method of manufacturing a semiconductor substrate, characterized by including a step of removing a portion including.

Further, the first epitaxial growth method is preferably a bias sputtering method, the porous single crystal is porous Si, and further, the step of making it porous is anodization. And

According to the present invention, since an epitaxial film having few stacking faults, good flatness, and good film thickness distribution can be formed on a porous layer at a relatively low temperature, it is effective for bonding and therefore high in thickness. It is possible to provide a semiconductor substrate having a high-quality SOI structure.

In particular, an important point of the present invention is that by bias sputtering or the like, the temperature of the substrate is controlled, and at the same time, the deposited atoms are supplied while irradiating the ions whose energies are controlled. A single crystal film with good flatness and few stacking faults is deposited, and then productivity is excellent,
It is to deposit by a CVD method with a small film thickness distribution, and as a result, the SOI substrate manufactured with the above configuration is a high quality film with few voids and stacking faults and with a small Si active layer film thickness distribution. The SOI substrate having excellent properties can be obtained.

[Embodiment Example] The embodiment will be described in detail below.

First, as shown in FIG. 1A, a Si single crystal substrate 101 is prepared, and the entire surface or a part thereof is made porous (102). The Si substrate 101 is made porous by an anodization method using an HF solution.

The porous Si will be briefly described. Porous Si was discovered by Uhril et al. In the course of research on electrolytic polishing of semiconductors in 1956 (A. Uhli.
r, Bell System. Tech. J. , Vol. Three
5, p. 333 (1956)). In addition, unagi etc.
The dissolution reaction of Si in the anodization is studied, and it is reported that the hole is necessary for the anodic reaction of Si in the HF solution (T. Unami: J. Electroc-hem. So.
c. , Vol. 127, p. 476 (1980)). According to observation with a transmission electron microscope, this porous Si is
Pores having an average diameter of about 600 angstroms are formed, and although the density is less than half that of single crystal Si, the single crystallinity is maintained, and CVD is performed on the upper part of the porous layer. It is also possible to grow a single crystal Si layer epitaxially by the method (Unagami
J. Electrochem. Soc. : Solid-
state science and technology
ody pp. 1339), the crystallinity of the grown single crystal film is not perfect, and crystal defects remain. When high temperature treatment or high temperature film formation is performed to improve crystallinity, porous Si
May change in quality, and the characteristics itself of the porous Si such as accelerated oxidation may change, and especially at 1000 ° C. or higher, rearrangement of internal pores may occur. That is, it is not easy to grow defect-free single crystal Si having good flatness at a low temperature, which is useful for forming FIPOS, on the porous layer, and does not change, for example, when forming an epitaxial growth layer,
It grows after passing through a layer containing many voids in an intermediate step (H. Takai et al. J. of El.
electronic Materials, 12, p. 9
73, 1983), crystal defects have been introduced as described above.

Then, while controlling the substrate temperature, the energy of the ions irradiating the substrate surface is controlled at the same time, and the Si substrate 101 is put into an apparatus capable of supplying the deposited atoms.

Here, a sputtering apparatus used in the present invention, which can control the substrate temperature and at the same time control the energy of the ions for irradiating the substrate surface to supply the deposited atoms will be described.

FIG. 2 is a schematic configuration diagram showing an example of an apparatus used for carrying out the present invention. The device is rf-d
It is a c-coupled bias sputtering device. In FIG.
91 is a vacuum chamber, 92 is a target, 93 is a permanent magnet, 94 is a base, 95 is a substrate support (electrostatic chuck),
96 is a high frequency power supply, 97 is a matching circuit, 98 is a direct current power supply for determining the direct current potential of the target, 99 is a direct current power supply for determining the direct current potential of the substrate, and 10 and 11 are low pass filters of the target and the substrate, respectively. Show.

The vacuum chamber 91 is made of SUS316,
On the inner surface of the chamber, a passivation oxide film of high-purity oxygen is formed on a mirror-polished surface having a surface smoothness of Rmax <0.1 μm, which has been subjected to electric field polishing or electric field composite polishing. The gas exhaust system, including the mass flow controller and the filter, is made of SUS316 and is subjected to electropolishing and passivation oxidation so as to minimize the amount of impurities when the gas is introduced into the chamber. The exhaust system is configured as follows. The main pump is a magnetic levitation tandem turbo molecular pump, and uses a dry pump as an auxiliary pump.
This exhaust system is an oil-free system, and the system is constructed so as to reduce contamination by impurities. The second-stage turbo molecular pump is a large-flow type pump, and the exhaust speed is maintained even when the degree of vacuum is in the order of mTorr during plasma generation. The introduction of the substrate 94 into the vacuum chamber 91 is performed through a load lock chamber (not shown) provided in contact with the chamber to prevent impurities from being mixed into the vacuum chamber 91. As a result, the amount of impurities in Ar when introduced into the chamber is several ppb or less even for the largest amount of water, which is 2E-11T as the background vacuum degree when the substrate temperature is not increased.
Orr can be achieved. In addition, the target is equipped with a variable high-frequency power supply capable of operating up to several hundred MHz, so that high-density plasma can be generated. Since a power source is connected and the potentials of the target and the substrate can be controlled, the film forming conditions such as a) film forming speed, b) energy of Ar ions with which the substrate is irradiated, and c) plasma density should be independently controlled. Is possible.

FIG. 3 shows the frequency dependence of the high frequency power applied to the target, which is the energy distribution of the ions irradiated on the surface of the substrate. The higher the frequency, the sharper the energy distribution, and the two peaks that appear in the case of low frequencies.
k also disappears, and the distribution has one energy peak. This is because as the frequency becomes higher, the ions are less likely to be swung by the high frequency, that is, it becomes difficult to obtain energy. Therefore, from the viewpoint of controllability, the higher the frequency, the more preferable. However, if the frequency is too high, the wavelength becomes about the same as that of the substrate, which causes the inner surface distribution, so about 50-500 MHz is preferable.

Regarding the substrate temperature, resistance heating is performed from the back surface of the electrostatic chuck, which is the substrate support, with a cantal heater. The control method is the PID control method and controls the thermocouple on the back surface of the substrate. It can be controlled within ± 1% on the substrate surface. The temporal change reaches the equilibrium temperature in about 30 minutes after placing the substrate on the electrostatic chuck, and the fluctuation thereafter is within ± 0.5%.
This good controllability is because an electrostatic chuck having a small surface roughness is used as the substrate support and heat energy is uniformly applied from the electrostatic chuck surface. However, the method is not limited to such a method, and if the controllability is good, radiant heating of a lamp or the like does not cause any problem.

Then, as shown in FIG. 1B, the epitaxial growth (103) is performed by the above-mentioned sputtering method.
Is performed on the surface of the porous substrate 102 to form a silicon single crystal layer 103 having good flatness and few stacking faults. The conditions at this time will be described.

In this apparatus, by precisely controlling the energy value of the ions irradiated onto the porous surface and the substrate temperature, a single-crystal Si film having no flatness on the porous surface and good flatness, or a porous film having pores on the porous surface is formed. A certain single crystal porous layer can be formed without degrading the underlying porous layer.

FIG. 4 shows an example of such a case in which 15 mTorr of Ar is used as an introduction gas and TargetDC is used.
It is a figure which summarized the crystallinity of the growth film when changing the ion irradiation energy and substrate temperature when 200 nm was deposited at a potential of −150 V, an rf power of 100 W, and a growth rate of 0.22 nm / sec.

In FIG. 4, under this condition, when the value of the ion irradiation energy is 40 eV or more, the ion irradiation energy is too strong and many defects are introduced into the growing film (region C in the figure). .

When the irradiation energy is 40 eV or less,
When the substrate temperature is set to a certain temperature, an Si single crystal film having no pores on the porous Si and good flatness can be obtained in the range indicated by the area A in the figure. The film thickness required at this time depends on the ion irradiation energy, the substrate temperature, etc., but for example, if the substrate temperature is 450 ° C. and the ion irradiation energy is 20 eV under the above conditions, 50 nm is required.

On the other hand, when the irradiation energy and the substrate temperature are changed and the growth conditions are changed in the direction of small energy, porous Si can be grown on the porous surface.
The site can be set to a desired value (region B in the figure).

That is, by controlling the thermal energy by the substrate temperature and the energy control by ion irradiation, the Si film formed on the porous layer can be freely controlled from a single crystal film with a flat surface to a porous layer with holes. It is possible, and by changing the target, a pn junction or a multilayer structure is possible, and the porosity of the porous layer can be continuously controlled by film formation during growth.

This is an example, but the condition for obtaining a flat single crystal film with few stacking faults is that the porosity is porous.
The conditions differ depending on the irradiation energy during deposition, the substrate temperature, the ratio γ of irradiated ions to the film forming semiconductor layer, the pressure, the substrate material, and the film forming material, and it is necessary to freely set the optimum value. What is important is that the energy value is precisely controlled, and a value that does not cause damage is given, and the energy by irradiating the surface of the substrate with ions and the thermal energy by the substrate temperature are appropriately given. γ is 0.1 to 30
The degree P is not particularly limited as long as the discharge is about 1 to 50 mTorr.

Then, as shown in FIG. 1C, a single crystal film 104 is further deposited by the CVD method. At this time, since the porous Si 102 is not already exposed on the surface, it may be grown under the conditions of epitaxial growth on the wafer. The surface cleaning condition with hydrogen is a low temperature of about 900 ° C., and the epitaxial layer has a good flatness and high quality. 104
Is obtained.

In FIG. 5, the film thickness deposited on the porous material by the bias sputtering method (BS) is plotted on the abscissa and C on the ordinate.
The surface roughness (rms value) of a 2 μm thick film deposited by the VD method is shown. The film thickness of 0 nm is 0.64 nm in rms value when the film is directly deposited by the CVD method. BS
2 μm thick with a film thickness of 5 nm and then deposited by the CVD method
The rms value of the film thickness is increased to 1 nm compared with the CVD method only.
However, the rms value suddenly decreases as the BS film thickness increases, and when the deposition is 50 nm or more, which fills the porous pores, the rms value is 2 μm deposited by the CVD method thereafter.
The rms value of the film thickness is 0.2 nm, which is similar to that of a Si wafer.

The deposition conditions for bias sputtering and CVD are shown below. Under this condition, the growth rate of the CVD method is about 13 times that of the bias sputtering method. Bias sputtering RF frequency: 100 MHz High frequency power: 100 W Temperature: 450 ° C. Ar gas pressure: 15 mTorr Growth rate: 0.22 nm / sec Target DC potential: −150 V Substrate DC potential: +20 V CVD source gas: SiH ₂ Cl ₂ … 500 sccm Carrier gas : H ₂ ... 230 l / min Substrate temperature: 900 ° C. Pressure: 80 Torr Growth rate: 2.92 nm / sec FIG. 6 shows the stacking fault density of the film under the same conditions as described above. When the BS film thickness is 50 nm or more, it sharply decreases as the BS film thickness increases, and the detection limit becomes 1 × 10 ³ / cm ² or less. It can be seen that both the surface flatness and the stacking fault density are drastically improved from around the film thickness where the bias sputtered film is deposited on the porous surface and flattened. Further, it is clear that when the bias sputtered film is 0, that is, when the single crystal film is deposited on the porous material only by the CVD method, it is significantly improved.

Then, the surface of the substrate is oxidized, and an Si film having an oxide film thickness of 500 nm is formed on the substrate and 90% in a nitrogen atmosphere.
It was laminated by heating at 0 ° C for 2 hours (Fig. 1
(D)). Both substrates 101 and 105 were firmly joined.

After that, the bonded substrates are polished from the back surface, and finally the porous layer is selectively etched with a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide. . The etching rate of the Si single crystal with respect to the etching solution is extremely low, it is 50 angstroms or less even after 65 minutes, and the selection ratio with respect to the etching rate of the porous layer reaches 10 5 or more, and etching in the single crystal layer The amount is a practically negligible reduction in film thickness. That is,
Single-crystal Si layers 104 and 103 having a thickness of 2 μm could be formed on the oxide film substrates 105 and 106 (FIG. 1).
(E)).

The void density is also remarkably reduced in accordance with the flatness of the surface, and is reduced from the value of 3.2 / cm ^{2 in} the case of only the CVD method to 0.6 / cm ² which is about 1/5. I was able to confirm that On the other hand, the film thickness distribution is ± within a 4-inch substrate.
Although it was within 5%, the value exceeded ± 10% in the case of only the bias sputtering method.

[0043]

EXAMPLES The present invention will be described below with reference to specific examples.

Example 1 A P-type (100) single crystal Si substrate having a thickness of 525 μm was anodized in an HF solution.

The anodization conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
1 hour: 11 (min) Porous Si thickness: 10 (μm) Porosity: 15 (%) The P-type (100) porous Si substrate was introduced into a sputtering apparatus, and the bias sputtering method (hereinafter referred to as BS method) was used. ), A Si epitaxial layer was grown at a low temperature of 0.2 micron on the porous substrate. The degree of vacuum before introducing Ar is 1E-9T.
It was orr. The deposition conditions are as follows. Surface cleaning conditions Temperature: 450 ° C Atmosphere: Ar Pressure: 15mTorr Substrate potential: 5V Target potential: -5V High frequency power: 5W RF frequency: 100MHz Deposition condition RF frequency: 100MHz High frequency power: 100W Temperature: 450 ° C Ar gas pressure : 15 mTorr Growth time: 15 min Film thickness: 0.2 μm Target DC potential: −150 V Substrate DC potential: 20 V The plasma potential at this time was 40 V as measured by the probe method and the irradiation energy was 20 eV.

Then, it was carried into a CVD apparatus and epitaxial Si was grown to 1 micron. The growth conditions are shown below. Surface cleaning conditions Carrier gas: H ₂ ... 180 l / min Substrate temperature: 1040 ° C Pressure: 80 Torr Growth time: 7.5 min Growth conditions Source gas: SiH ₂ Cl ₂ ... 500 sccm Carrier gas: H ₂ ... 230 l / min Substrate temperature: 900 ° C. Pressure: 80 Torr Growth time: 5.7 min The surface property of this epitaxial film was measured by AFM (atomic force microscope).
When observed in a 50 μm square area in y), the rms value was 0.193 nm, and pv (peak to ball)
The ey) value was 1.7 nm, which was as flat as the bulk Si wafer. On the other hand, when Secco Etching was performed to confirm the stacking fault density in the substrate, it was not observed.

On the other hand, in the AFM observation in the case where the epitaxial growth is directly performed on the porous material by the CVD method under the same conditions, the rms value is 0.662 nm and the pv value is 7.82.
The thickness is 6 nm, and when the stacking fault density is confirmed in the substrate by performing Secco Etching, it is 8.0E4 / cm.
^Two stacking faults were observed.

Next, this substrate was bonded to a Si substrate having an oxide film of 500 nm by heating at 900 ° C. for 2 hours in a nitrogen atmosphere. Both substrates were firmly bonded.

After that, the bonded substrate is polished from the back surface, and finally the porous layer is selectively etched with a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide. The etching rate of the Si single crystal with respect to the etching solution is extremely low, it is 50 angstroms or less even after 65 minutes, and the selection ratio with respect to the etching rate of the porous layer reaches 10 5 or more, and in the non-porous layer. The etching amount is a practically negligible reduction in film thickness. Eventually, a 1.2 μm-thick single crystal Si layer with few voids could be formed on the oxide film substrate.

Example 2 A P-type (100) single crystal Si substrate having a thickness of 525 μm was anodized in an HF solution.

The anodization conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
1 hour: 11 (min) Porous Si thickness: 10 (μm) Porosity: 15 (%) The P-type (100) porous Si substrate was introduced into a sputtering apparatus, and the bias sputtering method (hereinafter referred to as BS method) was used. ), A Si epitaxial layer was grown at a low temperature of 0.2 micron on the porous substrate. The degree of vacuum before introducing Ar is 1E-9T.
It was orr. The deposition conditions are as follows. Surface cleaning conditions Temperature: 550 ° C Atmosphere: Ar Pressure: 15mTorr Substrate potential: 5V Target potential: -5V High frequency power: 5W RF frequency: 100MHz Deposition condition RF frequency: 100MHz High frequency power: 100W Temperature: 550 ° C Ar gas pressure : 15 mTorr Growth time: 15 min Film thickness: 0.2 μm Target DC potential: -150 V Substrate DC potential: 25 V The plasma potential at this time was 40 V as measured by the probe method, and the irradiation energy was 15 eV.

Then, it was carried into a CVD apparatus and epitaxial Si was grown to 1 micron. The growth conditions are shown below. Surface cleaning conditions Carrier gas: H ₂ ... 180 l / min Substrate temperature: 900 ° C Pressure: 80 Torr Growth time: 7.5 min Growth conditions Source gas: SiH ₂ Cl ₂ ... 500 sccm Carrier gas: H ₂ ... 230 l / min Substrate temperature: 900 ° C. Pressure: 80 Torr Growth time: 5.7 min The surface property of this epitaxial film was measured by AFM (atomic force microscope).
As a result of observation in y), the rms value was 0.186n.
m, pv (peak to valley) value of 1.6
nm was as flat as a bulk Si wafer.
On the other hand, when Secco Etching was performed to confirm the stacking fault density in the substrate, it was not observed.

Then, this substrate was bonded to a fused quartz substrate by heating in a nitrogen atmosphere at 400 ° C. for 2 hours. Both substrates were firmly bonded.

After that, the bonded substrates are polished from the back surface, and finally the porous layer is selectively etched with a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide.

As a result, a single crystal Si layer having a thickness of 1.2 μm could be formed on the quartz substrate with few voids.

Example 3 A P-type (100) single crystal Si substrate having a thickness of 525 μm was subjected to anodization in an HF solution.

The anodization conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
1 hour: 11 (min) Porous Si thickness: 10 (μm) Porosity: 15 (%) MBE (Molecular Beam Epitaxy: Molecular B) capable of ion irradiation on the P-type (100) porous Si substrate
The Si epitaxial layer was grown at a low temperature of 0.1 micron by the electron epitaxy method. The deposition conditions are as follows.

Temperature: 700 ° C. Pressure: 1 × 10 ^-9 Torr Growth film thickness: 0.5 micron Ion irradiation energy 20-30 eV Then, the wafer was carried into a CVD apparatus and epitaxial Si was grown to 1 micron. The growth conditions are shown below. Surface cleaning conditions Carrier gas: H ₂ ... 180 l / min Substrate temperature: 1040 ° C Pressure: 80 Torr Growth time: 7.5 min Growth conditions Source gas: SiH ₂ Cl ₂ ... 500 sccm Carrier gas: H ₂ ... 230 l / min Substrate temperature: 900 ° C. Pressure: 80 Torr Growth time: 5.7 min The surface property of this epitaxial film was measured by AFM (atomic force microscope: atomic force microscope).
When observed in y), the rms value was 0.285n.
2.7 in m and pv (peak to valley) values
was nm. On the other hand, when Secco Etching was performed and the stacking fault density was confirmed in the substrate, it was 1.1E3 /
cm ^{2 was} observed.

On the other hand, in the AFM observation when epitaxial growth was directly performed on the porous material by the CVD method under the same conditions, the rms value was 0.662 nm and the pv value was 7.82.
The thickness is 6 nm, and when the stacking fault density is confirmed in the substrate by performing Secco Etching, it is 8.0E4 / cm.
^Two stacking faults were observed.

Example 4 A P-type (100) single crystal Si substrate having a thickness of 525 μm was anodized in an HF solution.

The anodization conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
1 hour: 11 (min) Porous Si thickness: 10 (μm) Porosity: 15 (%) The P-type (100) porous Si substrate was introduced into a sputtering apparatus, and the bias sputtering method (hereinafter referred to as BS method) was used. ), A Si epitaxial layer was grown at a low temperature of 0.2 micron on the porous substrate. The degree of vacuum before introducing Ar is 1E-9T.
It was orr. The deposition conditions are as follows. Surface cleaning conditions Temperature: 450 ° C Atmosphere: Ar Pressure: 15mTorr Substrate potential: 5V Target potential: -5V High frequency power: 5W RF frequency: 100MHz Deposition condition RF frequency: 100MHz High frequency power: 100W Temperature: 450 ° C Ar gas pressure : 15 mTorr Growth time: 15 min Film thickness: 0.2 μm Target DC potential: −150 V Substrate DC potential: 20 V The plasma potential at this time was 40 V when measured by the probe method, and the irradiation energy was 20 eV.

Then, it was carried into a CVD apparatus and epitaxial Si was grown to 1 micron. The growth conditions are shown below. Surface cleaning conditions Carrier gas: H ₂ ... 180 l / min Substrate temperature: 1040 ° C Pressure: 80 Torr Growth time: 7.5 min Growth conditions Source gas: SiH ₂ Cl ₂ ... 500 sccm Carrier gas: H ₂ ... 230 l / min Substrate temperature: 900 ° C. Pressure: 80 Torr Growth time: 5.7 min The surface property of this epitaxial film was measured by AFM (atomic force microscope: atomic force microscope).
When observed in a 50 μm square area in y), the rms value was 0.193 nm, and pv (peak to ball)
The ey) value was 1.7 nm, which was as flat as the bulk Si wafer.

Then, this substrate was replaced with a sapphire substrate 20.
Lamination was performed by heating at 0 ° C. for 2 hours. Both substrates were firmly bonded.

After that, the bonded substrates are polished from the back surface, and finally the porous layer is selectively etched with a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide. . The etching rate of the Si single crystal with respect to the etching solution is extremely low, it is 50 angstroms or less even after 65 minutes, and the selection ratio with respect to the etching rate of the porous layer reaches 10 5 or more, and in the non-porous layer. The etching amount is a practically negligible reduction in film thickness. Eventually, a 1.2 μm thick single crystal Si layer with few voids could be formed on the sapphire substrate.

Example 5 A P-type (100) single crystal Si substrate having a thickness of 525 μm was anodized in an HF solution.

The anodization conditions were as follows.

Current density: 7 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
1 hour: 11 (min) Porous Si thickness: 10 (μm) Porosity: 15 (%) The P-type (100) porous Si substrate was introduced into a sputtering apparatus, and the bias sputtering method (hereinafter referred to as BS method) was used. ), A Si epitaxial layer was grown at a low temperature of 0.2 micron on the porous substrate. The degree of vacuum before introducing Ar is 1E-9T.
It was orr. The deposition conditions are as follows. Surface cleaning conditions Temperature: 450 ° C Atmosphere: Ar Pressure: 15mTorr Substrate potential: 5V Target potential: -5V High frequency power: 5W RF frequency: 100MHz Deposition condition RF frequency: 100MHz High frequency power: 100W Temperature: 450 ° C Ar gas pressure : 15 mTorr Growth time: 15 min Film thickness: 0.2 μm Target DC potential: −150 V Substrate DC potential: 20 V The plasma potential at this time was 40 V when measured by the probe method, and the irradiation energy was 20 eV.

Then, it was carried into a CVD apparatus and epitaxial Si was grown to 1 micron. The growth conditions are shown below. Surface cleaning conditions Carrier gas: H ₂ ... 180 l / min Substrate temperature: 1040 ° C Pressure: 80 Torr Growth time: 7.5 min Growth conditions Source gas: SiH ₂ Cl ₂ ... 500 sccm Carrier gas: H ₂ ... 230 l / min Substrate temperature: 900 ° C. Pressure: 80 Torr Growth time: 5.7 min The surface property of this epitaxial film was measured by AFM (atomic force microscope: atomic force microscope).
When observed in a 50 μm square area in y), the rms value was 0.193 nm, and pv (peak to ball)
The ey) value was 1.7 nm, which was as flat as the bulk Si wafer. On the other hand, when Secco Etching was performed to confirm the stacking fault density in the substrate, it was not observed.

On the other hand, in the AFM observation in the case where the epitaxial growth was directly performed on the porous material by the CVD method under the same conditions, the rms value was 0.662 nm and the pv value was 7.82.
The thickness is 6 nm, and when the stacking fault density is confirmed in the substrate by performing Secco Etching, it is 8.0E4 / cm.
^Two stacking faults were observed.

Then, this substrate was bonded to a Si substrate on which Co was evaporated to a thickness of 20 nm by heating at 800 ° C. for 30 minutes in a nitrogen atmosphere. The interface is 70 nm CoSi ₂
The two substrates were firmly joined together.

Thereafter, the bonded substrates are polished from the back surface, and finally the porous layer is selectively etched with a mixed solution (10: 6: 50) of 49% hydrofluoric acid, alcohol and 30% hydrogen peroxide. . The etching rate of the Si single crystal with respect to the etching solution is extremely low, it is 50 angstroms or less even after 65 minutes, and the selection ratio with respect to the etching rate of the porous layer reaches 10 5 or more, and in the non-porous layer. The etching amount is a practically negligible reduction in film thickness.

As a result, a 1.2 μm-thick single-crystal Si layer with few voids in which CoSi ₂ was embedded could be formed.

[0077]

As described in detail above, according to the present invention,
Since an epitaxial film with few stacking faults, good flatness, and good film thickness distribution can be formed on a porous substrate at a relatively low temperature, it is also effective for bonding, and therefore a high-quality semiconductor substrate having an SOI structure can be obtained. It becomes possible to provide.

In particular, according to the present invention, by the bias sputtering method or the like, the temperature of the substrate is controlled, and at the same time, the deposited atoms are supplied while irradiating the ions whose energy is controlled. By depositing a single crystal film with few stacking faults, and then depositing it by the CVD method, which has excellent productivity and a small film thickness distribution, there are few voids and stacking faults, and the Si active layer film thickness distribution is also high quality. There is an effect that the SOI substrate can be formed as a film and has excellent productivity.

[Brief description of drawings]

FIG. 1 is a schematic cross section for explaining a process of the present invention.

FIG. 2 is a schematic configuration diagram of a bias sputtering apparatus used in the present invention.

FIG. 3 is a diagram showing the frequency dependence of the high frequency power applied to the target of the energy distribution of the ions irradiated onto the substrate surface.

FIG. 4 is a diagram showing crystallinity of a grown film when ion irradiation energy and substrate temperature are changed.

FIG. 5 is a diagram showing a surface roughness (rms value) of a film having a thickness of 2 μm deposited on a porous layer by a bias sputtering method and a CVD method thereafter.

FIG. 6 is a diagram showing a stacking fault density of a film having a thickness of 2 μm deposited on a porous layer by a bias sputtering method and a film having a thickness of 2 μm subsequently deposited by a CVD method.

[Explanation of symbols]

 1 Porous Layer 2 Epitaxial Si Single Crystal Layer 3 Si Substrate 4 Oxide Film 5 SOI Layer 10, 11 Low Pass Filter 91 Vacuum Chamber 92 Target 93 Permanent Magnet 94 Substrate 95 Substrate Support 96 High Frequency Power Supply 97 Matching Circuit 98, 99 DC Power Supply 101 Si substrate 102 Porous Si layer 103 Epitaxial film by bias sputtering 104 Epitaxial film by CVD 105 Second substrate 106 Oxide film

Claims (7)

[Claims] 1. A step of making a single crystal substrate porous, by supplying deposition atoms while irradiating ions having energy controlled on the substrate made porous at the same time while controlling the temperature of the substrate. 1. A method of manufacturing a semiconductor substrate, which comprises the step of performing the epitaxial growth of 1 and the step of performing the second epitaxial growth by a CVD method. 2. A step of making the first single crystal substrate porous,
A step of performing a first epitaxial growth on the porous first substrate by supplying deposited atoms while irradiating ions whose energy is controlled while controlling the temperature of the substrate, and then performing a first epitaxial growth by a CVD method. 2. A step of performing epitaxial growth, a step of bonding a second substrate on the epitaxial film of the first substrate, and a part of the first substrate including a porous layer other than the epitaxial film is removed after the bonding. A method for manufacturing a semiconductor substrate, comprising: 3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the first epitaxial growth method is a bias sputtering method. 4. The method for manufacturing a semiconductor substrate according to claim 1, wherein the porous single crystal is porous Si. 5. The method for producing a semiconductor substrate according to claim 1, wherein the step of making porous is anodization. 6. A first epitaxial film formed on an insulating substrate by supplying deposited atoms while irradiating ions, and a second epitaxial film formed on the first epitaxial film by a CVD method. A semiconductor substrate having a film. 7. The semiconductor substrate according to claim 6, wherein the first epitaxial film is formed by a bias sputtering method.