WO2002001617A1 - Semiconductor wafer processing method and plasma etching apparatus - Google Patents

Semiconductor wafer processing method and plasma etching apparatus Download PDF

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Publication number
WO2002001617A1
WO2002001617A1 PCT/JP2001/005402 JP0105402W WO0201617A1 WO 2002001617 A1 WO2002001617 A1 WO 2002001617A1 JP 0105402 W JP0105402 W JP 0105402W WO 0201617 A1 WO0201617 A1 WO 0201617A1
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WIPO (PCT)
Prior art keywords
wafer
semiconductor wafer
polishing
plasma
plasma etching
Prior art date
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PCT/JP2001/005402
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French (fr)
Japanese (ja)
Inventor
Hisashi Masumura
Makoto Kobayashi
Original Assignee
Shin-Etsu Handotai Co.,Ltd.
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Publication of WO2002001617A1 publication Critical patent/WO2002001617A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H01L21/02024—Mirror polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32366—Localised processing
    • H01J37/32376—Scanning across large workpieces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

Definitions

  • the present invention relates to a semiconductor wafer processing method and a plasma etching apparatus, and more specifically, to a technique for precisely flattening an entire wafer surface in a semiconductor wafer manufacturing process.
  • a single crystal rod manufactured by a single crystal manufacturing apparatus is sliced and thinned.
  • Slicing process A for obtaining a disk-shaped wafer, and chamfering process for chamfering the outer edge of the wafer obtained in the slice process A in order to prevent cracking or chipping of the wafer.
  • a step D a primary mirror polishing step E of roughing the surface of the etched wafer by sliding the surface of the wafer against a polishing cloth, and a finishing mirror polishing step F of finishing the surface of the primary mirror-polished wafer to finish mirror polishing; Finish mirror polished Ueha washed consisting final wash step G or et of removing abrasive and foreign matter adhering to the Ueha with.
  • the mirror-polished wafer obtained through the above-described process achieves a relatively high flatness in the center portion, as shown in FIG. 7, the mirror is approximately 5 mm from the outer edge of the wafer. So-called peripheral sagging often occurs from the position.
  • One of the causes of the peripheral sag is that when polishing the wafer in the primary mirror polishing process E, the peripheral part has a higher polishing pressure than the central part, and the peripheral part is excessively polished. It is in.
  • the integration density of semiconductor devices has increased, and the minimum line width of the circuit itself has reached a level of 0.13 / xm or less.
  • the site-based site flatness SFQR of the semiconductor wafer which is the substrate, is 0.13 / xm or less (site size: 25 mm X A level of 36 mm) is required.
  • the flatness guarantee area is conventionally 3 mm inside the outer peripheral edge. What has expanded into the 2 mm or 1 mm inner area.
  • SFQR Sitefrontrons-sQuaresRange
  • TTV Total Thickness Variation
  • PACE Pulsma Assisted Chemical Etching
  • After measuring the thickness distribution of the wafer by optical interference method or capacitance method According to its thickness distribution -The relative removal speed of the nozzle that irradiates the plasma on the surface of the wafer is controlled to control the amount of etching removed by the plasma, and the entire surface of the wafer is highly flat.
  • a raw material wafer W such as a silicon wafer is placed between a high-frequency electrode 1 and a ground electrode 2. Then, a high frequency is applied to the high frequency electrode 1 to form a plasma of a raw material gas such as SF 6 in the nozzle 3 and irradiates the surface of the raw material A wafer W.
  • a raw material gas such as SF 6
  • SF 6 a raw material gas
  • the raw material gas in the nozzle is subjected to plasma irradiation by applying a microwave to the nozzle, and this is used as an original.
  • plasma irradiation by applying a microwave to the nozzle, and this is used as an original.
  • irradiating the chemical wafer There is also a method of irradiating the chemical wafer.
  • semiconductor wafers often have peripheral sag, and plasma etching tends to excessively etch the peripheral area of the wafer. There is also a problem that it is difficult to achieve high flatness to the periphery.
  • Japanese Patent Application Laid-Open No. 11-26071 discloses that the raw material wafer is made concave to reduce surface irregularities, and this is called plasma etching. It discloses the technology for switching. With this technology, High flatness is achieved over the entire surface.
  • the diameter of the nozzles used in PACE varies from at least 3 mm to several tens of mm, but when plasma etching is performed using small-diameter nozzles, machining accuracy is improved.
  • machining accuracy is improved.
  • the larger the nozzle diameter the larger the local etching area and the higher the throughput, but the waviness component in a range smaller than the nozzle diameter Since it cannot be corrected, the flatness achieved after etching is reduced, and it is difficult to achieve the recently required SFQR max ⁇ 0.13 // II1.
  • the present invention has been made in view of the above-mentioned problems, and can achieve high-precision flattening over the entire surface of the wafer and high throughput. It is an object of the present invention to provide a method for processing a semiconductor wafer that can be processed, and a plasma etching apparatus that can be used for processing such a semiconductor wafer.
  • the surface of a semiconductor wafer is polished by bringing the surface of the semiconductor wafer into sliding contact with a polishing cloth with a predetermined polishing pressure, and the polished surface is subjected to plasma etching.
  • the polishing pressure at the peripheral portion of the semiconductor wafer is set to be smaller than that at the central portion so that the peripheral portion rises, and only the peripheral portion is polished. Processing of semiconductors, characterized by plasma-etching A method is provided.
  • the polishing pressure at the periphery of the wafer is made smaller than that at the center, so that the periphery is raised, and only the raised periphery is removed.
  • plasma etching it is possible to achieve high flatness over the entire surface of the wafer, and to significantly reduce the etching time and improve the throughput. it can . Also, it is possible to omit the mirror polishing after plasma etching without deteriorating the haze level in the center of the wafer.
  • the peripheral portion of the semiconductor wafer to be plasma etched is a region within 5 mm from the outer peripheral end of the wafer.
  • plasma etching should be performed with a diameter of l mm n! It is preferable to irradiate a raw material gas which is plasma-treated from nozzle force within a range of ⁇ 2 mm.
  • the force S can be suitably etched only in a narrow area around the wafer.
  • the source gas used for the plasma etching of the present invention can be a chlorine-based, hydrogen-based, or fluorine-based gas.
  • semiconductors such as silicon can be used.
  • the body can be suitably etched.
  • the source gas having been converted into a plasma has a diameter of the nozzle.
  • a plasma etching device characterized by being within the range of 1 mm to 2 mm is provided.
  • the polishing pressure at the peripheral portion of the semiconductor wafer is made smaller than that at the central portion, and the peripheral portion is polished by being brought into sliding contact with the polishing cloth.
  • the polishing cloth By forming a raised shape and then subjecting the polished surface to plasma etching only at the peripheral portion, excellent flatness can be achieved up to the peripheral portion of the wafer.
  • FIG. 1 is a schematic diagram showing an example of plasma etching.
  • FIG. 2 is a schematic diagram showing an example of plasma etching only the peripheral portion of the wafer using the apparatus according to the present invention.
  • FIG. 3 is a diagram schematically showing polishing of the wafer while holding the wafer with a holding plate having a smaller diameter than the wafer.
  • Fig. 4 shows the results obtained before and after the plasma etching in Example 1. This is a graph showing the amount of displacement of the thickness of the peripheral part of.
  • FIG. 5 is a graph showing the displacement of the thickness of the periphery of the wafer measured in Example 2 and Comparative Example.
  • FIG. 6 is a flowchart showing a general manufacturing process of a conventional semiconductor wafer.
  • FIG. 7 is a graph showing the displacement of the thickness of the peripheral portion after polishing the wafer with a polishing cloth in the conventional polishing process.
  • a semiconductor ingot grown from a silicon or other raw material melt by the chiral key method (CZ method) or the floating zone melting method (FZ method) is sliced. And say “Eno”.
  • etching is performed to remove processing distortion and the like on the wafer surface. In some cases, surface grinding is performed instead of wrapping.
  • the wafer that has undergone such a process is subjected to surface polishing in order to make the surface more flat and mirror-finished, but in the present invention, the wafer is formed into a shape in which the periphery of the wafer is raised in the polishing process. .
  • the polishing pressure at the peripheral portion of the semiconductor wafer is set to be smaller than that at the central portion, thereby reducing the polishing allowance at the peripheral portion and increasing the peripheral portion.
  • the method for reducing the polishing pressure in the peripheral portion is not particularly limited. ⁇ ⁇ A thin back coat film is formed on the back (rear side) from the center rather than the center, and ⁇ The back of the wafer is held by a conventional holding plate via the back coat film.
  • the polishing agent While holding W, the polishing agent is supplied to the polishing cloth 8 stuck on the surface plate 7 and, at a predetermined polishing pressure (pressure), the W is slid into contact with the polishing cloth 8 for polishing. You should. In this way, if the polishing is carried out while holding the blade, it protrudes from the holding surface of the holding plate.Because the polishing pressure in the peripheral part is smaller than that in the central part, the polishing allowance is reduced accordingly. . On the other hand, the thickness of the central portion of W, which is in contact with the holding surface of the holding plate 6, is almost uniform, achieving high flatness, and the peripheral portion is raised after polishing. Can be obtained.
  • the wafer that has been polished into a shape with a raised peripheral portion is then locally plasma-etched only on the raised peripheral portion.
  • ⁇ the thickness at each position on the entire surface is measured in advance by an optical interference method or a capacitance method, and ⁇ the entire surface is made uniform so that the entire thickness becomes uniform. While scanning was performed according to the measured value, according to the present invention, only the surrounding raised portion is plasma-etched.
  • the region to be plasma etched only the raised portion of the peripheral portion needs to be etched according to the measured value as described above, but it is polished with a polishing cloth.
  • excellent flatness can be achieved within 5 mm from the outer peripheral edge of the wafer.
  • the area within 5 mm from the outer edge of the ⁇ C can be plasma etched. For example, high flatness can be achieved over the entire wafer.
  • the diameter of 3 mm is relatively small among the conventional ones. Although it is possible to use one with a diameter of about 5 mm, it is possible to use a nozzle of such a size for a width of 5 mm around the ⁇ eno, but ultimately high accuracy Difficult etching processing is difficult. Therefore, in the present invention, plasma etching is performed by irradiating a plasma-processed raw material gas from a nozzle having a diameter in a range of 1 mm to 2 mm, thereby achieving very small area units. In addition to being able to perform high-precision etching, since only the peripheral portion is etched, the wafer can be removed with a high throughput.
  • a plasma etching apparatus provided with a nozzle having a diameter smaller than the conventional nozzle diameter and having a diameter in the range of lmni to 2 mm is used. As a result, only the periphery of the wafer can be more suitably etched.
  • the shape of the nozzle is not particularly limited.
  • a rectangular nozzle having a side of 1 to 2 mm may be used.
  • Efficient treatment can also be achieved by forming the shape along the outer periphery of the periphery of the wafer.
  • the method of plasma-forming the raw material gas is not particularly limited, and a method of applying a high frequency to a high-frequency electrode integrated with the nozzle or a method of applying a microwave to the nozzle is used. Any method such as the method can be adopted.
  • FIG. 2 schematically shows an example of a case where only the peripheral portion of the wafer is plasma-etched using the apparatus according to the present invention.
  • the raw material ⁇ E-W whose peripheral part is raised by polishing, is fixed on the rotating table 4 with an electrostatic chuck and rotated, and the diameter of the irradiation port is 1 to 2 mm.
  • Microwaves are applied to the spill 5 to plasmically irradiate the raw material gas, and this is radiated only to the peripheral portion of the wafer W, thereby facilitating the processing. Only the surrounding area can be etched.
  • the present invention it is possible to process a raw material ⁇ Ano ⁇ at a high throughput and to provide a mirror surface ⁇ A having a very excellent flatness to a peripheral portion, thereby producing an ⁇ Ea ⁇ . Quality and non-defective rate can be significantly improved.
  • a circuit can be formed over the entire surface, and the productivity and yield of semiconductor devices can be significantly improved.
  • the silicon wafer (diameter: 200 mm) obtained by slicing the ingot is suction-held using a polishing head (holding plate) that can adjust the polishing pressure around the wafer.
  • a polishing head holding plate
  • the wafer surface is slid against the polishing cloth for polishing.
  • a mirror-polished wafer (SFQR max: 0.20 ⁇ m) was obtained.
  • S FQR max represents the maximum value of S FQR of all sites on the wafer.
  • the thickness of the area within 12 mm from the outer edge of the mirror-polished wafer was measured, and plasma etching was performed based on the measured values.
  • thickness As a result of measuring only the peripheral portion, the time required for the measurement can be reduced as compared with the case where the entire surface of the wafer is measured.
  • the thickness around the wafer after plasma etching is flattened to the exclusion area of the peripheral area, and at the same time, within a narrow range.
  • the SFQR max which indicates the flatness of the surface, is also significantly improved from 0.20 / 111 after polishing to 0.5 ⁇ .
  • a silicon head (diameter: 200 mm) obtained by slicing an ingot is used to hold a polishing head (holding) that can adjust the polishing pressure around the wafer. Plate), hold the wafer at the periphery (especially 3 mm from the outer peripheral edge) with a lower pressure than the center, and slide the wafer surface against the polishing cloth for polishing. Then, a mirror-polished anode (SFQR max: 0.20 Mm) was obtained.
  • SFQR max 0.20 Mm
  • the thickness of an area within 5 mm from the outer edge of the wafer was measured on the polished surface of the mirror-polished wafer, and plasma etching was performed based on the measured value.
  • the thickness distribution (exclusion area: 2 mm around the periphery) of the wafer before and after plasma etching (raw material shape) and after (processed shape) was measured using a capacitance-type thickness measuring instrument. The results are shown in FIG.
  • the etching time was 10 seconds.
  • the entire polished surface of the mirror-polished surface was plasma-etched (etching time: 50 seconds).
  • the thickness distribution and haze level around the wafer were measured.
  • FIG. 5 is a graph showing the amount of thickness displacement before and after plasma etching in Example 2 and in the peripheral portion of each wafer of the comparative example based on a position 1 mm from the outer peripheral edge. It is. From this drawing force, the wafer obtained in the comparative example appears to have improved flatness at first glance compared to the wafer of Example 2; At about 4 mm and 8 mm from this point, there is a variation point force S, and the SFQR max shows a large value of 0.15 ⁇ . On the other hand, in the wafer obtained in Example 2, the thickness displacement in the region within 10 mm from the outer peripheral end was larger than that of the comparative example, but there was no displacement point, and SFQR max was 0. It shows a small value of 0 ⁇ ⁇ m, and the flatness of the local area is greatly improved.
  • the semiconductor wafer to which the present invention can be applied is not limited to this.
  • semiconductor wafers made of materials other than silicon can be used. It can be applied to this.
  • the size of the wafer is not particularly limited, and the present invention is more effective for a large-diameter wafer.
  • the method for forming the peripheral portion of the wafer into a raised shape is not particularly limited, and the pressure applied to the peripheral portion and the central portion is separately determined by a polishing head as in the embodiment.
  • a method of polishing the wafer holding part using a polishing head with a smaller diameter than the wafer diameter, or a method of protecting the wafer backside with resin or other protective film In order to reduce the thickness to coat only the periphery of the wafer, and to hold and hold the backside of the wafer by suction, the periphery of the wafer rises. It can be processed into a different shape.
  • the plasma etching of the present invention can be performed after the polishing step, that is, after the finishing mirror polishing step, but after the primary mirror polishing of the multi-step polishing. You may go to After polishing, the surrounding area of the wafer is raised to a protruding shape, and then plasma etching can be performed to achieve a highly flat wafer. .

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Abstract

A semiconductor wafer processing method for polishing the surface of a semiconductor wafer with an abrasive cloth sliding on the surface of the semiconductor wafer at a predetermined polishing pressure, characterized in that the polishing pressure on the peripheral portion of the semiconductor wafer is weaker than that on the central portion so that the peripheral portion is raised after the polishing and in that only the peripheral portion is plasma-etched. A plasma etching apparatus characterized in that the diameter of a nozzle ranges from 1 to 2 mm is also disclosed. The entire surface of a semiconductor wafer can be flattened with high precision and high throughput.

Description

明 細 書 半導体 ゥエーハの加工方法及ぴプラ ズマエ ッチング装置 技術分野  Description Semiconductors ゥ Processing methods for wafers and plasma etching equipment Technical field
本発明 は、 半導体ゥエーハの加工方法及びプラ ズマエ ッ チング装 置、 具体的には、 半導体ゥエーハの製造工程において、 ゥエーハ表 面全体を高精度に平坦化する技術に関する。 背景技術  The present invention relates to a semiconductor wafer processing method and a plasma etching apparatus, and more specifically, to a technique for precisely flattening an entire wafer surface in a semiconductor wafer manufacturing process. Background art
従来、 例えば半導体シ リ コ ンゥエーハ の製造は、 図 6 に一般的な 工程の流れを示 した よ う に、 単結晶製造装置に よ って製造された単 結晶棒をス ラ イ ス し て薄円板状の ゥエーハを得る ス ラ イ ス工程 A と ， 該ス ラ イ ス工程 Aで得 られた ゥエーハの割れや欠けを防ぐためにそ の外周エ ッ ジ部を面取 り する面取 り 工程 B と 、 面取 り された ゥエー ノ、をラ ッ ビングして これを平坦化する ラ ッ ビング工程 C と 、 面取 り およびラ ッ ビングされた ゥエーハ表面に残留する加工歪を除去する エ ッチング工程 D と 、 エ ッチングされた ゥエーハの表面を研磨布に 摺接させて粗研磨する一次鏡面研磨工程 E と 、 一次鏡面研磨 された ゥエーハの該表面を仕上げ鏡面研磨する仕上げ鏡面研磨工程 F と 、 仕上鏡面研磨 された ゥエーハを洗浄 して ゥエーハに付着 した研磨剤 や異物を除去する最終洗浄工程 Gか ら成る。  Conventionally, for example, in the manufacture of semiconductor silicon wafers, as shown in a general process flow in FIG. 6, a single crystal rod manufactured by a single crystal manufacturing apparatus is sliced and thinned. Slicing process A for obtaining a disk-shaped wafer, and chamfering process for chamfering the outer edge of the wafer obtained in the slice process A in order to prevent cracking or chipping of the wafer. A rubbing step C for rubbing B and the chamfered ゥ -Eno to flatten it, and an etching for removing machining distortion remaining on the chamfered and rubbed ゥ -Ah surface. A step D, a primary mirror polishing step E of roughing the surface of the etched wafer by sliding the surface of the wafer against a polishing cloth, and a finishing mirror polishing step F of finishing the surface of the primary mirror-polished wafer to finish mirror polishing; Finish mirror polished Ueha washed consisting final wash step G or et of removing abrasive and foreign matter adhering to the Ueha with.
前記の よ う な工程を経て得 られる鏡面研磨 ゥエーハは、 中央部分 では比較的高い平坦度が達成 される も の の 、 図 7 に示 される よ う に ゥエーハ外周端部か ら 5 m m前後の位置か ら いわゆ る周辺ダ レが生 じる場合が多い。 周辺ダレが生じる原因の 1 つ と しては、 一次鏡面 研磨工程 E でゥエーハ を研磨する際、 周辺部分の研磨圧が中央部分 よ り 高 く 、 周辺部分が過剰に研磨されて しま う こ と にあ る。 近年、 半導体デバイ ス の高集積化が進み、 回路 自 体の最小線幅は 0 . 1 3 /x m以下の レベル と な り 、 リ ソ グラ フ ィ プロ セスで回路 を 半導体ゥエーハ表面に形成する際にその焦点深度を確保する 目 的か ら、 基板 と な る 半導体ゥエーハ の表面基準のサイ ト フ ラ ッ ト ネ ス S F Q Rは、 0 . 1 3 /x m以下 （サイ ト サイ ズ ： 2 5 m m X 3 6 m m ) の レベルが要求 されてい る。 ま た、 コ ス ト の観点か ら 1 枚の半導 体ゥエーハか ら の半導体デバイ ス の収率を上げる ために、 平坦度の 保証エ リ ァは、 従来外周端部か ら 3 m m内側領域であっ た も のが、 2 m m又は 1 m m内側領域へと 拡大 している。 Although the mirror-polished wafer obtained through the above-described process achieves a relatively high flatness in the center portion, as shown in FIG. 7, the mirror is approximately 5 mm from the outer edge of the wafer. So-called peripheral sagging often occurs from the position. One of the causes of the peripheral sag is that when polishing the wafer in the primary mirror polishing process E, the peripheral part has a higher polishing pressure than the central part, and the peripheral part is excessively polished. It is in. In recent years, the integration density of semiconductor devices has increased, and the minimum line width of the circuit itself has reached a level of 0.13 / xm or less. When a circuit is formed on a semiconductor wafer surface by a lithographic process. In order to secure the depth of focus, the site-based site flatness SFQR of the semiconductor wafer, which is the substrate, is 0.13 / xm or less (site size: 25 mm X A level of 36 mm) is required. In order to increase the yield of semiconductor devices from a single semiconductor wafer from the viewpoint of cost, the flatness guarantee area is conventionally 3 mm inside the outer peripheral edge. What has expanded into the 2 mm or 1 mm inner area.
こ こ で S F Q R ( S i t e F r o n t l e a s t - s Q u a r e s R a n g e ) と は、 平坦度に関 して表面基準の平均平面 を サイ ト毎に算出 し、 その面に対する 凹凸の最大範囲を表 した値であ る。 . 一方、 上記の よ う に近年の最先端の半導体デバイ スの高集積化に 対応すべく 、 ゥエーハ全面にわたっ て高度な平坦度 とする こ と が要 求されてい る。 そのため、 ゥエーハ製造工程中、 研磨工程後にブラ ズマエ ッチング工程が追加 される こ と があ る。 こ の よ う にすれば、 ゥエーノヽの平坦度 （ T T V : T o t a l T h i c k n e s s V a r i a t i o n 、 すなわち ゥェ一ハ全面におけ る最大厚 と 最小厚 の差） を一層向上させる こ と が可能であ る。  Here, SFQR (Sitefrontrons-sQuaresRange) is a value that calculates the average plane of the surface reference for each flatness for each site, and expresses the maximum range of unevenness for that surface. is there. On the other hand, as described above, in order to cope with the recent high integration of the most advanced semiconductor devices, it is required to have a high degree of flatness over the entire surface of the wafer. Therefore, during the wafer manufacturing process, a plasma etching process may be added after the polishing process. In this way, it is possible to further improve the flatness of the antenna (TTV: Total Thickness Variation, ie, the difference between the maximum thickness and the minimum thickness over the entire wafer). You.
こ のプラ ズマエ ッ チング工程の一実施形態 と して、 例えば、 P A C E ( P l a s m a A s s i s t e d C h e m i c a l E t c h i n g ： プラ ズマ捕助化学エ ッチング） と 呼ばれる技術が開発 されている （例えば、 特開平 5 — 1 6 0 0 7 4 号公報、 特開平 6 — 5 5 7 1 号公報、 特開平 7 — 2 8 8 2 4 9 号公報参照）。  As one embodiment of this plasma etching step, for example, a technique called PACE (Plasma Assisted Chemical Etching) has been developed (for example, see Japanese Patent Application Laid-Open No. H05-205, 1993). — Refer to Japanese Patent Application Laid-Open No. 160704/1994, Japanese Patent Application Laid-Open No. 6-55771, and Japanese Patent Application Laid-Open No. 7-2888249.
これはプラ ズマに よ り ゥエーハ表面を部分的にエ ッチング しなが ら ゥエーハの厚 さ を均一化する方法であ り 、 ゥエーハの厚 さ分布を 光学干渉法や静電容量法で測定した後、 その厚さ分布に応 じて ゥェ ー ハ表面にブラ ズマ を照射する ノ ズルの相対的な移動速度を制御す る こ と に よ り プラ ズマによ るエ ッチ ング除去量を制御 し、 ゥエ ーハ 全面を高平坦度化する技術であ る。 This is a method of uniformizing the thickness of the wafer while partially etching the surface of the wafer by plasma.After measuring the thickness distribution of the wafer by optical interference method or capacitance method, According to its thickness distribution -The relative removal speed of the nozzle that irradiates the plasma on the surface of the wafer is controlled to control the amount of etching removed by the plasma, and the entire surface of the wafer is highly flat. Technology.
プラ ズマエ ッ チングの具体的な操作と しては、 図 1 に示すよ う に 高周波電極 1 と 接地電極 2 と の間に シ リ コ ン ゥエ ーハ等の原料ゥ ェ —ハ Wを置き 、 高周波電極 1 に高周波を印力 Π して ノ ズル 3 内 の S F 6等の原料ガ ス をプラ ズマ化 して原料ゥ エーハ Wの表面に照射す る 。 これに よ り ゥ エ ーハ表面の う ち ノ ズル 3 下に位置する領城を局所 的にエ ッ チングす る こ と ができ る。 したがっ て、 予め測定 した原料 ゥエ ー ノヽ Wの厚 さ分布に応 じて ノ ズル 3 あ る いは原料ゥエーハ Wの 移動速度を制御 しなが ら ゥエ ーハ wの表面全体を走査する こ と に よ り 半導体ゥエ ーハ表面全体を高平坦化す る こ と ができ る。 なお、 上 記の よ う に原科ガス を高周波電極でプラ ズマ化す る方法のほか、 ノ ズルにマイ ク 口 波を当 てて ノ ズル内 の原料ガス をプラ ズマィ匕 し、 こ れを原科ゥエ ーハに照射する方法も あ る。 As a specific operation of plasma etching, as shown in FIG. 1, a raw material wafer W such as a silicon wafer is placed between a high-frequency electrode 1 and a ground electrode 2. Then, a high frequency is applied to the high frequency electrode 1 to form a plasma of a raw material gas such as SF 6 in the nozzle 3 and irradiates the surface of the raw material A wafer W. As a result, it is possible to locally etch the territory located below nozzle 3 on the wafer surface. Accordingly, the entire surface of the wafer w is scanned while controlling the moving speed of the nozzle 3 or the material W according to the thickness distribution of the material W which is measured in advance. As a result, the entire surface of the semiconductor wafer can be highly flattened. In addition to the method of converting the raw gas into a plasma with a high-frequency electrode as described above, the raw material gas in the nozzle is subjected to plasma irradiation by applying a microwave to the nozzle, and this is used as an original. There is also a method of irradiating the chemical wafer.
しかし、 プラ ズマエ ッチングを行 う 場合、 原料ゥエ ーハの形状が 凹凸があればあ る ほ どノ ズルの速度制御は複雑にな り 、 ノ ズルの走 向距離あ るいは加速減速頻度が増大する。 そ のた め加工時間が長 く 、 不安定な も の と な り 、 生産性が低下 して しま う 。 また、 ゥエ ーハの T T Vが悪い場合にも 、 プラ ズマエ ッ チ ングによ る除去量が増え、 加工時間が長 く なっ て しま う と い う 問題があ る。  However, when performing plasma etching, the more the shape of the raw material wafer is uneven, the more complicated the speed control of the nozzle becomes, and the more the nozzle travels or accelerates / decelerates. Increase. This results in long machining times, instability, and reduced productivity. Also, when the TTV of the wafer is poor, there is a problem that the removal amount by plasma etching increases and the processing time becomes longer.
また、 前述の よ う に半導体ゥエ ーハには周辺ダ レが生じている場 合が多い上、 プラ ズマエ ッチングではゥエーハの周辺部分が過剰に エ ッチ ング される傾向があ る ので、 周辺部分まで高い平坦性を達成 する こ と は困難であ る と い う 問題も あ る。  In addition, as described above, semiconductor wafers often have peripheral sag, and plasma etching tends to excessively etch the peripheral area of the wafer. There is also a problem that it is difficult to achieve high flatness to the periphery.
こ の よ う な問題に対 し、 特開平 1 1 一 2 6 0 7 7 1 号公報では、 原料ゥエ ーハ を凹形状 と して表面の凹凸 を少な く し、 これをプラ ズ マエ ッ チングする技術を開示 してい る。 こ の技術によ，り 、 ゥエーハ 全面にわた っ て高い平坦度を達成 してい る。 In order to solve such a problem, Japanese Patent Application Laid-Open No. 11-26071 discloses that the raw material wafer is made concave to reduce surface irregularities, and this is called plasma etching. It discloses the technology for switching. With this technology, High flatness is achieved over the entire surface.
従来、 P A C E で使用 されている ノ ズルの径は少な く と も 3 m m 〜数十 m mまで様々 である が、 小径の ノ ズルを用いてプラ ズマエ ツ チングを行っ た場合、 加工精度が上が る も の の、 ゥエーハ全面を走 查する の に時間がかかり ス ループ ッ ト が低下する問題があ る。 一方、 ノ ズルの径が大き いも のほ ど局所エ ッチング領域が大き く な り 、 ス ループ ッ ト を向上させる こ と ができ る が、 ノ ズル径よ り 小 さ い範囲 の う ね り 成分を修正する こ と はでき ないので、 エ ッチング後 に達成 される平坦度が低下 し、 近年要求 されている S F Q R m a x ≤ 0 . 1 3 // II1ま で達成する こ と は困難である。  Conventionally, the diameter of the nozzles used in PACE varies from at least 3 mm to several tens of mm, but when plasma etching is performed using small-diameter nozzles, machining accuracy is improved. However, there is a problem that it takes time to run the entire surface of the wafer and the throughput is reduced. On the other hand, the larger the nozzle diameter, the larger the local etching area and the higher the throughput, but the waviness component in a range smaller than the nozzle diameter Since it cannot be corrected, the flatness achieved after etching is reduced, and it is difficult to achieve the recently required SFQR max ≤ 0.13 // II1.
また、 ゥエーハ全面をプラ ズマエ ッチングする と 、 表面が粗 く な り ヘイ ズ レベルが悪化し、 表面の微小な欠陥密度を検出する 際のパ 一ティ クル測定が困難で保証でき ないと い う 理由 から 、 プラ ズマェ ツチング後に再度研磨代が微少の研磨が必要にな り 、 コ ス ト ア ッ プ につなが る と い う 問題も あ る。 発明の開示  Also, if plasma etching is performed on the entire surface of the wafer, the surface becomes rough and the haze level deteriorates, and the particle measurement when detecting the minute defect density on the surface is difficult and cannot be guaranteed. Therefore, there is also a problem that a small amount of polishing is required again after the plasma cutting, which leads to cost up. Disclosure of the invention
本発明 は上記問題点に鑑みてな さ れた も の で、 ゥエ ーハ表面全体 にわたつ て高精度に平坦化する こ と ができ る と と も に、 高いス ルー プ ッ ト で処理する こ と ができ る 半導体ゥエー ハの加工方法、 及びそ の よ う な半導体 ゥエーハの加工に使用でき る プラ ズマエ ッ チ ング装 置を提供する こ と を 目 的 と する。  The present invention has been made in view of the above-mentioned problems, and can achieve high-precision flattening over the entire surface of the wafer and high throughput. It is an object of the present invention to provide a method for processing a semiconductor wafer that can be processed, and a plasma etching apparatus that can be used for processing such a semiconductor wafer.
前記 目 的を達成するため 、 本発明 によれば、 半導体ゥエ ーハの表 面を所定の研磨圧で研磨布に摺接さ せて研磨 し、 該研磨 した表面 を プラ ズマエ ッ チ ングする半導体 ゥエーハの加工方法において、 前記 半導体 ゥエーハの周辺部分の研磨圧 を中央部分よ り 小 さ く して研磨 する こ と に よ り 周辺部分が盛 り 上が っ た形状 と し、 該周边部分のみ をプラ ズマェ ツ チングする こ と を特徴と する 半導体ゥエ ー ノヽの加工 方法が提供 される。 In order to achieve the above object, according to the present invention, the surface of a semiconductor wafer is polished by bringing the surface of the semiconductor wafer into sliding contact with a polishing cloth with a predetermined polishing pressure, and the polished surface is subjected to plasma etching. In the method for processing a semiconductor wafer, the polishing pressure at the peripheral portion of the semiconductor wafer is set to be smaller than that at the central portion so that the peripheral portion rises, and only the peripheral portion is polished. Processing of semiconductors, characterized by plasma-etching A method is provided.
こ の よ う に半導体 ゥ エーハを研磨する際、 ゥエーハの周辺部分の 研磨圧を中央部分よ り 小 さ く して周辺部分が盛 り 上がっ た形状 と し 、 こ の盛 り 上がっ た周辺部分のみをプラ ズマエ ッ チングすれば、 ゥ エーハ全面にわたっ て高平坦度を達成す る こ と ができ る上、 エ ッ チ ング時間を大幅に短縮 してス ループ ッ ト を向上 さ せる こ と ができ る 。 ま た、 ゥエーハ中央部分のヘイ ズ レベルを悪化 させる よ う な こ と も な く 、 プラ ズマエ ッ チ ン グ後の鏡面研磨も省略する こ と も 可能で め る。  When polishing semiconductor wafers in this way, the polishing pressure at the periphery of the wafer is made smaller than that at the center, so that the periphery is raised, and only the raised periphery is removed. By plasma etching, it is possible to achieve high flatness over the entire surface of the wafer, and to significantly reduce the etching time and improve the throughput. it can . Also, it is possible to omit the mirror polishing after plasma etching without deteriorating the haze level in the center of the wafer.
前記半導体 ゥエーハのプラ ズマエ ッチングする周辺部分は、 該 ゥ エーハの外周端部か ら 5 m m以内の領域である こ と が好ま しい。  It is preferable that the peripheral portion of the semiconductor wafer to be plasma etched is a region within 5 mm from the outer peripheral end of the wafer.
前記した よ う に従来の方法では半導体 ゥエーハを研磨布に摺接 さ せて研磨する と ゥエーハの 中央部分では高平坦度 を達成でき る が、 ゥエーハ周辺 5 m m領域で高平坦度を達成す る こ と は困難であ る。 そ こ で、 ゥエ ーハ外周端部か ら 5 m m以内の領域を盛 り 上がっ た形 状 と して こ の領域だけ をプラ ズマエ ッチ ングすれば、 ゥエーハ全面 を よ り 効率的に平坦化でき 、 エ ッチ ング時間 を大幅に短縮 してス ル ー プ ッ ト を向上 させる こ と ができ る と と も に、 中央部分の品質を劣 ィ匕 させる こ と も ない。  As described above, in the conventional method, when the semiconductor wafer is polished by sliding it on a polishing cloth, high flatness can be achieved in the central portion of the wafer, but high flatness can be achieved in a 5 mm area around the wafer. This is difficult. Therefore, if the area within 5 mm from the outer peripheral edge of the wafer is raised and plasma etching is performed only on this area, the entire surface of the wafer is more efficiently flattened. In addition, the etching time can be greatly reduced to improve the throughput, and the quality of the central portion is not degraded.
こ の場合、 プラ ズマエ ッ チングを、 径が l m n！ 〜 2 m mの範囲内 にあ る ノ ズル力 ら プラ ズマィ匕した原料ガス を照射 して行 う こ と が好 ま しい。  In this case, plasma etching should be performed with a diameter of l mm n! It is preferable to irradiate a raw material gas which is plasma-treated from nozzle force within a range of ~ 2 mm.
こ の よ う な小径の ノ ズル力 ら プラ ズマ を照射 してエ ッ チ ングを行 えば、 ゥエーハ周辺部分の狭い領域だけを好適にェ ツチン グする こ と 力 Sでき る。  If etching is performed by irradiating the plasma from such a small-diameter nozzle force, the force S can be suitably etched only in a narrow area around the wafer.
本発明のプラ ズマエ ッチ ングに用 いる原料ガス は、 塩素系、 水素 系、 またはフ ッ素系のガス と する こ と ができ る。  The source gas used for the plasma etching of the present invention can be a chlorine-based, hydrogen-based, or fluorine-based gas.
これ ら の原料ガス を用い る こ と で、 シ リ コ ンを は じめ と する 半導 体ゥエーハを好適にエ ッ チ ングする こ と ができ る。 By using these source gases, semiconductors such as silicon can be used. The body can be suitably etched.
さ ら に本発明 に よれば、 プラ ズマ化した原料ガ ス を ノ ズルを通 じ て半導体 ゥエーハの表面に照射 してエ ッ チングす る プラ ズマエ ッ チ ング装置において、 前記ノ ズルの径が 1 m m〜 2 m mの範囲内にあ る こ と を特徴と する プラ ズマエ ッチ ング装置が提供される。  Further, according to the present invention, in a plasma etching apparatus for irradiating and etching the surface of a semiconductor wafer through a nozzle, the source gas having been converted into a plasma has a diameter of the nozzle. A plasma etching device characterized by being within the range of 1 mm to 2 mm is provided.
こ の よ う な従来に無い小径の ノ ズルを具備する プラ ズマエ ツ チ ン グ装置を用いれば、 半導体 ゥエーハの周辺部分の狭い領域だけ を局 所的にエ ッ チングする こ と ができ 、 前記本発明に係 る加工方法に好 適に使用でき る。  By using such a plasma etching device having an unprecedented small-diameter nozzle, it is possible to locally etch only a narrow area around the semiconductor wafer. It can be suitably used for the processing method according to the present invention.
以上説明 した よ う に、 本発明 では、 半導体 ゥエ ーハの周辺部分の 研磨圧を中央部分よ り 小 さ く して研磨布に摺接さ せて研磨する こ と によ り 周辺部分が盛 り 上がっ た形状 と し、 次いで、 研磨した表面 を 周辺部分のみをプラ ズマエ ッチ ングする こ と によ り ゥエーハの周辺 部分まで優れた平坦度を達成す る こ と ができ る。 ま た、 従来の よ う に ゥエーハ全面を走査 してプラ ズマエ ッ チングす る 必要が無 く 、 へ ィ ズ レベルを改善する た め の鏡面研磨も 必要無いため 、 高いス ルー プ ッ ト でゥエーハを加工する こ と 力 Sでき る。  As described above, in the present invention, the polishing pressure at the peripheral portion of the semiconductor wafer is made smaller than that at the central portion, and the peripheral portion is polished by being brought into sliding contact with the polishing cloth. By forming a raised shape and then subjecting the polished surface to plasma etching only at the peripheral portion, excellent flatness can be achieved up to the peripheral portion of the wafer. Also, unlike the conventional method, it is not necessary to scan the entire surface of the wafer and perform plasma etching, and it is not necessary to perform mirror polishing to improve the haze level. Can be processed.
本発明に よ り 得 られた鏡面 ゥエーハは、 周辺部分も含めた表面全 体に回路を形成 させる こ と ができ 、 半導体デパイ ス の生産性及び歩 留 り を向上 させる こ と ができ る。 図面の簡単な説明  With the mirror surface wafer obtained by the present invention, a circuit can be formed on the entire surface including the peripheral portion, and the productivity and yield of semiconductor devices can be improved. BRIEF DESCRIPTION OF THE FIGURES
図 1 は、 プラ ズマエ ッチ ングの一例を示す概略図である。  FIG. 1 is a schematic diagram showing an example of plasma etching.
図 2 は、 本発明 に係 る装置を用いて ゥエーハの周辺部分だけをプ ラ ズマエ ッチングする一例の概略図であ る。  FIG. 2 is a schematic diagram showing an example of plasma etching only the peripheral portion of the wafer using the apparatus according to the present invention.
図 3 は、 ゥエーハ ょ り 小径の保持板で ゥエーハ を保持 して研磨す る概略を示す図であ る。  FIG. 3 is a diagram schematically showing polishing of the wafer while holding the wafer with a holding plate having a smaller diameter than the wafer.
図 4 は、 実施例 1 のプラ ズマエ ッ チング前後に測定 した ゥエーハ の周辺部分の厚 さ の変位量を示すグラ フであ る。 Fig. 4 shows the results obtained before and after the plasma etching in Example 1. This is a graph showing the amount of displacement of the thickness of the peripheral part of.
図 5 は、 実施例 2 及ぴ比較例で測定した ゥ エーハの周辺部分の厚 さ の変位量を示すグ ラ フ である。  FIG. 5 is a graph showing the displacement of the thickness of the periphery of the wafer measured in Example 2 and Comparative Example.
図 6 は、 従来の半導体ゥ エーハの一般的な製造工程を示 した流れ 図であ る。  FIG. 6 is a flowchart showing a general manufacturing process of a conventional semiconductor wafer.
図 7 は、 従来の研磨工程において ゥエーハ を研磨布で研磨 した後 の周辺部分の厚 さ の変位量を示すグラ フ であ る。 発明を実施するための最良の形態  FIG. 7 is a graph showing the displacement of the thickness of the peripheral portion after polishing the wafer with a polishing cloth in the conventional polishing process. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の実施の形態について図面を参照 しなが ら さ ら に具 体的に説明する が、 本発明 はこれ ら に限定される も の ではない。  Hereinafter, embodiments of the present invention will be described more specifically with reference to the drawings, but the present invention is not limited thereto.
まず、 研磨される ま での半導体ゥエーハの製造工程を説明する と First, the manufacturing process of the semiconductor wafer before polishing is described.
、 チ ヨ ク ラ ルス キ ー法 （ C Z 法）、 浮遊帯域溶融法 （ F Z 法） 等に よ り シ リ コ ン等の原料融液か ら成長 させた半導体イ ンゴ ッ ト をス ラ イ ス して ゥエーノヽ と する。 次いで、 得られた ゥエーハの粗面取 り と ラ ッ ビ ングを行っ た後、 ゥエーハ表面の加工歪等 を除去する ため、 エ ッ チングが行われる。 なお、 ラ ッ ピングに代え て平面研削を行 う 場合も あ る。 A semiconductor ingot grown from a silicon or other raw material melt by the chiral key method (CZ method) or the floating zone melting method (FZ method) is sliced. And say “Eno”. Next, after performing rough surface chamfering and rubbing of the obtained wafer, etching is performed to remove processing distortion and the like on the wafer surface. In some cases, surface grinding is performed instead of wrapping.
こ の よ う な工程を経た ゥエーハは、 表面を よ り 平坦化及び鏡面化 する ために表面研磨が施 される が、 本発明では、 研磨工程で ゥエー ハ周辺部分が盛 り 上がっ た形状 とする。  The wafer that has undergone such a process is subjected to surface polishing in order to make the surface more flat and mirror-finished, but in the present invention, the wafer is formed into a shape in which the periphery of the wafer is raised in the polishing process. .
従来の一般的な研磨方法によ り ゥエーハ裏面全体を保持板で保持 して研磨布に摺接させて研磨する と 、 ゥエーハ周辺部分が過剰に研 磨されて周辺ダ レが発生する場合が多い。  When the entire backside of the wafer is held by a holding plate and polished by a conventional general polishing method, the peripheral portion of the wafer is often excessively polished, causing peripheral sagging. .
そ こ で、 本発明では、 半導体 ゥエーハの周辺部分の研磨圧を中央 部分よ り 小さ く して研磨する こ と に よ り 周辺部分の研磨代を少な く して周辺部分が盛 り 上がっ た形状と する。  Therefore, in the present invention, the polishing pressure at the peripheral portion of the semiconductor wafer is set to be smaller than that at the central portion, thereby reducing the polishing allowance at the peripheral portion and increasing the peripheral portion. And
周辺部分の研磨圧を小 さ く す る方法は特に限定 されないが、 ゥェ の背面 （裏面） に ゥ 中央部分よ り 周辺部分で薄い背面 コ 一 ト膜を形成し、 背面 コー ト膜を介 して ゥエーハ背面を従来の保持 板で保持 して ゥ ハ表面を研磨す る方法ゃ ゥ ハ周辺部分の押 圧力を中央部分か ら独立に制御でき る研磨ヘ ッ ド （保持板） を用 い て研磨する方法な どが考え られ る。 背面部分の研磨剤のまわ り 込み や周辺部分を盛 り 上げる量な どを気に しな ければ簡単な方法 と して 、 図 3 で示 され る よ う に ゥ ハ Wよ り 小径の保持板 6 で ゥ The method for reducing the polishing pressure in the peripheral portion is not particularly limited. 薄 い A thin back coat film is formed on the back (rear side) from the center rather than the center, and ゥ The back of the wafer is held by a conventional holding plate via the back coat film. Method (1) (2) (3) Polishing using a polishing head (holding plate) that can control the pressing force at the peripheral part independently from the central part is conceivable. If you don't care about the amount of abrasive pouring in the back part or the amount that the surrounding part is raised, it is a simple method to keep the diameter smaller than W as shown in Fig. 3. In plate 6 ゥ
Wを保持し、 定盤 7 上に貼 り 付けた研磨布 8 に研磨剤を供給する と と も に、 所定の研磨圧 （押圧） でゥ ハ Wを研磨布 8 に摺接 させ て研磨すればよ い。 こ の よ う に ゥ ハを保持して研磨を行えば、 保持板の保持面か ら はみ出すゥ 周辺部分の研磨圧は中央部分 よ り 小 さ く な る ため、 その分研磨代 も少な く なる。 一方、 保持板 6 の保持面に当接す る ゥ ハ Wの中央部分の厚さ はほぼ均一 と な つ て高い平坦度が達成 され、 研磨後は周辺部分が盛 り 上がっ た形状の ゥ ハを得る こ と ができ る。 While holding W, the polishing agent is supplied to the polishing cloth 8 stuck on the surface plate 7 and, at a predetermined polishing pressure (pressure), the W is slid into contact with the polishing cloth 8 for polishing. You should. In this way, if the polishing is carried out while holding the blade, it protrudes from the holding surface of the holding plate.Because the polishing pressure in the peripheral part is smaller than that in the central part, the polishing allowance is reduced accordingly. . On the other hand, the thickness of the central portion of W, which is in contact with the holding surface of the holding plate 6, is almost uniform, achieving high flatness, and the peripheral portion is raised after polishing. Can be obtained.
上記の よ う に研磨して周辺部分が盛り 上がっ た形状 と した ゥェ一 ハは、 次いでその盛 り 上がっ た周辺部分のみ を局所的にプラ ズマェ ツチングする。 従来のプラ ズマエ ッ チングでは、 予め ゥ ハ全面 の各位置におけ る厚 さ を光学干渉法や静電容量法で測定 し、 ゥ ハ全体が均一な厚 さ と な る よ う に ゥ ハ全面を走査 して測定値に 応じたエ ッチングを行っ ていたが、 本発明では周辺の盛 り 上がっ た 部分だけをプラ ズマェ ツチングする。  As described above, the wafer that has been polished into a shape with a raised peripheral portion is then locally plasma-etched only on the raised peripheral portion. In conventional plasma etching, 厚 the thickness at each position on the entire surface is measured in advance by an optical interference method or a capacitance method, and ゥ the entire surface is made uniform so that the entire thickness becomes uniform. While scanning was performed according to the measured value, according to the present invention, only the surrounding raised portion is plasma-etched.
プラ ズマエ ッ チ ングする領域に関 して は、 上記の よ う に周辺部分 の盛 り 上がっ た部分だけを測定値に応じてエ ッチ ングすればよ いが 、 研磨布に よ り 研磨する際、 前記 し たよ う に小径の保持板等で ゥェ ーハを保持して研磨する こ と で、 ゥエーハ外周端部から 5 m m よ り ゥ ハの内側では優れた平坦度を達成する こ と ができ る ので、 ゥ ハの外周端部か ら 5 m m以内の領域をプラ ズマエ ッ チングすれ ば、 ゥエーハ全面で高い平坦度を達成す る こ と ができ る。 As for the region to be plasma etched, only the raised portion of the peripheral portion needs to be etched according to the measured value as described above, but it is polished with a polishing cloth. At this time, by holding and polishing the wafer with a small-diameter holding plate or the like as described above, excellent flatness can be achieved within 5 mm from the outer peripheral edge of the wafer. The area within 5 mm from the outer edge of the ゥ C can be plasma etched. For example, high flatness can be achieved over the entire wafer.
また、 プラ ズマエ ッ チングに使用する ノ ズルに関 しては、 従来の も の の う ち 、 比較的小径の 3 m n！〜 5 m m程度の径を有する も の を 使用する こ と も一応可能だが、 ゥエーノヽ周辺 5 m mの幅に対 して こ のよ う な大き さ の ノ ズルを用いたの では、 結局高精度なエ ッチ ング 加工が困難であ る。 したがっ て本発明では、 径が 1 m m〜 2 m mの 範囲内 にあ る ノ ズルか らプラ ズマ化 した原料ガス を照射 してプラ ズ マエ ッ チングを行 う こ と で、 狭い面積単位で非常に高精度にエ ッ チ ングする こ と ができ る上、 周辺部分だけのエ ッチ ングであ る の で高 いス ループ ッ ト で ゥエーハをカ卩ェす る こ と ができ る。 すなわち 、 本 発明でプラ ズマエ ッ チングを行 う場合、 従来の ノ ズル径よ り 細い、 l m ni ~ 2 m mの範囲内の径を有す る ノ ズルを具備 したプラ ズマェ ツチング装置を用い る こ と で、 ゥエ ーハ周辺部分のみを よ り 好適に エ ッチングする こ と ができ る。  As for the nozzles used for plasma etching, the diameter of 3 mm is relatively small among the conventional ones. Although it is possible to use one with a diameter of about 5 mm, it is possible to use a nozzle of such a size for a width of 5 mm around the ヽ eno, but ultimately high accuracy Difficult etching processing is difficult. Therefore, in the present invention, plasma etching is performed by irradiating a plasma-processed raw material gas from a nozzle having a diameter in a range of 1 mm to 2 mm, thereby achieving very small area units. In addition to being able to perform high-precision etching, since only the peripheral portion is etched, the wafer can be removed with a high throughput. That is, when plasma etching is performed in the present invention, a plasma etching apparatus provided with a nozzle having a diameter smaller than the conventional nozzle diameter and having a diameter in the range of lmni to 2 mm is used. As a result, only the periphery of the wafer can be more suitably etched.
ま た、 ノ ズルの形状については特に限定す る も の ではない。 上記 の よ う に直径が 1 〜 2 m mであ る小径の 円形 ノ ズルの他に も 1 辺が 1 ~ 2 m mの長方形の ノ ズル等でも よ い。 ゥエーハ周辺部の外周 に 沿っ た形状にする こ と によ っ て効率的に処理する こ と も でき る。  Further, the shape of the nozzle is not particularly limited. In addition to the small diameter circular nozzle having a diameter of 1 to 2 mm as described above, a rectangular nozzle having a side of 1 to 2 mm may be used.ゥ Efficient treatment can also be achieved by forming the shape along the outer periphery of the periphery of the wafer.
なお、 原料ガス をプラ ズマ化する 方法 と しては特に限定されず、 ノ ズル と 一体 と なっ た高周波電極に高周波を印加する方式、 あ る い はマイ ク 口 波を ノ ズルに当 て る方式等のいずれの方式も採用する こ と ができ る。  The method of plasma-forming the raw material gas is not particularly limited, and a method of applying a high frequency to a high-frequency electrode integrated with the nozzle or a method of applying a microwave to the nozzle is used. Any method such as the method can be adopted.
図 2 は、 本発明 にかかる装置を用 いて ゥエーハの周辺部分のみ を プラ ズマエ ッ チングする場合の一例の概略を示 している。 研磨に よ り 周辺部分が盛 り 上がった形状の原料ゥエーハ Wを回転テーブル 4 上に静電チャ ッ ク で固定して回転さ せる と と も に、 照射口 の径が 1 〜 2 m mの ノ ズル 5 にマイ ク ロ 波を 当 てて原料ガス をプラ ズマィ匕 し 、 こ れを ゥエーハ Wの周辺部分だけに照射させる こ と で容易 に ゥェ ーハ周辺部分のみをエ ッチングする こ と ができ る。 FIG. 2 schematically shows an example of a case where only the peripheral portion of the wafer is plasma-etched using the apparatus according to the present invention. The raw material ゥ E-W, whose peripheral part is raised by polishing, is fixed on the rotating table 4 with an electrostatic chuck and rotated, and the diameter of the irradiation port is 1 to 2 mm. Microwaves are applied to the spill 5 to plasmically irradiate the raw material gas, and this is radiated only to the peripheral portion of the wafer W, thereby facilitating the processing. Only the surrounding area can be etched.
本発明 でプラ ズマエ ッチ ングする際に使用する原料ガス と して は 、 従来使用 してい る も の を限定する こ と な く 使用 でき る が、 具体的 には、 C C 1 4等の塩素系、 H 2等の水素系、 または S F 6等の フ ッ 素系のガ ス を使用でき 、 特に、 シ リ コ ン ゥエ ーハを加工す る場合に は、 S F 6 を好適に使用でき る。 As the raw material gas used in the plastics Zumae pitch ring in the present invention, even you are using conventional to Ru can Do rather used as this limiting the. Specifically, chlorine, such as CC 1 4 System, hydrogen gas such as H 2 , or fluorine gas such as SF 6 can be used.In particular, SF 6 can be suitably used when processing silicon wafers. You.
本発明 に よれば、 原料ゥエー ノヽを高いス ループ ッ ト で加工 し、 周 辺部分ま で非常に優れた平坦度の鏡面ゥエーハを提供する こ と がで き る ので、 ゥエ ーハの生産性及び良品率を著 し く 向上させる こ と が でき る。 また、 こ の よ う な ゥエ ーハを用いる こ と で表面全体に回路 を形成 させる こ と ができ 、 半導体デバイ ス の生産性及び歩留 り を著 し く 向上させる こ と ができ る。  According to the present invention, it is possible to process a raw material ヽ Ano で at a high throughput and to provide a mirror surface ゥ A having a very excellent flatness to a peripheral portion, thereby producing an ハ Ea ハ. Quality and non-defective rate can be significantly improved. In addition, by using such a wafer, a circuit can be formed over the entire surface, and the productivity and yield of semiconductor devices can be significantly improved.
ま た、 周辺部分だけをプラ ズマエ ッチ ングする ので、 研磨面全体 のヘイ ズ レベルはほ と ん ど低下せず、 プラ ズマェ ツ チング後にヘイ ズを除去するための鏡面研磨等を行 う 必要も無い。  In addition, since only the peripheral portion is plasma etched, the haze level of the entire polished surface is hardly reduced, and it is necessary to perform mirror polishing or the like to remove haze after plasma etching. Not even.
以下、 実施例及び比較例 を示 して本発明 を よ り 具体的に説明す る が、 本発明はこれ ら に限定 される も の ではない。  Hereinafter, the present invention will be described more specifically with reference to Examples and Comparative Examples, but the present invention is not limited thereto.
(実施例 1 ) (Example 1)
イ ン ゴ ッ ト をス ラ イ ス し て得たシ リ コ ンゥエー ハ （径 ： 2 0 0 m m ) を ゥエーハ周辺部分の研磨圧力が調節でき る研磨へ ッ ド （保持 板） を用い吸着保持し、 ゥエ ーハ周辺部 （特に外周端部か ら 3 m m ) を中心部 よ り 弱い圧力で保持 し、 ゥエ ーハ表面 を研磨布に摺接 さ せて研磨を行 う こ と で鏡面研磨 ゥエ ーハ （ S F Q R m a x ： 0 . 2 0 μ m ) を得た。 S F Q R m a x と は、 ゥエ ーハ上の全サイ ト の S F Q R の中の最大値を表 してい る。  The silicon wafer (diameter: 200 mm) obtained by slicing the ingot is suction-held using a polishing head (holding plate) that can adjust the polishing pressure around the wafer. By holding the periphery of the wafer (especially 3 mm from the outer edge) at a lower pressure than that of the center, the wafer surface is slid against the polishing cloth for polishing. A mirror-polished wafer (SFQR max: 0.20 μm) was obtained. S FQR max represents the maximum value of S FQR of all sites on the wafer.
こ の鏡面研磨 ゥエーハの外周端部か ら 1 2 m m以内の領域の厚 さ を測定 し、 測定値に基づいてプ ラ ズマエ ッチング した。 なお、 厚 さ 測定を周辺部分のみ と した結果、 測定にかかる時間 も 、 ゥエ ーハ全 面を測定する場合に比べ短縮する こ と ができ た。 The thickness of the area within 12 mm from the outer edge of the mirror-polished wafer was measured, and plasma etching was performed based on the measured values. In addition, thickness As a result of measuring only the peripheral portion, the time required for the measurement can be reduced as compared with the case where the entire surface of the wafer is measured.
プ ラ ズマエ ッ チング前 （原料形状） と 後 （加工後形状） の ゥエ ー ハ周辺部分の厚 さ変位量 （除外領域 ： 周辺 2 m m ) を静電容量式厚 さ測定器を用いて測定 し、 結果を図 4 に示 した。  Measure the thickness displacement (excluded area: 2 mm around) of the wafer periphery before and after plasma etching (raw material shape) and after (processed shape) using a capacitance-type thickness gauge. Figure 4 shows the results.
図 4 に示 されてい る よ う に、 プラ ズマエ ッ チング後の ゥェ一ハ周 辺部分の厚さ は、 周辺部分の除外領域に至る ま で平坦化 されてい る と 同時に、 狭い範囲内での平坦度を示す S F Q R m a x も研磨後の 0 . 2 0 /1 111カ ら 0 . '0 5 μ ιηに大幅に改善 されてい る こ と 力 Sわ力 る。  As shown in Fig. 4, the thickness around the wafer after plasma etching is flattened to the exclusion area of the peripheral area, and at the same time, within a narrow range. The SFQR max, which indicates the flatness of the surface, is also significantly improved from 0.20 / 111 after polishing to 0.5 μμηη.
(実施例 2 ) (Example 2)
イ ン ゴ ッ ト をス ラ イ ス し て得たシ リ コ ン ゥ エ ーハ （径 ： 2 0 0 m m ) を ゥエ ーハ周辺部分の研磨圧力 が調節でき る研磨ヘ ッ ド （保持 板） を用い吸着保持 し、 ゥ エ ーハ周辺部 （特に外周端部か ら 3 m m ) を中心部よ り 弱い圧力で保持 し、 ゥエ ーハ表面 を研磨布に摺接 さ せて研磨を行 う こ と で鏡面研磨 ゥエ ー ノヽ （ S F Q R m a x ： 0 . 2 0 M m ) を得た。  A silicon head (diameter: 200 mm) obtained by slicing an ingot is used to hold a polishing head (holding) that can adjust the polishing pressure around the wafer. Plate), hold the wafer at the periphery (especially 3 mm from the outer peripheral edge) with a lower pressure than the center, and slide the wafer surface against the polishing cloth for polishing. Then, a mirror-polished anode (SFQR max: 0.20 Mm) was obtained.
こ の鏡面研磨ゥエ ーハの研磨 した面の う ち 、 ゥエ ーハ外周端部か ら 5 m m以内の領域の厚 さ を測定し、 測定値に基づいてプ ラ ズマェ ッチングした。  The thickness of an area within 5 mm from the outer edge of the wafer was measured on the polished surface of the mirror-polished wafer, and plasma etching was performed based on the measured value.
プ ラ ズマエ ッチング前 （原料形状） と 後 （加工後形状） の ゥエ ー ハ周辺部分の厚 さ分布 （除外領域 ： 周辺 2 m m ) を静電容量式厚 さ 測定器を用いて測定 し、 結果を図 5 に示 した。 なお、 エ ッ チング時 間は 1 0 秒であっ た。  The thickness distribution (exclusion area: 2 mm around the periphery) of the wafer before and after plasma etching (raw material shape) and after (processed shape) was measured using a capacitance-type thickness measuring instrument. The results are shown in FIG. The etching time was 10 seconds.
ま た、 ゥエーノヽ表面のヘイ ズ レべノレをノ ーテイ ク ノレカ ウ ンタ ー （ In addition, the haze level on the {Eno} surface is changed to a notch counter (
L S — 6 0 0 0 P M T H V = 9 0 0 V換算） を用いて測定した。 (比較例） LS-600 PMTHV = 900 V conversion). (Comparative example)
実施例 2 と 同様にシ リ コ ンゥエ ーハの鏡面研磨を行い、 鏡面研磨 ゥエ ーハ （ S F Q R m a x ： 0 . 2 0 μ m ) を得た。  Mirror polishing of the silicon wafer was performed in the same manner as in Example 2 to obtain a mirror polished wafer (SFQRmax: 0.20 μm).
電極径 5 O m mのプラ ズマエ ッチング装置を用 い、 鏡面研磨ゥェ 一 ノヽの研磨した面全体をプラ ズマエ ッチ ング し （エ ッ チング時間 ： 5 0 秒）、 実施例 2 と 同様に ゥ エ ーハ周辺部分の厚 さ 分布 と ヘイ ズ レベルを測定した。  Using a plasma etching device with an electrode diameter of 5 O mm, the entire polished surface of the mirror-polished surface was plasma-etched (etching time: 50 seconds). The thickness distribution and haze level around the wafer were measured.
図 5 は、 実施例 2 のプラ ズマエ ッ チング前後、 及び比較例の各 ゥ エーハの周辺部分の厚 さ変位量を外周端部か ら 1 O m mの位置を基 準 と して示 した グラ フ であ る。 こ の図力 ら、 比較例で得 られた ゥ ェ ーハは一見実施例 2 の ゥエ ーハ よ り も平坦度が改善されている よ う に見え る が、 ゥエ ーハ外周端部か ら約 4 m m と 8 m mの位置に変異 点力 Sあ り 、 S F Q R m a x は 0 . 1 5 μ ιη と い う 大き い値を示 して いる。 一方、 実施例 2 で得 られた ゥエ ーハは、 外周端部か ら 1 0 m m以内の領域での厚 さ変位量が比較例よ り 大き いが変位点がな く 、 S F Q R m a x は 0 . 0 Ί μ m と い う 小 さい値を示し、 局所的な領 域の平坦度が大幅に改善されている。  FIG. 5 is a graph showing the amount of thickness displacement before and after plasma etching in Example 2 and in the peripheral portion of each wafer of the comparative example based on a position 1 mm from the outer peripheral edge. It is. From this drawing force, the wafer obtained in the comparative example appears to have improved flatness at first glance compared to the wafer of Example 2; At about 4 mm and 8 mm from this point, there is a variation point force S, and the SFQR max shows a large value of 0.15 μιη. On the other hand, in the wafer obtained in Example 2, the thickness displacement in the region within 10 mm from the outer peripheral end was larger than that of the comparative example, but there was no displacement point, and SFQR max was 0. It shows a small value of 0 Ί μm, and the flatness of the local area is greatly improved.
ま た、 ゥエ ーハ表面のヘイ ズ レベルについては、 実施例 2 では 4 0 ビ ッ ト と い う 小 さ い値であっ たの に対 し、 比較例では 1 0 4 ビ ッ ト と い う 高い値を示 し、 ヘイ ズを除去す る研磨を しな ければ使用 で き ないも のであ っ た。 なお、 本発明 は、 上記実施形態に限定 される も の ではない。 上記 実施形態は単な る例示であ り 、 本発明の特許請求の範囲に記載 さ れ た技術的思想 と 実質的に同一な構成を有 し、 同様な作用効果を奏す る も のは、 いかな る も のであっ ても 本発明の技術的範囲に包含 され る。 Also, © for Hay's level of error over the leaf surface, against to was small have values that would have a 4 0 bit in the second embodiment, 1 0 4 bit and have the comparative example The value was so high that it could not be used without polishing to remove the haze. Note that the present invention is not limited to the above embodiment. The above-described embodiment is merely an example, and any one having substantially the same configuration as the technical idea described in the claims of the present invention and having the same effect will be described. Anything is included in the technical scope of the present invention.
例 えば、 前記実施の形態ではシ リ コ ン ゥエ ーハ を加工する場合を 例に説明 したが、 本発明が適用 でき る半導体 ゥエ ーハはこれに限定 されず、 S O I ゥエ ーハの ほか、 シ リ コ ン以外の材質から な る 半導 体ゥエ ーハに対 し て も適用 でき る。 ま た、 ゥエ ーハの大き さ に関 し ても特に限定 される も の ではな く 、 本発明は大口 径の ゥエ ーハほ ど 有効であ る。 For example, in the above-described embodiment, a case where a silicon wafer is processed is described. Although described in the examples, the semiconductor wafer to which the present invention can be applied is not limited to this. In addition to SOI wafers, semiconductor wafers made of materials other than silicon can be used. It can be applied to this. Further, the size of the wafer is not particularly limited, and the present invention is more effective for a large-diameter wafer.
また、 ゥエ ーハ周辺部分を盛 り 上がっ た形状と する方法は特に限 定されず、 実施例の よ う に研磨へ ッ ドに よ っ て周辺部 と 中心部の加 ェ圧力 を別 々 に調整する方法以外に も 、 ゥエ ーハ保持部分が ゥエ ー ハ径ょ り も小径の研磨へ ッ ドを使用 し研磨す る方法や、 ゥエ ーハ裏 面に樹脂等の保護膜を コーテ ィ ング して、 そ の周辺部のみコーテ ィ ングする厚 さ を薄 く し、 ゥエ ーハ裏面を吸着保持 して研磨する こ と な どでも ゥエ ーハ周辺部分が盛 り 上がっ た形状に加工する こ と がで さ る。  In addition, the method for forming the peripheral portion of the wafer into a raised shape is not particularly limited, and the pressure applied to the peripheral portion and the central portion is separately determined by a polishing head as in the embodiment. In addition to the method of adjusting the height of the wafer, a method of polishing the wafer holding part using a polishing head with a smaller diameter than the wafer diameter, or a method of protecting the wafer backside with resin or other protective film In order to reduce the thickness to coat only the periphery of the wafer, and to hold and hold the backside of the wafer by suction, the periphery of the wafer rises. It can be processed into a different shape.
また、 研磨工程後にプラ ズマエ ッ チング工程を追加する が、 本発 明のプラ ズマエ ッ チ ングは、 研磨工程後、 つま り 仕上げ鏡面研磨ェ 程後に行っ て も 、 多段研磨の 1 次鏡面研磨後 に行っ て も 良い。 こ れ らの研磨に よ り ゥエ ーハ周辺部分を盛 り 上が っ た形状にした後、 プ ラ ズマエ ッチングを行 う こ と に よ り 高平坦度な ゥエ ーハに加工でき る。  Although a plasma etching step is added after the polishing step, the plasma etching of the present invention can be performed after the polishing step, that is, after the finishing mirror polishing step, but after the primary mirror polishing of the multi-step polishing. You may go to After polishing, the surrounding area of the wafer is raised to a protruding shape, and then plasma etching can be performed to achieve a highly flat wafer. .

Claims

請 求 の 範 囲 The scope of the claims
1 . 半導体 ゥエ ーハの表面を所定の研磨圧で研磨布に摺接させて 研磨 し、 該研磨 した表面をプラ ズマエ ッ チングす る半導体 ゥエーハ の加工方法において、 前記半導体ゥエ ーハの周辺部分の研磨圧を 中 央部分よ り 小 さ く して研磨する こ と に よ り 周辺部分が盛 り 上がっ た 形状 と し、 該周辺部分のみをプラ ズマエ ッチ ングする こ と を特徴 と する半導体ゥエ ーハの加工方法。 1. A method of processing a semiconductor wafer in which a surface of the semiconductor wafer is polished by bringing the surface of the semiconductor wafer into sliding contact with a polishing cloth at a predetermined polishing pressure, and the polished surface is plasma-etched. The polishing pressure of the peripheral part is set smaller than that of the central part, so that the peripheral part has a raised shape, and only the peripheral part is plasma-etched. Semiconductor wafer processing method.
2 . 前記半導体ゥエ ーハのプラ ズマエ ッチ ングする周辺部分が、 該ゥエ ーハの外周端部から 5 m m以内の領域であ る こ と を特徴と す る請求項 1 に記載の半導体ゥエ ーハの加工方法。 2. The semiconductor wafer according to claim 1, wherein a peripheral portion of the semiconductor wafer for plasma etching is a region within 5 mm from an outer peripheral end of the wafer. Processing method for semiconductor wafers.
3 . 前記プラ ズマエ ッチ ングを、 径が Ι ιη π！ 〜 2 m mの範囲内 に ある ノ ズルか ら プラ ズマ化 した原料ガス を照射して行 う こ と を特徴 とする請求項 1 ま たは請求項 2 に記載の半導体ゥエ ーハの加工方法 3. The plasma etching is performed with a diameter of ιιη π! 3. The method for processing a semiconductor wafer according to claim 1, wherein the plasma is irradiated with a source gas which has been plasmatized from a nozzle within a range of about 2 mm.
4 . 前記プラ ズマエ ッチングに用いる原料ガス が、 塩素系、 水素 系、 ま たはフ ッ素系のガス であ る こ と を特徴 とする請求項 1 ない し 請求項 3 のいずれか 1 項に記載の半導体 ゥエ ーハの加工方法。 4. The method according to any one of claims 1 to 3, wherein the raw material gas used for the plasma etching is a chlorine-based, hydrogen-based, or fluorine-based gas. The semiconductor wafer described in the above.
5 . プラ ズマ化 した原料ガス をノ ズルを通 じて半導体ゥエ ーハの 表面に照射 してエ ッ チングする プラ ズマエ ッ チング装置において、 前記ノ ズルの径が 1 m m 〜 2 m mの範囲内に ある こ と を特徴と す る プラ ズマエ ッ チ ング装置。 5. In a plasma etching apparatus for irradiating the plasma by irradiating the surface of the semiconductor wafer through the nozzle with the plasma-formed source gas, the diameter of the nozzle ranges from 1 mm to 2 mm. A plasma etching device characterized by being located inside.
PCT/JP2001/005402 2000-06-29 2001-06-25 Semiconductor wafer processing method and plasma etching apparatus WO2002001617A1 (en)

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