JP3371392B2 - Manufacturing method of bonded SOI substrate - Google Patents

Manufacturing method of bonded SOI substrate

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Publication number
JP3371392B2
JP3371392B2 JP34361895A JP34361895A JP3371392B2 JP 3371392 B2 JP3371392 B2 JP 3371392B2 JP 34361895 A JP34361895 A JP 34361895A JP 34361895 A JP34361895 A JP 34361895A JP 3371392 B2 JP3371392 B2 JP 3371392B2
Authority
JP
Japan
Prior art keywords
polishing
manufacturing
soi substrate
insulating film
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP34361895A
Other languages
Japanese (ja)
Other versions
JPH09102540A (en
Inventor
弘 佐藤
芳宏 宮沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP34361895A priority Critical patent/JP3371392B2/en
Publication of JPH09102540A publication Critical patent/JPH09102540A/en
Application granted granted Critical
Publication of JP3371392B2 publication Critical patent/JP3371392B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Element Separation (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、貼り合わせSOI
(Silicon on insulator) 基板の製造方法、特にウエハ
全体に均一な厚さで島状半導体層を形成できる貼り合わ
せSOI基板の製造方法に関するものである。
TECHNICAL FIELD The present invention relates to a bonded SOI.
(Silicon on insulator) The present invention relates to a method for manufacturing a substrate, particularly a method for manufacturing a bonded SOI substrate capable of forming an island-shaped semiconductor layer with a uniform thickness on the entire wafer.

【0002】[0002]

【従来の技術】絶縁体の表面に薄膜単結晶シリコン層を
形成してなる所謂SOI基板を用いて、超LSIを製造
する開発が進められている。各種のSOI基板の製造方
法の中でも最も結晶性が良く、特性面でも優れていると
考えられるものに貼り合わせ方式によるSOI基板の製
造方法がある。このSOI基板の製造方法の工程を図3
に示した。このSOI基板の製造方法を図3を参照しな
がら簡単に説明する。
2. Description of the Related Art Development of a VLSI using a so-called SOI substrate in which a thin film single crystal silicon layer is formed on the surface of an insulator is under development. Among the various SOI substrate manufacturing methods, the one that is considered to have the best crystallinity and the excellent characteristics is the bonding method of the SOI substrate. FIG. 3 shows the steps of the method for manufacturing the SOI substrate.
It was shown to. A method of manufacturing this SOI substrate will be briefly described with reference to FIG.

【0003】図3Aに示したように、表面が鏡面に仕上
げられた単結晶シリコンウエハである素子形成基板1の
その表面にフォトリソグラフィー技術を用いて、複数の
凹凸部2からなる所定のパターンが段差で形成されてい
る。これらの凹凸部2に上部絶縁膜3Aと下部絶縁膜3
Bとが連続して形成されている絶縁膜3、例えば、Si
2 膜を形成し、更に段差を埋めるために全面に平坦化
用の層、例えば、多結晶シリコン層4を形成し、この多
結晶シリコン層4の表面を平坦研磨する。
As shown in FIG. 3A, a predetermined pattern composed of a plurality of concave and convex portions 2 is formed on the surface of an element forming substrate 1 which is a single crystal silicon wafer having a mirror finished surface by using a photolithography technique. It is formed by steps. An upper insulating film 3A and a lower insulating film 3 are formed on these uneven portions 2.
An insulating film 3 formed continuously with B, for example, Si
An O 2 film is formed, a flattening layer, for example, a polycrystalline silicon layer 4 is formed on the entire surface to further fill the step, and the surface of the polycrystalline silicon layer 4 is flatly polished.

【0004】次に、図3Bに示したように、その平坦化
された多結晶シリコン層4の表面に、例えば、別の鏡面
に仕上げられたシリコンウエハの支持基板5を貼り合わ
せ、その支持基板5を所定の厚さまで研削した、素子形
成基板1と支持基板5との貼り合わせからなる貼り合わ
せ基板7を作製する。その後、図3Cに示したように、
絶縁膜3の内の上部絶縁膜3Bを研磨ストッパーにし
て、単結晶シリコンウエハである素子形成基板1を、そ
の裏面から研磨し、SiO2 の絶縁膜3で分離された複
数の島状シリコン薄層6を有する貼り合わせSOI基板
8を得ている。
Next, as shown in FIG. 3B, a supporting substrate 5 of, for example, another mirror-finished silicon wafer is attached to the flattened surface of the polycrystalline silicon layer 4, and the supporting substrate 5 is attached. 5 is ground to a predetermined thickness, and a bonded substrate 7 is manufactured by bonding the element forming substrate 1 and the supporting substrate 5. Then, as shown in FIG. 3C,
Using the upper insulating film 3B of the insulating film 3 as a polishing stopper, the element forming substrate 1 which is a single crystal silicon wafer is polished from the back surface thereof, and a plurality of island-shaped silicon thin films separated by the insulating film 3 of SiO 2 are formed. A bonded SOI substrate 8 having a layer 6 is obtained.

【0005】なお、図3Cの貼り合わせSOI基板8は
同図Bの貼り合わせ基板7を上下反転させた状態で示さ
れている。従って、図3Bにおける上部絶縁膜3A及び
下部絶縁膜3Bは、図3Cにおいては、それぞれ下部絶
縁膜3A及び上部絶縁膜3Bとなる。説明の紛らわしさ
を避けるために、以下の説明では、図3Cの貼り合わせ
SOI基板8の状態で、上方に在る絶縁膜3Bを上部絶
縁膜と呼ぶことにする。
The bonded SOI substrate 8 in FIG. 3C is shown in a state in which the bonded substrate 7 in FIG. 3B is turned upside down. Therefore, the upper insulating film 3A and the lower insulating film 3B in FIG. 3B become the lower insulating film 3A and the upper insulating film 3B in FIG. 3C, respectively. In order to avoid ambiguity in the description, in the following description, in the state of the bonded SOI substrate 8 of FIG. 3C, the insulating film 3B located above will be referred to as an upper insulating film.

【0006】ところで、前記貼り合わせSOI基板8の
製造工程において、支持基板5を貼り合わせた後の素子
形成基板1の研磨は、SiO2 膜の凹部内の島状シリコ
ン薄層6を如何に凹部周辺のSiO2 膜の上部絶縁膜3
Bと同一平面に、平坦で且つ研磨ダメージがないように
仕上げられるかにかかっている。
By the way, in the process of manufacturing the bonded SOI substrate 8, polishing of the element forming substrate 1 after bonding the support substrate 5 is performed by forming the island-shaped silicon thin layer 6 in the recess of the SiO 2 film into a recess. Upper insulating film 3 of peripheral SiO 2 film
It depends on whether it is finished on the same plane as B and is flat and free from polishing damage.

【0007】図4に図3Bに示した工程における貼り合
わせ基板7を上下反転させた状態で再度掲載した。そし
て研磨前の単結晶シリコンウエハである素子形成基板1
には、その前の研削精度から、図示のようにマクロな厚
みむらが生じている。例えば、厚みが厚い方では5〜1
0μm程度、厚みが薄い方では1μm程度の厚みむらが
ある。
FIG. 4 shows the laminated substrate 7 in the step shown in FIG. 3B upside down again. The element formation substrate 1 which is a single crystal silicon wafer before polishing
In this case, due to the grinding accuracy before that, a macro thickness unevenness is generated as shown in the figure. For example, the thicker one is 5-1
There is unevenness of about 0 μm, and about 1 μm in the thinner one.

【0008】[0008]

【発明が解決しようとする課題】従来、このような厚み
むらのある素子形成基板1を前記のように研磨するに当
たっては、この素子形成基板1を部分研磨法または選択
研磨法のどちらかのみを用いて仕上げられていた。前者
の部分研磨法は、素子形成基板1の前記厚みむらを無く
し、その厚みを均一にしようとする加工であって、素子
形成基板1の表面を、その一部分づつ研磨加工ヘッドで
走査しながら研磨し、続いて次の一部分を研磨する場合
には直前に研磨した部分の一部分に重なるようにして順
次研磨して行く方法である。この場合に使用する研磨液
としては遊離砥粒を含む研磨液を用い、その遊離砥粒で
化学的研磨より物理的研磨が勝った研磨を行う。この部
分研磨法のみで素子形成基板1の表面を研磨すると、図
5に示したように、研磨加工ヘッドの前記走査の重なり
部分によるミクロな厚みむら9Aが生じてしまい、素子
形成領域である島状シリコン薄層6に厚みむらを与えて
しまうという問題点があった。前記ミクロな厚みむら9
Aは他の部分より10〜100nm程度薄くなってしま
う。
Conventionally, in polishing the element forming substrate 1 having such a thickness unevenness as described above, the element forming substrate 1 is subjected to only a partial polishing method or a selective polishing method. It was finished using. The former partial polishing method is a process for eliminating the thickness unevenness of the element forming substrate 1 and making the thickness uniform, and polishing the surface of the element forming substrate 1 part by part with a polishing head while scanning. Then, in the case of polishing the next portion, the method is to sequentially polish so as to overlap a portion of the portion that has just been polished. As the polishing liquid used in this case, a polishing liquid containing free abrasive grains is used, and the free abrasive grains are used for polishing in which physical polishing is superior to chemical polishing. When the surface of the element forming substrate 1 is polished only by this partial polishing method, as shown in FIG. 5, microscopic thickness unevenness 9A due to the overlapping portion of the scanning of the polishing processing head occurs, and the island which is the element forming region is formed. There is a problem in that the silicon thin layer 6 is uneven in thickness. The micro uneven thickness 9
A becomes thinner than other parts by about 10 to 100 nm.

【0009】また、選択研磨法は、本出願人が出願し、
平成2年11月1日に公開された公開特許平2−267
939「研磨方法」の公開特許公報にその一研磨方法が
披瀝されているが、素子形成基板1の被研磨面全面を同
時に研磨し、上部絶縁膜3Bが存在する平面で同時に研
磨が終了する研磨方法である。
The applicant has applied for the selective polishing method,
Published Japanese Patent Application No. 2-267 published on November 1, 1990
One of the polishing methods is shown in Japanese Patent Laid-Open No. 939 "polishing method", but the entire surface to be polished of the element forming substrate 1 is polished at the same time, and polishing is simultaneously completed on the plane where the upper insulating film 3B is present. Is the way.

【0010】この選択研磨法を実行できる研磨装置10
を図7に示した。この研磨装置10は回転するウエハホ
ルダ11と、研磨定盤12の平面に研磨パッド13を貼
り付けてなる回転する研磨盤14とから構成されてい
る。この研磨装置10を用いて貼り合わせ基板7を研磨
する場合には、ウエハホルダ11に貼り合わせ基板7
を、その素子形成基板1側を下側にしてワックスで接
着、または真空吸着で固定し、研磨パッド13に素子形
成基板1の被研磨面を当接せしめて、ノズル15から研
磨液Lを供給しながら前記被研磨面全面の研磨を同時に
行う。この場合の研磨液LはSiO2 の上部絶縁膜3B
とは化学反応せず、単結晶シリコンと化学反応するアル
カリ性溶液の研磨液、或いは遊離砥粒を含有するアルカ
リ性溶液の研磨液が用いられ、物理的な研磨よりも化学
的な研磨が勝る研磨を行う。また、研磨パッド13とし
てはセラミック板などの超硬質定盤からスウェードタイ
プの発泡ポリウレタンの軟質クロスなど、必要に応じて
各種硬度のものが用いられる。
A polishing apparatus 10 capable of executing this selective polishing method.
Is shown in FIG. The polishing apparatus 10 is composed of a rotating wafer holder 11 and a rotating polishing platen 14 in which a polishing pad 13 is attached to a flat surface of a polishing platen 12. When the bonded substrate stack 7 is polished by using the polishing apparatus 10, the bonded substrate stack 7 is attached to the wafer holder 11.
Is adhered with wax with the element forming substrate 1 side facing down or fixed by vacuum suction, the surface to be polished of the element forming substrate 1 is brought into contact with the polishing pad 13, and the polishing liquid L is supplied from the nozzle 15. Meanwhile, the entire surface to be polished is polished at the same time. In this case, the polishing liquid L is the upper insulating film 3B of SiO 2.
Does not chemically react with, but uses a polishing solution of an alkaline solution that chemically reacts with single crystal silicon or a polishing solution of an alkaline solution containing free abrasive grains. To do. Further, as the polishing pad 13, various hardnesses such as a super hard surface plate such as a ceramic plate to a soft cloth of suede type foamed polyurethane are used as needed.

【0011】この研磨装置10を用いた選択研磨法のみ
では、図6に示したように、マクロな厚みむらによって
生じる部分的な過剰研磨が避けられず、厚みむら9B、
9C、9Dが生じ、同一平面に仕上げることができなか
った。
As shown in FIG. 6, partial overpolishing caused by macroscopic unevenness in thickness cannot be avoided only by the selective polishing method using the polishing apparatus 10, and uneven thickness 9B,
9C and 9D occurred, and it was not possible to finish on the same plane.

【0012】従って、前記島状シリコン薄層6の厚みは
20nm〜100nm程度であるので、前記のような厚
みむら9A或いは厚みむら9B、9C、9Dが生じる
と、所望の良好な素子を形成することができないという
問題点があった。それ故、本発明はこのような問題を解
決しようとするものであって、SiO膜などの絶縁膜
の凹部内の島状シリコン薄層を、凹部周辺の絶縁膜の上
部絶縁膜と同一平面に、平坦で且つ研磨ダメージがない
ように研磨仕上することができる貼り合わせSOI基板
の製造方法を得ることを目的とするものである。
Therefore, since the thickness of the island-shaped silicon thin layer 6 is about 20 nm to 100 nm, when the thickness unevenness 9A or the thickness unevenness 9B, 9C, 9D as described above occurs, a desired good element is formed. There was a problem that I could not do it. Therefore, the present invention is intended to solve such a problem, in which an island-shaped silicon thin layer in a recess of an insulating film such as a SiO 2 film is flush with the upper insulating film of the insulating film around the recess. Another object of the present invention is to provide a method for manufacturing a bonded SOI substrate which is flat and can be polished and finished without polishing damage.

【0013】[0013]

【課題を解決するための手段】それ故、本発明の貼り合
わせSOI基板の製造方法では、素子形成基板の表面に
上部絶縁膜と下部絶縁膜とからなる絶縁段差により複数
の凹部パターンが形成され、そしてそれら凹部内に素子
形成領域が島状に残るように、前記凹部外に在る前記素
子形成基板を研磨するに当たり、先ず、部分研磨法によ
り前記上部絶縁膜に達する直前まで絶縁段差凹部外に在
る前記素子形成基板を研磨し、その後、選択研磨法によ
り前記上部絶縁膜を研磨ストッパーとして前記残余の素
子形成基板を研磨する研磨方法を採って、前記課題を解
決した。
Therefore, in the method for manufacturing a bonded SOI substrate of the present invention, a plurality of concave patterns are formed on the surface of the element forming substrate by the insulating step formed by the upper insulating film and the lower insulating film. Then, in polishing the element forming substrate outside the recess so that the element forming regions remain in the recesses in the form of islands, first, by a partial polishing method, an insulating step outside the concave is formed until just before reaching the upper insulating film. The above problem is solved by polishing the element formation substrate present in 1) and then polishing the remaining element formation substrate using the upper insulating film as a polishing stopper by a selective polishing method.

【0014】従って、本発明の貼り合わせSOI基板の
製造方法を採れば、島状シリコン薄層を、凹部周辺の絶
縁膜の上部絶縁膜と同一平面に、平坦で且つ研磨ダメー
ジがないように研磨仕上することができる。
Therefore, according to the method of manufacturing the bonded SOI substrate of the present invention, the island-shaped silicon thin layer is polished on the same plane as the upper insulating film around the recess so as to be flat and free from polishing damage. Can be finished.

【0015】[0015]

【発明の実施の形態】次に、図1及び図2を参照しなが
ら、本発明の貼り合わせSOI基板の製造方法の実施例
を説明する。図1は本発明の貼り合わせSOI基板の製
造方法を説明するための製造工程図であり、そして図2
は本発明の貼り合わせSOI基板の製造方法の一実施例
を説明するためのプラズマエッチング法の概念図であ
る。なお、従来のSOI基板の構成部分と同一の構成部
分には同一の符号を付して説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a method for manufacturing a bonded SOI substrate of the present invention will be described with reference to FIGS. FIG. 1 is a manufacturing process diagram for explaining a method for manufacturing a bonded SOI substrate of the present invention, and FIG.
FIG. 3 is a conceptual diagram of a plasma etching method for explaining an example of a method for manufacturing a bonded SOI substrate of the present invention. The same components as those of the conventional SOI substrate are designated by the same reference numerals in the following description.

【0016】図1において、同図Aは図3Bの貼り合わ
せ基板7を上下反転させたものであり、また、図4と同
一の貼り合わせ基板7である。この研磨前の貼り合わせ
基板7は、前記のように、素子形成基板1の厚みに研削
などの加工精度から面内で厚みむらが生じている。その
マクロな厚みむらは、例えば、厚みが厚い方では5〜1
0μm程度、厚みが薄い方では1μm程度のむらである
ことは前記した。
In FIG. 1, FIG. 1A shows the laminated substrate 7 of FIG. 3B turned upside down, and is the same laminated substrate 7 as in FIG. As described above, in the bonded substrate 7 before polishing, the thickness of the element forming substrate 1 has in-plane thickness unevenness due to processing accuracy such as grinding. The macro thickness unevenness is, for example, 5-1 for thicker ones.
As described above, the unevenness is about 0 μm and about 1 μm for the thinner one.

【0017】このような厚みむらがある貼り合わせ基板
7を面内均一性良く仕上げるには、次のような研磨方法
を採ることが最適であることが判った。即ち、先ず最初
に部分研磨加工を行う。この部分研磨加工では、部分加
工前の厚みむらがある素子形成基板1に対して、その表
面に前記の部分研磨法を施し、前記上部絶縁膜に達する
直前まで絶縁段差凹部外に在る前記素子形成基板を研磨
し、その面内のマクロな厚みむらを減少させる。その
後、選択研磨法により前記上部絶縁膜を研磨ストッパー
として残余の前記素子形成基板を研磨することである。
It has been found that the following polishing method is optimal for finishing the bonded substrate 7 having such uneven thickness with good in-plane uniformity. That is, first, partial polishing is performed. In this partial polishing process, the surface of the element-formed substrate 1 having partial thickness unevenness before the partial processing is subjected to the above-described partial polishing method, and the element existing outside the insulating step concave portion until just before reaching the upper insulating film. The formed substrate is polished to reduce in-plane macroscopic thickness unevenness. Then, the remaining element formation substrate is polished by the selective polishing method using the upper insulating film as a polishing stopper.

【0018】この発明の研磨方法を実施するに当たって
は、先ず、部分研磨加工を施す前に、素子形成基板1の
厚さ測定をその全面で行い、コンピュータに記憶させ
る。その後、部分研磨加工を開始するのであるが、この
部分研磨加工では、前記コンピュータの指示に基づき、
素子形成基板1より小口径の加工ヘッドによって素子形
成基板1の表面を部分的に走査し、その素子形成基板1
を研磨する。
In carrying out the polishing method of the present invention, first, before the partial polishing process is performed, the thickness of the element forming substrate 1 is measured on the entire surface and stored in the computer. After that, the partial polishing process is started. In this partial polishing process, based on the instructions of the computer,
The surface of the element forming substrate 1 is partially scanned by a processing head having a smaller diameter than the element forming substrate 1, and the element forming substrate 1
To polish.

【0019】この小口径の加工ヘッドを用いて素子形成
基板1の表面を部分的に走査して研磨する、この部分研
磨加工では、遊離砥粒を含む研磨液を用いる。この研磨
液を用いた場合は、その砥粒で化学的な研磨より物理的
な研磨が勝った研磨が行われる。この研磨の加工速度は
自動コントロールされ、厚みむらが修正される。
The surface of the element forming substrate 1 is partially scanned and polished by using this small-diameter processing head. In this partial polishing processing, a polishing liquid containing loose abrasive grains is used. When this polishing liquid is used, physical polishing is performed with the abrasive grains rather than chemical polishing. The processing speed of this polishing is automatically controlled, and the uneven thickness is corrected.

【0020】前記遊離砥粒を含む研磨液を用いた、この
部分研磨加工は、マクロな厚みむらを修正するのに適し
た方法であるが、ミクロに見た場合には段落〔000
7〕に記したような欠点をもっているので、本発明にお
いては、この部分研磨加工では、研磨前のマクロな厚み
むらを除くだけの研磨加工を行う。即ち、図1Bに示し
たように、この部分研磨加工は、上部絶縁膜3Bに達す
る直前まで絶縁段差凹部外に在る前記素子形成基板1を
研磨し、研磨加工ヘッドの走査の重なり部分によるミク
ロな厚みむら9Aの深さが上部絶縁膜3Bに達する前の
段階で必ず停止さす。
This partial polishing process using a polishing liquid containing the above-mentioned loose abrasive grains is a method suitable for correcting macroscopic thickness unevenness, but when viewed microscopically, paragraph [000] is used.
7], the partial polishing process according to the present invention is performed only by removing the macroscopic unevenness in thickness before polishing. That is, as shown in FIG. 1B, in this partial polishing process, the element forming substrate 1 existing outside the insulating step concave portion is polished until just before reaching the upper insulating film 3B, and the micro processing is performed by the overlapping portion of the scanning of the polishing processing head. It is always stopped before the depth of the uneven thickness 9A reaches the upper insulating film 3B.

【0021】本発明においては、前記のような遊離砥粒
を含んだ研磨液を用いる部分研磨加工に代えて、プラズ
マエッチング法やイオンミリング法による部分加工を行
ってもよい。中でもプラズマエッチング法は、図2に示
したようなプラズマエッチング装置20を用いて行うこ
とができる。即ち、このプラズマエッチング装置20は
真空チャンバ(不図示)内に設けられた、陽極21が装
着されたプラズマ加工ヘッド22と陰極23と、これら
陽極21及び陰極23間に接続された高周波電圧源24
などから構成されている。そしてこの実施例において
は、前記プラズマ加工ヘッド22が固定されている形式
のプラズマエッチング装置20であるものとする。
In the present invention, instead of the partial polishing process using the polishing liquid containing free abrasive grains as described above, a partial process by a plasma etching method or an ion milling method may be performed. Above all, the plasma etching method can be performed by using the plasma etching apparatus 20 as shown in FIG. That is, the plasma etching apparatus 20 is provided in a vacuum chamber (not shown), a plasma processing head 22 having an anode 21 mounted thereon, a cathode 23, and a high-frequency voltage source 24 connected between the anode 21 and the cathode 23.
Etc. In this embodiment, it is assumed that the plasma processing head 22 is a fixed type plasma etching apparatus 20.

【0022】このような構成のプラズマエッチング装置
20を用い,所謂PACE法(Plasma-Assisted Chemic
al Etching)で加工を行う。この手法を用いて、前記貼
り合わせ基板7の素子形成基板1を部分加工する場合に
は、陰極23の表面に素子形成基板1面を上向きにして
貼り合わせ基板7を載置し、そして、例えば、CF4
どのガスを真空チャンバー内に供給し、その真空チャン
バー内を1Toll以上の高ガス圧にし、高周波電圧源
24から高周波電圧を前記陽極21及び陰極23間に印
加してCF4 をプラズマ化する。図2中、符号Pはその
プラズマを指す。そして1〜50μm/minのエッチ
ングレートで等方性プラズマエッチングを行う。この加
工時に、貼り合わせ基板7を同一平面内で順次X−Y方
向に移動させる。そうすることにより素子形成基板1の
表面全面を等方性プラズマにより化学的にエッチングす
ることができる。
Using the plasma etching apparatus 20 having such a structure, the so-called PACE method (Plasma-Assisted Chemic) is used.
al Etching). When the element forming substrate 1 of the bonded substrate 7 is partially processed using this method, the bonded substrate 7 is placed on the surface of the cathode 23 with the surface of the element forming substrate 1 facing upward, and, for example, , CF 4 or the like is supplied into the vacuum chamber, the inside of the vacuum chamber is set to a high gas pressure of 1 Toll or more, and a high frequency voltage is applied from the high frequency voltage source 24 between the anode 21 and the cathode 23 to generate CF 4 plasma. Turn into. In FIG. 2, the symbol P indicates the plasma. Then, isotropic plasma etching is performed at an etching rate of 1 to 50 μm / min. During this processing, the bonded substrate stack 7 is sequentially moved in the XY direction within the same plane. By doing so, the entire surface of the element formation substrate 1 can be chemically etched by isotropic plasma.

【0023】このプラズマエッチング装置20を用いた
場合にも、前記遊離砥粒を含んだ研磨液で部分研磨加工
を行った時に生じた厚みむら9Aとほぼ同様の厚みむら
が生じるものである。即ち、プラズマ加工ヘッド22で
素子形成基板1の表面を一度走査した帯状部分の一方の
側縁を、次の走査が重なるようにして、プラズマ加工ヘ
ッド22で次の帯状のエッチング部分を走査して行くも
のであるので、素子形成基板1の表面の前記走査の重な
り部分では、図1Bに示したような厚みむら9Aが生じ
るものである。
Even when this plasma etching apparatus 20 is used, the thickness unevenness is almost the same as the thickness unevenness 9A generated when the partial polishing process is performed with the polishing liquid containing the loose abrasive grains. That is, the plasma processing head 22 scans the next strip-shaped etched portion so that one side edge of the strip-shaped portion that has once scanned the surface of the element forming substrate 1 overlaps the next scan. Therefore, the thickness unevenness 9A as shown in FIG. 1B occurs in the overlapping portion of the scanning on the surface of the element forming substrate 1.

【0024】従って、このプラズマエッチング装置20
を用いて、前記貼り合わせ基板7の表面を部分加工する
場合も、図1Bに示したように、上部絶縁膜3Bに達す
る直前まで絶縁段差凹部外に在る前記素子形成基板1を
エッチングし、プラズマ加工ヘッド22の走査の重なり
部分によるミクロな厚みむら9Aの深さが上部絶縁膜3
Bに達する前の段階で必ず停止さす。以降の研磨加工は
前記選択研磨加工を用いて仕上げる。このプラズマエッ
チング法による素子形成基板1の表面の加工は遊離砥粒
を含む研磨液を用いた部分研磨加工に比し比較的早いエ
ッチング速度で加工できるので、前記部分加工を能率良
く加工することができる。
Therefore, this plasma etching apparatus 20
Even when the surface of the bonded substrate 7 is partially processed by using, the element forming substrate 1 existing outside the insulating step concave portion until just before reaching the upper insulating film 3B is etched as shown in FIG. 1B, The depth of the microscopic thickness unevenness 9A due to the overlapping portion of the scanning of the plasma processing head 22 is the upper insulating film 3
Be sure to stop before reaching B. The subsequent polishing process is finished by using the selective polishing process. The processing of the surface of the element forming substrate 1 by the plasma etching method can be performed at a relatively high etching rate as compared with the partial polishing processing using a polishing liquid containing loose abrasive grains, so that the partial processing can be processed efficiently. it can.

【0025】またイオンミリング法を用いて部分加工を
行ってもよい。この場合は、化学的な加工が行われる前
記プラズマエッチングによる部分加工とは異なり、遊離
砥粒を含んだ研磨液による部分研磨と同様に、物理的な
研磨が行われる。
Further, partial processing may be performed by using an ion milling method. In this case, unlike the partial processing by the plasma etching in which the chemical processing is performed, the physical polishing is performed similarly to the partial polishing by the polishing liquid containing the loose abrasive grains.

【0026】このようにして、部分研磨加工を終了した
貼り合わせ基板7は、ミクロ的には薄い素子形成基板1
の単結晶シリコン層が残っているものの、マクロ的な厚
みむらは大きく減少し、ほぼ0.05〜0.5μm程度
に修正される。
In this way, the bonded substrate 7 which has been partially polished is microscopically thin element forming substrate 1.
Although the single crystal silicon layer of No. 1 remains, the macroscopic thickness unevenness is greatly reduced and is corrected to about 0.05 to 0.5 μm.

【0027】次に、本発明においては、部分研磨加工が
終了した貼り合わせ基板7に選択研磨加工が施される。
選択研磨加工は、上部絶縁膜3Bを殆ど研磨せず、素子
形成基板1の単結晶シリコン層のみを研磨する必要性か
ら、砥粒を殆ど含まないアルカリ系研磨液を用い、物理
的な研磨よりも化学的な研磨が勝った研磨を行う。例え
ば、エチレンジアミンやアンモニアなどは容易に使用で
きるものである。また、選択研磨機としては、一般的な
片面用鏡面研磨機を用いてよい。
Next, in the present invention, the selective polishing process is performed on the bonded substrate 7 after the partial polishing process is completed.
In the selective polishing process, since it is necessary to polish only the single crystal silicon layer of the element forming substrate 1 without polishing the upper insulating film 3B, an alkaline polishing liquid containing almost no abrasive grains is used and physical polishing is performed. Even chemical polishing is superior to polishing. For example, ethylenediamine and ammonia can be easily used. Further, as the selective polishing machine, a general one-sided mirror polishing machine may be used.

【0028】この選択研磨加工で上部絶縁膜3Bの表面
まで研磨すると、部分研磨加工で生じたミクロな厚みむ
ら9Aも同時に除去することができる。従って、この選
択研磨加工を行うことにより上部絶縁膜3Bの表面が全
面でほぼ同時に露出するため、図1Cに示したように、
過剰研磨の極めて少ない島状シリコン薄層6が貼り合わ
せ基板7の全面にわたって形成された貼り合わせSOI
基板8を得ることができる。
When the surface of the upper insulating film 3B is polished by this selective polishing process, the microscopic thickness unevenness 9A caused by the partial polishing process can be removed at the same time. Therefore, by performing this selective polishing process, the surface of the upper insulating film 3B is exposed almost at the same time on the entire surface, and as shown in FIG. 1C,
Bonded SOI in which the island-shaped silicon thin layer 6 with extremely little excessive polishing is formed over the entire surface of the bonded substrate 7.
The substrate 8 can be obtained.

【0029】[0029]

【発明の効果】以上、説明したように、本発明の貼り合
わせSOI基板の製造方法によれば、絶縁膜の凹部内の
島状シリコン薄層を、凹部周辺の絶縁膜の上部絶縁膜と
同一平面に、平坦で且つ研磨ダメージなどがないように
表面仕上することができ、歩留りを向上させることがで
きる。また、コンピュータによる自動加工の導入が容易
になる。従って、これらの相乗効果でコストダウンを計
ることができる。
As described above, according to the method for manufacturing a bonded SOI substrate of the present invention, the island-shaped silicon thin layer in the recess of the insulating film is the same as the upper insulating film of the insulating film around the recess. It is possible to finish the surface on a flat surface so that it is flat and free from polishing damage, and the yield can be improved. Moreover, the introduction of automatic processing by a computer becomes easy. Therefore, cost reduction can be achieved by these synergistic effects.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の貼り合わせSOI基板の製造方法を
説明するための製造工程図である。
FIG. 1 is a manufacturing process diagram for explaining a method for manufacturing a bonded SOI substrate of the present invention.

【図2】 本発明の貼り合わせSOI基板の製造方法の
一実施例を説明するためのプラズマエッチング法の概念
図である。
FIG. 2 is a conceptual diagram of a plasma etching method for explaining an example of a method for manufacturing a bonded SOI substrate of the present invention.

【図3】 従来技術の貼り合わせSOI基板の製造方法
を説明するための製造工程図である。
FIG. 3 is a manufacturing process diagram for explaining a method for manufacturing a bonded SOI substrate according to a conventional technique.

【図4】 貼り合わせSOI基板を製造する前の貼り合
わせ基板の形状を説明するための貼り合わせSOI基板
の断面図である。
FIG. 4 is a cross-sectional view of a bonded SOI substrate for explaining the shape of the bonded substrate stack before manufacturing the bonded SOI substrate.

【図5】 図4に示した貼り合わせ基板に従来の手法で
部分研磨加工を施した場合の欠点を説明するための貼り
合わせSOI基板の断面図である。
5 is a cross-sectional view of a bonded SOI substrate for explaining a defect when the bonded substrate shown in FIG. 4 is partially polished by a conventional method.

【図6】 図4に示した貼り合わせ基板に従来の手法で
選択研磨加工を施した場合の欠点を説明するための貼り
合わせSOI基板の断面図である。
6 is a cross-sectional view of a bonded SOI substrate for explaining a defect when the bonded substrate shown in FIG. 4 is subjected to selective polishing by a conventional method.

【図7】 従来の選択研磨加工用研磨装置の一部断面図
である。
FIG. 7 is a partial cross-sectional view of a conventional polishing apparatus for selective polishing processing.

【符号の説明】[Explanation of symbols]

1 素子形成基板 2 凹凸部 3 絶縁膜 3A 下部絶縁膜(図1において) 3B 上部絶縁膜(図1において) 4 多結晶シリコン層 5 支持基板 6 島状シリコン薄層 7 貼り合わせ基板 8 貼り合わせSOI基板 9A 部分研磨加工による厚みむら 9B 選択研磨加工による厚みむら 9C 選択研磨加工による厚みむら 9D 選択研磨加工による厚みむら 1 element formation substrate 2 uneven parts 3 insulating film 3A Lower insulating film (Fig. 1) 3B Upper insulating film (in FIG. 1) 4 Polycrystalline silicon layer 5 Support substrate 6 Thin silicon layer 7 Laminated substrate 8 Bonded SOI substrate 9A Thickness unevenness due to partial polishing 9B Thickness unevenness due to selective polishing 9C Thickness unevenness due to selective polishing Thickness unevenness due to 9D selective polishing

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/762 H01L 21/3065 H01L 27/12 Front page continuation (58) Fields surveyed (Int.Cl. 7 , DB name) H01L 21/762 H01L 21/3065 H01L 27/12

Claims (6)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 素子形成基板の表面に上部絶縁膜と下部
絶縁膜とからなる絶縁段差により複数の凹部パターンが
形成され、そして該凹部内に素子形成領域が島状に残る
ように、前記凹部外に在る前記素子形成基板を加工する
貼り合わせSOI基板の製造方法において、 該製造方法は、 前記上部絶縁膜に達する直前まで絶縁段差凹部外に在る
前記素子形成基板の厚みむらを除去する部分研磨加工工
程と、 該部分研磨加工工程に続いて、前記上部絶縁膜をストッ
パーとして前記残余の素子形成基板の厚みむらを除去す
選択研磨加工工程とからなる加工工程を経て面内厚み
が均一な貼り合わせSOI基板を得ることを特徴とする
貼り合わせSOI基板の製造方法。
1. A plurality of recess patterns are formed on the surface of an element formation substrate by an insulating step made up of an upper insulating film and a lower insulating film, and the recesses are formed so that the element forming regions remain in island shapes in the recesses. A method for manufacturing a bonded SOI substrate for processing the element-forming substrate outside, wherein the manufacturing method removes thickness unevenness of the element-forming substrate outside the insulating step recess until just before reaching the upper insulating film. a partial polishing step, subsequent to the partial polishing step, the upper insulating film uniformity is selected polishing step through the process step consisting of the surface within the thickness of removing uneven thickness of the element forming substrate of the residual as a stopper A method for manufacturing a bonded SOI substrate, which comprises obtaining a bonded SOI substrate.
【請求項2】 前記部分研磨加工工程では主として化学
的に研磨されることを特徴とする請求項1に記載の貼り
合わせSOI基板の製造方法。
2. The method for manufacturing a bonded SOI substrate according to claim 1, wherein the partial polishing process is mainly performed by chemical polishing.
【請求項3】 前記部分研磨加工工程がプラズマエッチ
ングで研磨されることを特徴とする請求項2に記載の貼
り合わせSOI基板の製造方法。
3. The method for manufacturing a bonded SOI substrate according to claim 2, wherein the partial polishing process step is performed by plasma etching.
【請求項4】 前記部分研磨加工工程では主として物理
的に研磨されることを特徴とする請求項1に記載の貼り
合わせSOI基板の製造方法。
4. The method for manufacturing a bonded SOI substrate according to claim 1, wherein the partial polishing process is mainly performed by physical polishing.
【請求項5】 前記部分研磨加工工程がイオンミリング
で研磨されることを特徴とする請求項1に記載の貼り合
わせSOI基板の製造方法。
5. The method for manufacturing a bonded SOI substrate according to claim 1, wherein the partial polishing process step is performed by ion milling.
【請求項6】 前記選択研磨加工工程では、主として化
学的に研磨されることを特徴とする請求項1に記載の貼
り合わせSOI基板の製造方法。
6. The method for manufacturing a bonded SOI substrate according to claim 1, wherein the selective polishing process step is performed mainly by chemical polishing.
JP34361895A 1995-08-02 1995-12-28 Manufacturing method of bonded SOI substrate Expired - Fee Related JP3371392B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34361895A JP3371392B2 (en) 1995-08-02 1995-12-28 Manufacturing method of bonded SOI substrate

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP7-197530 1995-08-02
JP19753095 1995-08-02
JP34361895A JP3371392B2 (en) 1995-08-02 1995-12-28 Manufacturing method of bonded SOI substrate

Publications (2)

Publication Number Publication Date
JPH09102540A JPH09102540A (en) 1997-04-15
JP3371392B2 true JP3371392B2 (en) 2003-01-27

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Country Link
JP (1) JP3371392B2 (en)

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Publication number Priority date Publication date Assignee Title
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