JP2002343972A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten a step caused by the formation of a lower gate electrode accurately and efficiently. SOLUTION: An SiO2 film 10 is so deposited as to fill a recessed part 2 of a stopper film 3 (S10), and a recessed part 12 is formed only in a gate electrode formation section of the SiO2 film 10 (S11). Thereafter, a polysilicon layer 4 is so deposited as to fill the recessed part 12 (S12), and then the polysilicon layer 4 is etched (S14) via a mask 13 (S13) and then polished to be flattened to the same thickness as the SiO2 film 10 to form a gate electrode 14 (S15). Next, a SiO2 film 15 is so deposited as to cover the gate electrode 14, and then hydrogen ions are implanted from the SiO2 film 15 side to form an ion-implanted layer 16 in a semiconductor substrate 1 (S16). Thereafter, a base substrate 8 is laid on the surface of the SiO2 film 15 (S17), heat treatment is conducted to peel off the semiconductor substrate 1 (S18), and only the remaining part of the semiconductor substrate 1 is selectively polished (S19).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI film on an oxide film.
The present invention relates to a method for manufacturing a semiconductor device such as a double-gate MOS transistor formed by forming a layer and forming a lower gate electrode.

[0002]

2. Description of the Related Art An SOI (SILICON ON INSULATOR) substrate has an oxide film functioning as an insulating film formed on a silicon substrate serving as a support substrate, and an SOI layer (semiconductive layer; single-crystal silicon thin film) on the oxide film. ) Is formed. For example, in the case of an SOI substrate having a lower gate electrode (back gate), the SOI substrate is formed by a pattern structure in which the lower gate electrode is covered with an oxide film, so that a step occurs in the oxide film around the lower gate electrode. Semiconductor element and SOI
In order to flatten such a step for the purpose of thinning the layer, polysilicon is deposited on an oxide film so as to remove the step, the polysilicon layer is flattened, and then the base substrate is overlaid. Methods are known.

FIG. 2 is a manufacturing process diagram of an SOI substrate by superimposing a general base substrate. In FIG.
Step S21 is a step of forming a gate oxide film, in which a gate oxide film and a stopper film are formed on the surface of the semiconductor substrate 1 in which the recess 2 has been formed in advance by a trench method or the like so as to fill the recess 2. The SiO ₂ film 3 is formed with a thickness of, for example, about 50 nm by a thermal oxidation method or the like.

[0004] Then, at the gate layer formation step of step S22, as by CVD or the like covering the of SiO ₂ film 3 surface, the polysilicon layer 4, for example a thickness 300nm thickness of about SiO ₂ film 3 Deposits on the surface. And
In the gate layer etching step of step S23, a gate electrode (lower gate electrode (back gate)) 5 is formed on the surface of the SiO ₂ film 3 by etching the polysilicon layer 4 through a resist having a desired pattern. I do.

Step S24 shows an oxide film covering step, in which an SiO ₂ film 6 serving as an insulating film is formed to a thickness of, for example, 600 nm so as to cover the surface of the gate electrode 5.
It is deposited on the surface of the iO ₂ film 3. Thus, the gate electrode 5 has a structure covered with the insulating film. In this structure, Si formed to reflect the shape of the gate electrode 5
The thickness of the step 5a of the O ₂ film 6 is, for example, 350 nm to 40 nm.
It reaches about 0 nm.

Step S25 shows a step of forming a flattening film, in which SiO 2 is formed so as to cover the surface of the step 5a.
₂ A polysilicon layer 7 is deposited on the film 6 by a CVD method or the like. As described above, the thickness of the step 5a is 350 nm to 400 nm.
In the case of about nm, the thickness of the polysilicon layer 7 is 2-3
Although μm is sufficient, it is generally preferable to form it relatively thick to 5 μm.

Next, step S26 shows a flattening step. For example, a polishing pad made of polyurethane foam and a polishing slurry made of colloidal silica (average particle diameter of about 80 nm) are used to form the step 5a. After polishing so as to remove the step 7a of the polysilicon layer 7 reflecting the shape, colloidal silica (average particle diameter 40
The surface of the polysilicon layer 7 is flattened by using a polishing slurry having a thickness of about 10 nm.

Thereafter, in the substrate bonding step shown in step S27, the base substrate 8 is superposed on the flattened surface of the polysilicon layer 7. In this superposition, the surface of the polysilicon layer 7 and the base substrate 8
The surface to be bonded is subjected to RCA cleaning or the like so that particles and the like are not attached, and is subjected to a hydrophilic treatment so that an OH group is present on the surface to be bonded. Further, after the above-mentioned superposition, for example, at a temperature of 1100 ° C. in an oxygen or nitrogen atmosphere.
By performing the heat treatment for 30 minutes to 120 minutes, the bonding between the polysilicon layer 7 and the base substrate 8 can be strengthened.

Step S28 shows a grinding step, in which the surface of the semiconductor substrate 1 is ground to such an extent that damage due to the grinding does not remain in the SOI layer 9 described later. First, after roughing is performed using a diamond grindstone or the like (a grindstone having a grindstone number of about 2,000), the semiconductor substrate 1 is subjected to, for example, a plasma etching method to reduce the thickness of the semiconductor substrate 1 to 2 mm.
Adjust to about 00 nm ± 50 nm.

Then, in the selective polishing step of step S29, for example, a polishing pad and ethylenediamine (Si and S
By selectively polishing the semiconductor substrate 1 using a polishing slurry having a large polishing rate ratio with respect to iO ₂ so that the surface of the step portion (step portion reflecting the concave portion 2) of the SiO ₂ film 3 is exposed, SiO _{2 is} polished. An SOI substrate having the SOI layer 9 formed on the gate electrode 5 via the film 3 can be obtained.

It is known that the resistance can be reduced by forming the polysilicon layer relatively thick (see Japanese Patent Application Laid-Open No. 10-125881).

[0012]

However, when an SOI substrate is manufactured by the method shown in FIG. 2, there are the following problems, for example.

1) In the flattening film forming step as described above,
In order to form a polysilicon layer having a thickness of about 5 μm so as to remove a step having a thickness of about 350 nm to 400 nm, a large amount of time and gas is consumed, and the working efficiency is low and the running cost is high. No. 2-177433).

2) When depositing polysilicon having a thickness of about 5 μm using a CVD apparatus, a large amount of polysilicon is deposited in the CVD furnace. For this reason, it is necessary to periodically clean the inside of the CVD furnace, and the working efficiency is significantly reduced.

3) In the step of forming a flattening film as described above, the polysilicon is thinner at the convex portion of the step and thicker at the concave portion. For this reason, on the surface (joining surface; flattened surface) that overlaps with the base substrate,
The grain sizes of the polysilicon are different from each other, which affects the yield in the substrate bonding process.

4) When depositing polysilicon having a thickness of about 5 μm, a jig (claw) for supporting the substrate (semiconductor substrate 1)
Since polysilicon is also deposited on the periphery, a projection-like foreign matter is formed on the back surface of the semiconductor substrate. Since such foreign matter has an adverse effect in a later step, a step of removing the foreign matter is required, and it takes time and effort.

5) In the polishing step, the grinding step, and the selective polishing step, since a thick semiconductor substrate is ground or polished, the cost increases and the film thickness after polishing becomes non-uniform. As shown in FIG. 3, there is a problem that the SiO ₂ film 3 serving as a stopper film is ground or the semiconductor substrate 1 to be polished remains.

6) Since the polysilicon layer is formed thick in a narrow area, cavities (bubbles) are easily generated by the polysilicon layer, and there is a problem that the yield is reduced.

In addition to the method using polysilicon as shown in FIG. 2, for example, an oxide film (Si
There is known a method in which O ₂ ) is formed thick in advance, the oxide film is planarized, and then a base substrate is superposed (see JP-A-8-153780). However, as described above, in order to cover with a gate electrode oxide film and then flatten and overlay a base substrate, an oxide film having a thickness of about 5 μm is required, and the oxide film must be formed by batch deposition. Therefore, a lot of time and gas are consumed as in the case of the above-mentioned polysilicon layer, and the working efficiency is low and the running cost is high. Further, since an oxide film is formed thick in a narrow region, cavities are easily generated as in the case of using polysilicon, and there is a problem that the yield is reduced.

Oxygen ions are implanted into the entire surface of the semiconductor substrate to
Although it is also known in a method of producing an IO substrate (SIMOX method; see IEICE's IEICE (1997-03)), the oxygen ions cause damage to the substrate, and therefore the There is a problem such as remarkably impairing.

The present invention has been made on the basis of the above-mentioned problem, and it is intended to efficiently and efficiently flatten a step caused by the formation of a lower gate electrode, and to reduce a manufacturing cost such as a running cost in an SOI substrate to reduce a yield. An object of the present invention is to provide a method of manufacturing a semiconductor device to be improved.

[0022]

According to the present invention, in order to solve the above-mentioned problems, the invention according to claim 1 is directed to a lower gate covered with an oxide film (SiO ₂ ) on a semiconductor substrate. After patterning the electrodes, the base substrate is
In a method of manufacturing a semiconductor device formed by forming an OI layer,
A step of performing ion implantation (hydrogen ion implantation) from the oxide film side to form a peeling layer (ion implantation layer) on the semiconductor substrate, and a step of superimposing a base substrate on the oxide film; Removing the semiconductor substrate with the release layer, and selectively polishing the semiconductor substrate remaining on the base substrate side to form the SOI layer.

According to a second aspect of the present invention, after a stopper film (SiO ₂ ) having a step having the same thickness as the SOI layer is formed, and an oxide film is deposited on the stopper film,
The oxide film was patterned to form a recess, a gate layer (polysilicon) was deposited on the oxide film so as to be embedded in the recess, and etching was performed so that the gate layer remained only in the recess. Thereafter, the lower gate electrode is formed by planarization by a CMP method.

When the oxide film is patterned, for example, the oxide film is etched together with a stopper film to expose the surface of the semiconductor substrate to form a recess, and then a predetermined thickness of SiO ₂ is formed on the bottom of the recess by thermal oxidation. The gate layer may be deposited after forming a film or the like.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings.

In the present embodiment, in order to flatten the step caused by the formation of the lower gate electrode with high accuracy and high efficiency in the fabrication of an SOI substrate without using a flattening film such as polysilicon, the lower gate electrode In addition to improving pattern formation, a hydrogen injection separation method (UNIBOND method;
A semiconductor device is manufactured using the IEICE's IEICE (1997-03)))).

FIG. 1 is a schematic process chart showing a method of manufacturing a semiconductor device according to the present embodiment. The same components as those shown in FIG. 2 are denoted by the same reference numerals, and a detailed description thereof will be omitted. In FIG. 1, step S10 indicates an oxide film forming step, and a gate oxide film forming step S10 is performed.
21, the recess 2 of the gate oxide film 3 is formed on the gate oxide film 3 serving as a stopper film manufactured through the same process as that of the stopper film 2.
The SiO ₂ film 10 was deposited by a CVD method or the like so as to fill the gap. For example, the thickness of the concave portion 2 of the semiconductor substrate 1 is set to 30 nm to 120 nm (thickness necessary for forming an SOI layer according to a target device), and the thickness of the gate oxide film 3 is set to 50 nm to 100 nm. And

Step S11 shows an oxide film etching step. First, SiO ₂ reflecting the shape of the concave portion 2 is formed.
Polishing pad (for example, IC1000 + Suba40 manufactured by Rodel Nitta) so as to remove the concave portion 11 of the film 10
0) and a polishing slurry (for example, SC11 manufactured by Cabot)
2), the SiO ₂ film 10 was polished to a predetermined thickness (for example, 300 nm; polished to the same thickness as a target gate electrode) and planarized. Thereafter, only the gate electrode forming portion of the SiO ₂ film 10 is etched and patterned through a predetermined pattern of resist or the like, so that the SiO ₂ film 3 is exposed and the concave portion 1 is formed in the SiO ₂ film 10.
2 was formed.

The above oxide film etching step S11
In, for example, by etching a gate electrode forming portion in the SiO ₂ film 3 and the SiO ₂ film 10,
After the concave portion 12 is formed by exposing the surface of the semiconductor substrate 1, a predetermined thickness of SiO ₂ is formed on the bottom of the concave portion 12 by a thermal oxidation method.
A film (gate oxide film) may be formed.

Step S12 shows a gate layer forming step, in which a polysilicon layer 4 is deposited on the exposed surfaces of the SiO ₂ film 3 and the SiO ₂ film 10 so as to fill the recesses 12 described above. Next, in a mask forming step of step S13, a mask 13 having a predetermined pattern made of SiO ₂ or resist was formed only on the gate electrode forming portion on the polysilicon layer 4. Thereafter, in the gate layer etching step of step S14, etching was performed (plasma etching or the like) so that only the gate electrode forming portion was left in the polysilicon layer 4. Then, in the gate layer flattening step of step S15, the SiO ₂ film 10
The polysilicon layer 4 was planarized and polished by CMP so as to have the same thickness as that of the gate electrode 14 to form a pattern.

Step S16 shows an ion implantation step, which is performed on the gate electrode 14 and the SiO ₂ film 1.
SiO ₂ as a superposition and insulating film on top
After depositing the film 15 by a CVD method or the like, an ion-implanted layer 16 as a release layer was formed in the vicinity of the SiO ₂ film 3 in the semiconductor substrate 1 by implanting hydrogen ions as shown by arrows in FIG. . Note that, for example, the Si
The thickness of the O ₂ film 15 is 300 nm, and the ion-implanted layer 16 is formed at a position approximately 200 nm away from the SiO ₂ film 3 with a uniform depth.

Next, in the substrate bonding step shown in step S17, the base substrate 8 is superimposed on the flattened surface of the SiO ₂ film 15 and, for example, at a temperature of 400 ° C. in an oxygen or nitrogen atmosphere. Temporarily joined by heat treatment. In this substrate bonding step, the Si
The bonding surface between the O ₂ film 15 and the base substrate 8 is, for example, RCA
By cleaning and the like, particles and the like are not attached, and by performing a hydrophilic treatment so that OH groups are present on the joint surface, bubbles are not formed on the joint surface.

Thereafter, in the heat treatment step shown in step S18, the semiconductor substrate 1 to which the base substrate 8 has been joined as described above is subjected to a heat treatment at, for example, 600 ° C. in a nitrogen atmosphere to expand the ion-implanted layer 16, Semiconductor substrate 1
Was stripped from the position of the ion-implanted layer 16. After the semiconductor substrate 1 is peeled as described above, a heat treatment at, for example, 800 ° C. to 1000 ° C. is performed in a nitrogen atmosphere, so that S
The bonding between the iO ₂ film 15 and the base substrate 8 can be strengthened. Further, the peeled surface of the semiconductor substrate 1 can be polished as necessary to reduce the surface roughness, and can be reused in, for example, the substrate bonding step S17.

Then, in the selective polishing step of step S19, a nonwoven fabric substrate cloth (for example,
a polishing pad such as uba400 (having a hardness of 82 according to JIS K-6301)) and a selective polishing slurry such as an ethylenediamine solution (eg, a solution having an ethylenediamine concentration of 0.0005%) (polishing rate ratio with respect to Si and SiO ₂ ) Polishing slurry) having a large SiO ₂ film 3
By selectively polishing only the semiconductor substrate 1 remaining in the heat treatment step S18 so that the surface of the stepped portion (stepped portion reflecting the concave portion 2) is exposed, the SOI is formed on the gate electrode 5 via the SiO ₂ film 3. An SOI substrate on which the layer 17 is formed can be obtained.

In the above-mentioned SOI substrate, for example, a double gate MOS transistor can be manufactured by forming an upper gate electrode and a source electrode, a drain electrode and the like on the SOI layer 17 by a general patterning method. .

By manufacturing an SOI substrate as described above, it is not necessary to use a flattening film such as polysilicon. Therefore, foreign matter caused by deposits in the CVD furnace due to the polysilicon or a substrate supporting jig. Can be suppressed. Further, in the gate layer flattening step, the selective polishing step, and the like, the polished region has an extremely small area (for example, the gate layer etching step S15) as compared with, for example, the method shown in FIG.
Or it becomes a thin area (for example, selective polishing step S19). Furthermore, the bonding between the substrate (Si) and the oxide film (SiO ₂ ) in the substrate bonding step is stronger and more stable than, for example, the bonding between the substrate (Si) and polysilicon (Si) as shown in FIG. It becomes something.

Although the present invention has been described in detail only with respect to the specific examples described above, it will be apparent to those skilled in the art that various modifications and variations are possible within the technical idea of the present invention. It goes without saying that such variations and modifications belong to the scope of the claims.

[0038]

As described above, according to the present invention, it is not necessary to use a flattening film such as polysilicon.
The time and cost required for manufacturing a substrate can be reduced. Also,
In a gate layer flattening step, a selective polishing step, and the like, an extremely small area or a thin region is polished. Further, since the bonding between the substrate (Si) and the oxide film (SiO ₂ ) in the substrate bonding step is strong and stable, an SOI substrate with a good yield can be obtained without generating a cavity or the like at the bonding surface.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of an SOI substrate in this embodiment.

FIG. 2 is a manufacturing process diagram of a general SOI substrate.

FIG. 3 is a schematic configuration diagram of an SOI substrate that has been unevenly ground and polished.

[Explanation of symbols]

1 ... semiconductor substrate 2,11,12 ... recess 3,10,15 ... SiO ₂ film 4 ... polysilicon layer 8 ... base substrate 13 ... mask 14 ... gate electrode 16 ... ion implanted layer 17 ... SOI layer

Claims (2)

[Claims] 1. A method for manufacturing a semiconductor device, comprising: forming a lower gate electrode covered with an oxide film on a semiconductor substrate by patterning; and overlaying a base substrate to form an SOI layer. Forming a release layer on the semiconductor substrate by performing ion implantation from the above; a step of superimposing a base substrate on the oxide film; and removing the semiconductor substrate with the release layer and remaining on the base substrate side. Selectively polishing a semiconductor substrate to form the SOI layer. 2. A stopper film having a step having the same thickness as the SOI layer is formed, an oxide film is deposited on the stopper film, and then the oxide film is patterned to form a concave portion. A gate layer is deposited on the oxide film so as to be embedded in the oxide film, and etched so that the gate layer remains only in the concave portion, and then flattened by a CMP method to form the lower gate electrode. The method for manufacturing a semiconductor device according to claim 1.