JP3147073B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for electrically isolating element regions by using a trench isolation method, and more particularly, to a method of removing a mask material and a pad oxide film thereunder. The edge of the oxide film embedded in the groove is formed thicker than near the center, and in the subsequent etching process,
The present invention relates to a method for suppressing the occurrence of a depression at the edge of a groove.

[0002]

2. Description of the Related Art As a method of isolating an element in a semiconductor device, a method of selectively forming an oxide film in an element isolation region has been proposed.
With the COS method, a groove (trench) is formed in the element isolation region,
There is known a groove separation method in which an insulating material is embedded in a groove to perform separation.

The LOCOS oxide film requires a relatively large area for element isolation, and there is a problem that if the element isolation width is 500 nm or less, it cannot be properly isolated. In addition, the silicon oxide film becomes convex upward with respect to the silicon substrate surface due to volume expansion during oxidation, and a step is formed on the substrate surface. Such a step will occur in a later step.
This may cause uneven exposure, abnormal exposure, disconnection, and the like.

In order to solve this problem, Japanese Patent Laid-Open No. 8-213449
No., LOCO is inserted in a shallow groove formed in the silicon substrate.
By forming an S oxide film, LOCO with little step
A technique for forming an S oxide film has been disclosed. However, even with this technique, the point that the element isolation region has a large area cannot be improved.

Therefore, recently, a groove separation method has been widely used for element separation. FIG. 7 shows a manufacturing process of a semiconductor device using the groove separation method. In this manufacturing process, first, FIG.
1A, a pad oxide film 2 and a silicon nitride film 3 are sequentially formed on the surface of a silicon substrate 1, and then the silicon nitride film 3, the pad oxide film 2 and the silicon substrate 1 are formed by dry etching. A groove is formed by etching away. After removing the resist, a silicon oxide film 5 is formed so as to fill the groove. Next, the convex silicon oxide film 5 is polished as shown in FIG.

Next, as shown in FIG. 7C, the silicon nitride film 3 is removed, the pad oxide film 2 is further removed, and the surface of the silicon oxide film 5 is processed to be substantially flush with the substrate 1. In the semiconductor element formed by this method, when the pad oxide film 2 is removed, the etching of the silicon oxide film 5 proceeds from the upper surface and the side surface of the silicon oxide film 5, so that the boundary between the groove and the silicon oxide film 5 is formed. Partial etching proceeds excessively. As a result, as shown in FIG.
A depression 6 having a depth of 50 nm to 100 nm is formed in the silicon oxide film 5 at the end of the groove (periphery of the groove). The depression 6 causes two problems.

[0007] The first problem is that since there is a large inclination angle in the recess 6, the etching residue is apt to occur in a later step. For example, as shown in FIGS. 8A and 8B, a gate oxide film 2 'is formed, a polysilicon 9 is deposited, and then the polysilicon 9 is patterned to form a gate line. As shown by the plane, the depression 6
In some cases, the gate line is short-circuited due to the remaining polysilicon 10.

The second problem is that due to this step, a step remains on the surface of a film formed in a later step, and exposure deviation tends to occur at the time of lithography, and contrary to the recent improvement in resolution of lithography, the size of each part is reduced. Will fluctuate.

In order to solve these problems, for example,
Japanese Patent Application Laid-Open No. 8-330410 discloses a technique in which a dent is formed at the upper edge of a groove, and an insulator having an etching ratio with the insulating material embedded in the groove can be embedded in the dent. However, in this method, it is necessary to embed an insulator of a material different from that of the insulator in the groove in the recess, which increases the number of manufacturing steps.
Further, since the insulator and the insulator have different etching rates, when the insulator is planarized in a later step, the insulator remains as it is, and unevenness is formed on the surface thereof.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made by a trench isolation method capable of reducing a depression at an edge of an oxide film embedded in a trench by a relatively simple process. An object of the present invention is to provide a method for manufacturing a device. Another object of the present invention is to provide a method for manufacturing a semiconductor device having an element isolation region having a small area and a small step.

[0011]

In order to achieve the above object, a method of manufacturing a semiconductor device according to a first aspect of the present invention is directed to a method of manufacturing a semiconductor device of a trench isolation type, wherein a pad oxide film is formed on a silicon substrate. Forming a silicon nitride film on the pad oxide film, etching the silicon nitride film, the pad oxide film, and a predetermined region of the silicon substrate sequentially to form a groove, and forming a silicon oxide in the groove. Using a CMP (Chemical Mechanical Polisher) device,
Polished in the first stage of polishing.
The shape is formed, and the curved shape is formed by the second stage polishing, and the groove is formed.
The peripheral portion is formed in a shape higher than the central portion of the silicon nitride film, the silicon nitride film is removed by etching, the pad oxide film is removed by wet etching, and the silicon oxide embedded in the trench is formed on the silicon substrate. The projecting portion is substantially removed.

According to this method, when the pad oxide film is removed by wet etching, the surface portion of the silicon oxide buried in the groove undergoes etching from the upper surface and the etching from the side surface. Since the surface portion of the silicon oxide film embedded in the trench is formed in a predetermined shape in which the peripheral portion is higher than the central portion of the groove, the progress of etching from the upper surface can be offset by the thickness of this edge portion, and the thickness from the upper surface side. Etching does not proceed very much. Therefore, it can be reduced to a shallower and gentler one than the conventional depression.

A semiconductor according to a second aspect of the present invention
The method of manufacturing a device is a method of manufacturing a semiconductor device of a groove separation system.
A pad oxide film is formed on a silicon substrate,
Forming a silicon nitride film on the pad oxide film;
At the place of the silicon nitride film, the pad oxide film, and the silicon substrate
A constant area is sequentially etched to form a groove, and a silicon
Silicon buried in the trenches and buried in the oxide
First, the surface of the oxide is hardened to a predetermined hardness using a CMP apparatus.
The silicon nitride film and the first polishing pad
The first step of polishing silicon and silicon oxide is performed.
Using a second polishing pad softer than the predetermined hardness
Polishing the silicon nitride film and silicon oxide
By performing the second stage polishing, the periphery of the groove is
The edge is formed in a high shape, and the silicon nitride film is etched.
And removed by wet etching.
Pad oxide film is removed and embedded in the groove.
A portion of silicon oxide protruding above the silicon substrate
And substantially eliminating the minute components.

A semiconductor according to a third aspect of the present invention
The method of manufacturing a device is a method of manufacturing a semiconductor device of a groove separation system.
A pad oxide film is formed on a silicon substrate,
Forming a silicon nitride film on the pad oxide film;
At the place of the silicon nitride film, the pad oxide film, and the silicon substrate
A constant area is sequentially etched to form a groove, and a silicon
Silicon buried in the trenches and buried in the oxide
First, the surface portion of the oxide is hardened to a hardness of 80 to 100 according to JISA.
Using a CMP apparatus with a first polishing pad
Polishing of the first stage is performed, and then 75 to 90
Using a CMP apparatus having a second polishing pad having hardness
By performing the second stage polishing, from the center of the groove
The periphery is formed in a high shape, and the silicon nitride film is etched.
And removed by wet etching.
The pad oxide film is removed and embedded in the trench.
Silicon oxide projecting above the silicon substrate
A portion is substantially removed.

[0015] As an abrasive for an oxide film, PH10-1
Those containing silica in about 2 are generally used. When such an abrasive is used, the polishing rate of the silicon nitride film is about 1/4 of the polishing rate of the silicon oxide film. Therefore, the boundary between the silicon nitride film and the silicon oxide film is hardly polished. Polishing proceeds near the center of the groove, away from the edge of the film. Therefore, according to this method, a curved shape can be formed in the silicon oxide film.

In the first stage polishing, the silicon oxide
Forming the surface of the compound into a flat shape, and polishing the second stage
Then, the surface of the silicon oxide is formed into a curved shape.
Is desirable.

In the first stage polishing, the polishing is performed according to JISA.
Using a first polishing pad having a hardness of ~ 100,
In the second stage polishing, a hardness of 75-90 by JISA
It is desirable to use a second polishing pad.

The polishing in the second stage is performed by removing silicon in the trench.
The difference between the film thickness at the trench edge and the film thickness at the center at the oxide surface
Can be terminated when it becomes about 50-100 nm
desirable.

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device for performing element isolation by using a trench isolation method according to an embodiment of the present invention will be described below with reference to the drawings.

[First Embodiment] A first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS.

In this manufacturing method, first, the silicon substrate 1 shown in FIG. 1A is thermally oxidized to form a pad oxide film 2 having a thickness of about 20 nm as shown in FIG. A silicon nitride film 3 is formed on 2. FIG.
As shown in (c), a predetermined area of the silicon nitride film 3 is covered with a resist 4 and the resist 4 is used as a mask.
The silicon nitride film 3, the pad oxide film 2, and the silicon substrate 1 are sequentially etched by a dry etching method to form a groove 21 having a depth of about 400 nm in the silicon substrate 1. After the resist 4 is removed, as shown in FIG.
Bias CV so as to embed (fill) 1
The silicon oxide film 5 is formed to a thickness of, for example, 700 nm by the method D.

The silicon oxide film 5 buried in the groove 21 becomes an insulating material, and electrically separates semiconductor elements.

Next, the surface of the silicon oxide film 5 embedded in the groove 21 is processed so that the groove edge is thick and the center is thin (hereinafter, referred to as a curved shape).

In order to form such a curved shape, in this embodiment, polishing pads having different hardnesses are used.
Two-stage polishing is performed by CMP (Chemical Mechanical Polisher).

FIG. 3 shows the configuration of a CMP apparatus used for polishing. This CMP apparatus includes a spindle 31, a carrier 32, a polishing pad 33, a platen 34, and an abrasive charging section 35.

The spindle 31 is connected to a pressing mechanism, and rotates the carrier 32 holding the object to be polished while applying pressure. The platen 34 is formed of a disk-shaped rigid body, holds and rotates the polishing pad 33, and polishes the object to be polished. The polishing agent input section 35 is provided for the polishing pad 3.
3. Abrasive is put on top.

First, in the first-stage polishing, a hard polishing pad 33 is used, and the pressure is 200 to 700 g / cm ² ,
The number of rotations of the carrier is 10 to 100 rpm, the number of rotations of the platen is 10 to 100 rpm, and the flow rate of the abrasive is 50 to 50.
It is set to about 0 ml / min, and the carrier 32 is used as shown in FIG.
While holding the silicon substrate 1 in the state shown in FIG. 1, the silicon oxide film 5 is polished to flatten the substrate surface. Polish its surface.

As the hard polishing pad 33, for example, a polishing pad made of a rigid foamed polyurethane of JISA hardness of 90 to 100 is provided on the polishing side, and an elastic material having a JISA hardness of 50 to 80 as a lower layer is made of polyurethane. A pad or the like made of an impregnated nonwoven fabric can be used.

As shown in FIG. 2A, when the silicon nitride film 3 is substantially exposed (exposed over the entire surface of the substrate), the first-stage polishing is completed, and the process proceeds to the second-stage polishing.

In the polishing in the second stage, a soft polishing pad 33 is used, the pressure is 200 to 700 g / cm ² , the rotation speed of the carrier is 10 to 100 rpm, the rotation speed of the platen is 10 to 100 rpm, and the polishing agent is used. Flow rate of 50 to 500
At a rate of about ml / min, the silicon substrate 1 is held by the carrier 32, the semiconductor substrate 1 in the state shown in FIG. 2A is held, and the surface thereof is polished.

As the soft polishing pad 33, for example, a polishing pad made of a foamed polyurethane or a polyurethane impregnated nonwoven fabric having a hardness of about 70 to 90 according to JISA on the polishing side, and a hardness of 50 to 70 JISA on the lower layer side.
In this case, a laminate of pads composed of a polyurethane-impregnated nonwoven fabric can be used. If the hardness is optimized, the polishing pad may be formed in a single layer instead of a stacked layer.

Generally, the polishing rate of the silicon nitride film 3 is as low as about １ ／ of the polishing rate of the silicon oxide film 5. For this reason, the boundary between the silicon nitride film 3 and the silicon oxide film 5 is hard to be polished, but is separated from the end of the silicon nitride film 3.
Polishing proceeds near the center of the groove 21. In this manner, a curved shape is formed on the surface of the silicon oxide film 5 buried in the groove 21 as shown in FIG. Polishing is completed when the difference in film thickness between the end portion and the central portion becomes about 50 to 100 nm.

The timing for terminating the polishing is as follows. For example, the relationship between the polishing time and the progress of the polishing is determined in advance by experiments or the like in the first and second stages of polishing, and the polishing is continued for a predetermined time. At that point, the polishing may be terminated.

Next, as shown in FIG. 2C, the silicon nitride film 3 is removed with hot phosphoric acid. Then, FIG.
As shown in FIG. 4D, the pad oxide film 2 is removed by performing an isotropic etching process with buffered hydrofluoric acid for a predetermined time, and the surface of the silicon oxide film 5 is made substantially flush with the surface of the substrate 1 so as to isolate the element. The film 5 is completed.

Subsequent steps are the same as those in the usual method of manufacturing a semiconductor device, and a semiconductor element is appropriately formed in each region separated by the element isolation insulating film 5.

Conventionally, the depression 6 at the peripheral edge of the silicon oxide film 5 which has been generated when the pad oxide film is removed is formed by the progress of the etching from above the peripheral edge of the silicon oxide film 5 and the progress of the etching from the side surface. This is due to a synergistic effect.

According to this embodiment, since the edge portion of the silicon oxide film 5 is formed thick, the progress of etching from the upper surface can be offset with the thickness of the upper surface, and the etching from the upper surface side does not progress much. Therefore, although a dent is formed by etching from the side surface, it can be reduced to a shallower and gentler dent than the conventional dent.

As described above, in the method of manufacturing a semiconductor device according to the present embodiment, the end (edge) of the groove 21 of the silicon oxide film 5 is polished so as to be thicker than the center. Therefore, when the pad oxide film 2 is etched, the depression 6 is prevented from expanding downward, and the size of the depression can be made smaller than before.

The present invention is not limited to the above embodiment, but can be variously modified and applied. For example, groove 2
The material of the insulator filled in 1 is arbitrary, for example,
A silicon nitride film or the like can be used. In this case, the pad film is formed of a nitride film, and the mask layer thereon is formed of a silicon oxide film or the like. Also, a mask layer (silicon nitride film 3)
Etc.), the material of the groove 21, the pad film, the film thickness, the forming method, the etching method, and the like can be arbitrarily changed.

[Second Embodiment] In the first embodiment, the curved shape is formed on the surface of the silicon oxide film 5 by polishing. However, the curved shape may be formed by etching. This manufacturing method will be described as a second embodiment with reference to FIGS.

First, in order to flatten the silicon oxide film 5 of the semiconductor device in the state shown in FIG. 4A and expose the silicon nitride film 3, polishing is performed in the same manner as in the first embodiment. . FIG. 4 shows a flattened silicon oxide film 5.
(B).

Next, the flattened silicon oxide film 5 is
Rather than polishing, isotropic etching is performed with buffered hydrofluoric acid or the like using the silicon nitride film 3 as a mask.

In this etching, the supply of the etchant is relatively reduced near the interface between the silicon oxide film 5 and the silicon nitride film 3, the etching rate is lower than in other regions, and the etching progresses near the interface. Is sent. Therefore, as shown in FIG. 4C, a curved shape can be formed on the surface of the silicon oxide film 5 filling the groove 21.

In the second embodiment, since a curved shape is formed on the surface of the silicon oxide film 5 filling the groove 21 by etching, the thickness of the silicon nitride film 3 is reduced.
It is necessary to make the thickness about 100 to 200 nm thicker than that of the first embodiment in advance as much as the etching proceeds.

[Third Embodiment] In the first embodiment, the structure of the insulating film filling the groove 21 is arbitrary. For example, the insulating film may cover the inner surface of the groove 21 and the surface of the silicon nitride film 3. A suitable liner film may be formed, and the silicon oxide 5 may be embedded in the groove where the liner film is formed.
This manufacturing method is referred to as a third embodiment, as shown in FIGS.
This will be described with reference to FIG. The feature of the third embodiment is that the etching rate of the liner film is lower than that of the buried film.

As shown in FIG. 5A, for example, the HTO film 7 covering the inner surface of the groove 21 and the surface of the silicon nitride film 3 is formed.
(High Temperture Oxide) is formed to a thickness of about 100 nm.
Since the HTO film 7 is formed at a high temperature of about 800 ° C., the etching rate when etching with a solution containing an aqueous hydrofluoric acid solution is different from that of another CVD method, for example, a bias C method.
Generally lower than the silicon oxide film 5 formed by the VD method, the normal pressure CVD method or the like. FIG. 5 shows an example of a silicon oxide film formed by a bias CVD method as a buried film, but the present invention is not limited to this. However, if a high-temperature heat treatment is applied after the film formation, the etching rate of the silicon oxide film formed by these CVD methods decreases, and the difference from the HTO film, for example, decreases. It is desirable to perform it after the processing is completed.

The silicon oxide film 5 is formed to a thickness of, for example, 600 nm by a bias CVD method so as to fill the inner surface of the groove 21 covered with the HTO film 7.

Next, using a CMP apparatus, the silicon oxide film 5 and the HTO film 7 formed on the silicon nitride film 3 are polished to flatten the substrate surface. Polishing is completed when the silicon nitride film 3 is substantially exposed (exposed over the entire surface of the substrate).

Next, instead of polishing in the second stage, isotropic etching is performed with buffered hydrofluoric acid or the like as in the second embodiment. Since the etching rate of the HTO film 7 is lower than the etching rate of the silicon oxide film 5, HT
The etching of the O film 7 does not proceed as compared with the etching of the silicon oxide film 5. Further, in the vicinity of the boundary between the silicon oxide film 5 and the HTO film 7, the etching rate decreases, and the etching rate at the peripheral portion of the silicon oxide film 5 also decreases.
For this reason, the entire insulating film in the groove 21 is formed as shown in FIG.
As shown in the figure, a curved shape in which the peripheral portions of the HTO film 7 and the silicon oxide film 5 are high (thick) and the central portion of the silicon oxide film 5 is low (thin) can be formed.

Next, as shown in FIG. 5C, the silicon nitride film 3 is removed, and the pad oxide film 2 is removed with an aqueous solution containing hydrofluoric acid. In this case, since the curved shape is formed, the occurrence of the conventional depression 6 due to the thickness of the curved groove edge can be suppressed.

In the third embodiment, the first-stage polishing is performed using a CMP apparatus, isotropic etching is performed using buffered hydrofluoric acid or the like, and the surface of the silicon oxide film 5 buried in the groove is formed. Although the curved shape is formed, the second stage polishing may be performed instead of the etching. By performing the second-stage polishing, a curved shape in which the peripheral portions of the HTO film 7 and the silicon oxide film 5 are high (thick) and the central portion of the silicon oxide film 5 is low (thin) can be formed.

In the third embodiment, the HTO film 7 different from the film filling the groove 21 is used as the liner film. For example, the same type of film as the film filling the groove 21 is used as the liner film. A thin film may be formed, annealed at a high temperature, and then the entire groove 21 may be buried to make a difference in film quality.

[Fourth Embodiment] The polishing rate and the etching rate may be changed by changing the film quality of the insulating film between the center and the edge, and a curved shape may be formed by polishing or etching.

The film quality of the insulating film can be changed, for example, by implanting ions and controlling the ion concentration.

Therefore, in this embodiment, the bias C
After the silicon oxide film 5 is formed by the VD method or the like, ions are selectively implanted, and as shown in FIG. 6A, regions 8a and 8 having different ion concentrations are formed on the surface region of the silicon oxide film 5.
b is formed.

In the ion implantation, for example, phosphorus ions are
The implantation angle is 45 degrees or less, and the dose is 10E15 / cm ³
The implantation energy is about 100 to 300 KeV while rotating the substrate. According to this implantation method, since the inclination angle of the bias CVD film is approximately 45 degrees, the shoulder portion of the silicon oxide film 5 functions as a mask,
A larger amount of ions are implanted into the center portion than the edge portion. Therefore, the ion concentration near the edge of the groove 21 is less than half the ion concentration near the center of the groove 21.

For example, 10E15 / cm at 200 KeV
^When about ³ phosphorus is injected obliquely by rotation, about 200
A maximum concentration region is formed in a region having a depth of nm. At this time, the ion concentration near the center of the groove is 1.2E20at.
oms / cm ³ .

After the ion implantation, the surface of the silicon oxide film 5 is polished using a CMP apparatus or the like until the silicon nitride film 3 is exposed, as shown in FIG. On this occasion,
Due to the difference in ion concentration, the polishing rate is higher at the center than at the edge of the groove 21, and a curved shape is formed in the surface region of the silicon oxide film 5 by polishing.

After the ion implantation, the surface of the silicon oxide film 5 is polished as shown in FIG. 6B, and then the silicon oxide film 5 is polished by using an etching solution whose etching rate increases as the ion concentration increases. By etching the surface region of the silicon oxide film 5, a curved shape can be formed in the surface region of the silicon oxide film 5.

It should be noted that the ions to be implanted and the implantation conditions are not limited to the above-mentioned examples, but are arbitrary.

[Fifth Embodiment] In the first embodiment, the first stage polishing is performed by using the CMP apparatus until the silicon nitride film 3 is exposed on the entire surface of the substrate. The polishing in the first stage may be terminated before the surface is exposed, and the polishing may be switched to the polishing in the second stage. In this case, after the silicon nitride film 3 is exposed, further polishing is performed until the thickness difference between the end and the center of the groove 21 becomes about 50 to 100 nm.

Since the polishing speed of the silicon nitride film 3 is lower than the polishing speed of the silicon oxide film 5, if polishing is continued, the polishing speed is significantly different between a dense portion and a sparse portion of the pattern. However, since this region where the dense and sparse portions of the pattern are present is polished with a soft pad, this pattern dependency is less likely to occur. Therefore, the difference in film thickness due to the density of the pattern is improved as compared with the first embodiment.

As described above, the first to fifth embodiments of the present invention are described.
According to the embodiment, the surface of the silicon oxide film buried in the groove is processed into a curved shape so that the peripheral edge of the surface is thicker than the central portion, and thereafter, the pad oxide film is etched by etching. At the time of removal, the depression formed near the interface between the silicon oxide film and the groove can be made shallow and small. In addition, thereby, the step on the surface is reduced, and it is possible to prevent etching residue and the like in a later step.

The present invention is not limited to the above-described embodiment, and various modifications and applications are possible. For example, in the above embodiment, the present invention was applied to the formation of an insulating film for element isolation. However, the present invention is not limited to this. Can be applied when flattening. The method of processing the surface portion of the insulating film into a curved shape is not limited to the example specified in the above embodiment, and any other method can be used.

[0074]

As described above, according to the present invention,
It is possible to provide a method of manufacturing a semiconductor device by a trench isolation method that can reduce a depression at an edge of an oxide film embedded in a trench by a relatively simple process. In addition, it is possible to provide a method for manufacturing a semiconductor device including an element isolation region that is narrow and has few steps.

[Brief description of the drawings]

FIG. 1 is a diagram showing steps of a method for manufacturing a semiconductor device by a groove separation method.

FIG. 2 is a diagram showing steps of a method for manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a view schematically showing a CMP apparatus.

FIG. 4 is a diagram illustrating a process of a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a diagram illustrating a process of a method of manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a process of a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing steps of a conventional method for manufacturing a semiconductor device.

FIG. 8 is a diagram showing a recessed portion of a trench isolation element having a MOSFET.

FIG. 9 is a top view of the substrate surface after gate lines are formed.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Pad oxide film 3 Silicon nitride film 4 Resist 5 Silicon oxide film 6 Depression 7 HTO film 8a Phosphorous high concentration area 8b Phosphorus low concentration area 9 Polysilicon 10 Polysilicon residue 21 Groove 31 Spindle 32 Carrier 33 Polishing pad 34 Platen 35 Abrasive input section

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/76 H01L 21/304 622 H01L 21/318 H01L 21/762

Claims (6)

(57) [Claims] 1. A method of manufacturing a semiconductor device of a trench isolation method, comprising: forming a pad oxide film on a silicon substrate; forming a silicon nitride film on the pad oxide film; A predetermined region of the silicon substrate is sequentially etched to form a groove, a silicon oxide is buried in the groove, and a surface portion of the silicon oxide buried in the groove is
By polishing using a P (Chemical Mechanical Polisher) device, a flat shape is formed by the first-stage polishing, and a curved shape is formed by the second-stage polishing. The silicon oxide film is formed in a high shape, the silicon nitride film is removed by etching, the pad oxide film is removed by wet etching, and a portion of the silicon oxide buried in the groove that protrudes on the silicon substrate is substantially removed. A method of manufacturing a semiconductor device. 2. A method of manufacturing a semiconductor device of a trench isolation method, comprising: forming a pad oxide film on a silicon substrate; forming a silicon nitride film on the pad oxide film; A predetermined region of the silicon substrate is sequentially etched to form a groove, a silicon oxide is buried in the groove, and a surface portion of the silicon oxide buried in the groove is
Using a P apparatus, first, a first-stage polishing of polishing the silicon nitride film and the silicon oxide using a first polishing pad having a predetermined hardness is performed, and then a first polishing process softer than the predetermined hardness is performed. A second step of polishing the silicon nitride film and the silicon oxide by using the polishing pad of No. 2 to form a shape in which a peripheral portion is higher than a central portion of the groove, and etching the silicon nitride film by etching Removing the pad oxide film by wet etching and substantially removing a portion of the silicon oxide buried in the trench protruding above the silicon substrate. Production method. 3. A method of manufacturing a semiconductor device of a trench isolation type, comprising: forming a pad oxide film on a silicon substrate; forming a silicon nitride film on the pad oxide film; A predetermined region of the silicon substrate is sequentially etched to form a groove, a silicon oxide is buried in the groove, and the surface of the silicon oxide buried in the groove has a hardness of 80 to 100 according to JISA. First-stage polishing is performed using a CMP apparatus having a first polishing pad, and then second-stage polishing is performed using a CMP apparatus having a second polishing pad having a hardness of 75 to 90 according to JISA. By polishing, the peripheral portion is formed higher than the central portion of the groove, the silicon nitride film is removed by etching, and the pad oxide film is removed by wet etching. And substantially removing a portion of the silicon oxide embedded in the trench protruding above the silicon substrate. 4. The method according to claim 1, wherein in the first stage polishing, the surface of the silicon oxide is formed into a flat shape, and in the second stage polishing, the surface of the silicon oxide is formed in a curved shape. The method for manufacturing a semiconductor device according to claim 2, wherein: 5. The method according to claim 1, wherein the polishing in the first stage is performed according to JISA.
The first polishing pad having a hardness of し 100 is used, and the second polishing step uses a second polishing pad having a hardness of 75 to 90 according to JISA. Or a method for manufacturing a semiconductor device according to item 2. 6. The polishing in the second step is completed when the difference between the film thickness at the edge of the groove and the film thickness at the center of the surface of the silicon oxide in the groove becomes about 50 to 100 nm. The method of manufacturing a semiconductor device according to claim 1, wherein: