CN111341662B - Groove gradient side oxygen structure, preparation method thereof and semiconductor device - Google Patents
Groove gradient side oxygen structure, preparation method thereof and semiconductor device Download PDFInfo
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- CN111341662B CN111341662B CN202010143198.4A CN202010143198A CN111341662B CN 111341662 B CN111341662 B CN 111341662B CN 202010143198 A CN202010143198 A CN 202010143198A CN 111341662 B CN111341662 B CN 111341662B
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 title claims abstract description 44
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 104
- 238000000034 method Methods 0.000 claims abstract description 45
- 239000011247 coating layer Substances 0.000 claims abstract description 33
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 31
- 239000011574 phosphorus Substances 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 claims abstract description 22
- 238000011049 filling Methods 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000005260 corrosion Methods 0.000 claims abstract description 14
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 230000007797 corrosion Effects 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 9
- 230000000694 effects Effects 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000000137 annealing Methods 0.000 claims description 17
- 230000003647 oxidation Effects 0.000 claims description 13
- 238000007254 oxidation reaction Methods 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 238000005253 cladding Methods 0.000 claims description 9
- 239000007772 electrode material Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- 239000000945 filler Substances 0.000 claims description 6
- 239000011368 organic material Substances 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 claims description 4
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 239000004642 Polyimide Substances 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 229920001721 polyimide Polymers 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000009826 distribution Methods 0.000 abstract description 7
- 230000005684 electric field Effects 0.000 abstract description 7
- 239000007788 liquid Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- IYYIVELXUANFED-UHFFFAOYSA-N bromo(trimethyl)silane Chemical compound C[Si](C)(C)Br IYYIVELXUANFED-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- DOTMOQHOJINYBL-UHFFFAOYSA-N molecular nitrogen;molecular oxygen Chemical compound N#N.O=O DOTMOQHOJINYBL-UHFFFAOYSA-N 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
Abstract
The invention relates to a groove gradient side oxygen structure, a preparation method thereof and a semiconductor device. The preparation method of the groove gradient side oxygen structure comprises the following steps: a) Forming a mask layer on the surface of the silicon wafer, wherein a groove definition area is formed on the mask layer; b) Etching the groove definition area to form a groove and removing the mask layer; c) Forming at least one layer of coating layer on the surface of the groove, and carrying out surface phosphorus treatment on the coating layer on the surface of the groove; d) Filling the groove with a filling material; e) Corroding the coating layer and obtaining a required corrosion effect; f) And removing part or all of the filling material to obtain the trench gradient side oxygen structure. The method is simple and efficient, an ideal slope ladder field plate can be formed on the surface of the side wall of the groove, electric field distribution of a drift region of the device is optimized, and remarkable improvement and improvement of the performance of the device are achieved.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a groove gradient side oxygen structure, a preparation method thereof and a semiconductor device.
Background
Currently, in semiconductor device technology, a side-Oxide-doped OB (Oxide-b) technology of a trench structure is widely used, and in devices such as a medium-low voltage MOSFET and a trench schottky (TMBS), FRD and IGBT devices are also used. Typical mass-produced products such as SGT (split gate MOSFET) devices and the like. For a trench-bypass-OB MOSFET, the electric field distribution of the device drift region is uneven, and a gap exists between the device drift region and the Super Junction structure, so that the design concept of a gradient-bypass-GOB structure is provided.
The structure shown in fig. 1 is given in US20010000033A1, and the implementation method is also given: the dynamic mask etching principle is adopted, polysilicon is used as a sacrificial layer, and the polysilicon is gradually etched, so that the oxidation layer realizes a slope gradient side oxygen etching shape.
In the paper "Design and Fabrication of Superjunction Power MOSFET Devices" of the doctor school in 2008, chen Yu, national University of Singapore (national university of singapore), a number of process implementations are also presented that make it possible to realize a ramp-like gradient profile of side oxygen corrosion, which still applies the corrosion principle of dynamic masks. However, as mentioned on page 72 of the paper, "much work is required to find a suitable etchant and sacrificial material to achieve a vertical gradient oxide wall".
In another example, "the book of the main institute of engineering of blue-hao, harbin university, 2013, entitled" the simulation study of deep trench dielectric engineering of gate-enhanced power UMOSFET "on page 16, it is said that" GOB adjusts the electric field distribution in the drift region by adjusting the side oxygen angle, so that the electric field distribution is significantly more uniform than that of the OB structure, and has better performance, and the disadvantage is mainly that the side oxygen angle is difficult to control in the actual process. In general, GOB gradient side oxygen structure is difficult to realize in the current practical technology, so that the devices in actual mass production are also OB side oxygen structures, as shown in (a), (b) and (c) in FIG. 2.
For the MOSFET device with OB side oxygen structure, such as a split gate MOSFET device, if the side oxygen in the trench is a thermal oxide layer grown by a thermal oxidation process, after the channel region is etched, the interface of the oxide layer is substantially at an angle of 90 degrees with the sidewall of the trench, in this case, the thermal oxidation process is further performed to grow the gate oxide layer, so that a relatively thin gate oxide layer is formed at the interface of the side oxygen and the sidewall of the trench, as shown in fig. 3, so that the voltage withstand (Vgs) between the gate and the source is greatly reduced, and the durability of the device is reduced.
In view of this, the present invention has been made.
Disclosure of Invention
The invention aims to provide a groove gradient side oxygen structure and a preparation method thereof, and the method is simple and efficient, can form an ideal slope ladder field plate on the surface of the side wall of the groove, optimize the electric field distribution of a drift region of a device and realize remarkable improvement and improvement of the performance of the device.
The invention also provides a semiconductor device applying the trench gradient side oxygen structure.
In order to achieve the above object of the present invention, the following technical solutions are specifically adopted:
the preparation method of the groove gradient side oxygen structure comprises the following steps:
a) Forming a mask layer on the surface of the silicon wafer, wherein a groove definition area is formed on the mask layer;
b) Etching the groove definition area to form a groove and removing the mask layer;
c) Forming at least one layer of coating layer on the surface of the groove, and carrying out surface phosphorus treatment on the coating layer on the surface of the groove;
d) Filling the groove with a filling material;
e) Corroding the coating layer and obtaining a required corrosion effect;
f) And removing part or all of the filling material to obtain the trench gradient side oxygen structure.
Optionally, in step a), the silicon wafer is selected from a single wafer or an epitaxial wafer.
Optionally, the silicon wafer is an N-type silicon wafer.
Optionally, in step c), at least one of the coating layers is formed by thermal oxidation and/or vapor deposition (CVD).
Optionally, the cladding layer includes a field oxide layer and/or a dielectric layer.
Optionally, in step c), at least one field oxide layer is formed by thermal oxidation, and then at least one dielectric layer is formed by vapor deposition.
In at least one of the coating layers, the outermost coating layer needs to meet the condition of being able to be corroded and removed, and other inner coating layers (the field oxide layer and/or the dielectric layer) can be corroded or can not be corroded, namely whether the inner coating layer needs to be corroded or not can be designed according to actual requirements.
As an embodiment of the present invention, the cladding layer formed in the trench may be a field oxide layer, a composite dielectric layer, or a layer including both a field oxide layer and a composite dielectric layer; for example, a part of oxide layer is formed by a thermal oxidation process, then a CVD process is performed to deposit a dielectric layer, and 2 or more dielectric layers are formed, and the finally formed outermost dielectric layer is required to be capable of wet etching and relatively dense phosphorus doping (phosphorus treatment process).
Optionally, in step c), the method of surface phosphorus treatment comprises:
at 850-1100 deg.c, pre-diffusion treatment with phosphorus source is performed for over 10 min.
Optionally, the phosphorus source is selected from POCl 3 Or pH of 3 。
In the invention, by adjusting the diffusion temperature of the phosphorus pre-diffusion treatment and the time of introducing the phosphorus source, the post-corrosion slope angle of the coating layer (the field oxide layer and/or the dielectric layer) can be adjusted within a certain range, and the higher the diffusion temperature is, the longer the time is, and the smaller the post-corrosion slope angle of the coating layer (the field oxide layer and/or the dielectric layer) is.
Optionally, an annealing treatment is further included after the pre-diffusion treatment; the annealing treatment method comprises the following steps:
and heat-treating for 0-60 min under the annealing atmosphere and the condition of being higher than the pre-diffusion treatment temperature.
Optionally, the annealing atmosphere is selected from oxygen and/or nitrogen.
Alternatively, both pre-diffusion and annealing of the phosphorus source may be performed in a diffusion furnace.
As one embodiment of the invention, the surface phosphorus treatment of the coating layer on the surface of the groove can be generally carried out by adopting a diffusion furnace, and the POCl of a liquid source is introduced 3 Or a gaseous source PH 3 Carrying out conventional phosphorus pre-diffusion process treatment, wherein the diffusion temperature is 850-1100 ℃ and the diffusion time is more than 10 minutes.
As an embodiment of the invention, after the conventional phosphorus pre-diffusion process is finished, the annealing treatment can be continued, and the annealing treatment can be carried out by adopting a diffusion furnace, wherein the atmosphere can be oxygen O 2 Or nitrogen N 2 Or nitrogen-oxygen mixed gas, the process temperature is not lower than the phosphorus treatment temperature, the process time can be adjusted according to the actual condition and the actual requirement, and annealing for 1 hour is usually enough.
Alternatively, the annealing step may or may not be performed, as desired.
Optionally, in step d), the filler material is selected from polysilicon or an organic material.
Optionally, the organic material is selected from at least one of photoresist or polyimide.
When an organic material is used as the filler material, it is required that the organic material be a material that cannot be corroded by a corrosive liquid and can be removed with high selectivity in a subsequent process.
Optionally, in step e), wet etching is performed on the cladding layer, and after wet etching, an included angle alpha is formed between the residual slope of the cladding layer and the axial direction of the depth of the groove; the included angle alpha is 6-40 degrees.
Optionally, the wet etching solution may be BOE (6:1), which comprises the following components: the volume ratio of the aqueous hydrofluoric acid (49%) to the aqueous ammonium fluoride (40%) was 6:1.
Optionally, in step f), the trench filler is removed, for example, the filler is polysilicon, and according to the device structure design, the corresponding process is performed, so that the filled polysilicon can be completely removed, or the polysilicon is etched to a level below the level of the slope of the cladding layer (e.g., field oxide layer) formed after etching.
According to another aspect of the present invention, there is provided a trench gradient side oxygen structure made according to any of the methods described above.
According to another aspect of the present invention, there is provided a semiconductor device to which the above trench gradient side oxygen structure is applied.
The semiconductor device includes a substrate; the substrate is provided with at least one trench gradient side oxygen structure as described above.
Optionally, the semiconductor device further comprises an insulating dielectric layer and a conductive electrode material disposed within the trench.
Optionally, the thickness of the insulating dielectric layer increases linearly along the depth direction of the trench.
Optionally, the insulating medium layer is in a slope shape, the slope length is 0.5-5 μm, and the included angle between the slope and the axial direction of the depth of the groove is smaller than 40 degrees.
Optionally, the conductive electrode material is connected to an electrode on the surface of the substrate, or the conductive electrode material is floating.
Optionally, the conductive electrode material is a single piece, or the conductive electrode material is separated into several segments by the insulating dielectric layer.
Compared with the prior art, the invention has the beneficial effects that:
(1) The preparation method of the groove gradient side oxygen structure provided by the invention is simple and efficient, and an ideal slope step field plate can be formed on the surface of the side wall of the groove through a directional corrosion process, so that the electric field distribution of a drift region of a device is optimized, and the remarkable improvement and improvement of the performance of the device are realized.
(2) According to the preparation method of the groove gradient side oxygen structure, provided by the invention, the angle and the length of the slope of the groove side wall surface can be adjusted within a certain range through isotropic surface treatment, the use of a wet etching process, surface treatment and differential design of an annealing process, and the device performance optimization space is increased.
(3) When the groove gradient side oxygen structure prepared by the method is used for a gate control device, the uniformity of the thickness of the gate oxide can be improved, the voltage resistance level of the gate oxide layer can be improved, and the durability of the device can be improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a trench side oxygen structure of the type shown in the prior art;
FIG. 2 shows SGTs (a, b) and TMBS (c) using trench-side oxygen technology in a conventional semiconductor device;
FIG. 3 is a schematic diagram showing a partial thickness of a gate oxide layer after gate oxidation in a conventional split gate MOSFET device, wherein (b) is a partial enlarged view of (a);
FIG. 4 is a schematic illustration of a process for fabricating a trench gradient side oxygen structure in accordance with one embodiment of the present invention; wherein, (a) a mask layer and a trench definition region are formed; (b) etching to form a trench; (c) Removing the mask layer and forming a coating layer (field oxide layer) and performing surface phosphorus treatment; (d) filling the trench with a filling material; (e) Removing filling materials at the groove inlet and on the surface of the silicon wafer substrate by adopting an etching or corrosion process; (f) According to design and requirements, the coating layer (field oxide layer) is corroded to a certain extent, and the slope of the residual coating layer (field oxide layer) forms an included angle alpha with the axial direction of the depth of the groove; completely removing (g) or partially removing (h) the filling material in the groove; when the multilayer coating layers are provided, the multilayer coating layers are corroded to a certain extent and form slopes, so that the structure shown in (i) is obtained; when the multilayer coating layer is provided, only the outermost layer of the multilayer coating layer is corroded to a certain extent and forms a slope, and the inner layer is not corroded, so that the structure shown in (j) is obtained;
the reference numerals are as follows:
1-a mask layer; 2-a silicon wafer substrate; 3-grooves; 4-cladding layers (field oxide layers and/or dielectric layers); 5-filling material; 6-residual filler material;
FIG. 5 is a schematic view showing a slope angle α of a trench gradient side oxygen structure of 12 degrees (a) and 9 degrees (b) according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a trench MOSFET device according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a trench MOSFET device according to another embodiment of the present invention, wherein (a) and (b) respectively show two cases where a polysilicon material is separated into two parts by an insulating material;
fig. 8 is a schematic structural diagram of a diode device with a trench structure according to another embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to examples, but it will be understood by those skilled in the art that the following examples are only for illustrating the present invention and should not be construed as limiting the scope of the present invention. The specific conditions are not noted in the examples and are carried out according to conventional conditions or conditions recommended by the manufacturer. The reagents or apparatus used were conventional products commercially available without the manufacturer's attention.
According to one embodiment of the invention, the preparation process of the trench gradient side oxygen structure is as shown in fig. 4:
a) Providing an N-type silicon wafer 2 (a single wafer or an epitaxial wafer) as a base material, forming a mask layer 1 on the surface of the silicon wafer, wherein a groove definition region is formed on the mask layer 1;
b) Etching the groove definition area to form a groove 3 and removing the mask layer 1;
c) Forming at least one coating layer 4 on the surfaces of the silicon wafer 2 and the groove 3, and carrying out surface phosphorus treatment on the coating layer 4 on the surface of the groove;
d) Filling the trench 3 with a filling material 5;
e) Corroding the coating layer 4, and obtaining a required corrosion effect according to set requirements;
f) And removing part or all of the filling material 5 according to set requirements to obtain the trench gradient side oxygen structure.
According to a specific embodiment of the present invention, as shown in (c) of fig. 4, the clad layer in step c) is a field oxide layer formed by a thermal oxidation process; the field oxide layer can be subjected to wet corrosion, and a relatively dense phosphorus doping and phosphorus treatment process can be realized.
According to a specific embodiment of the present invention, as shown in fig. 4 (i) and (j):
in the step c), the coating layer comprises a field oxide layer and a dielectric layer, wherein the dielectric layer can be a single dielectric layer or a plurality of composite dielectric layers; forming a partial oxide layer through a thermal oxidation process, and then depositing a dielectric layer through a CVD process to form a single-layer or multi-layer dielectric layer; the dielectric layer positioned on the outermost layer is required to be capable of being subjected to wet corrosion, and a relatively concentrated phosphorus doping and phosphorus treatment process can be realized; the field oxide layer and the dielectric layer located in the inner layer may or may not be corrodible as shown in fig. 4 (i), as shown in fig. 4 (j), according to actual needs.
According to a specific embodiment of the invention, in the diffusion furnace pair step c)The coating layer of (2) is subjected to pre-diffusion treatment of phosphorus, and the phosphorus source can be liquid source POCl 3 Or a gaseous source PH 3 The diffusion temperature is 850-1100 ℃, and the diffusion time is more than 10 minutes.
According to a specific embodiment of the present invention, after the pre-diffusion treatment is completed, the annealing treatment atmosphere may be oxygen O in the diffusion furnace 2 Or nitrogen N 2 Or nitrogen-oxygen mixed gas, the process temperature is not lower than the phosphorus treatment temperature, the process time can be adjusted according to the actual condition and the actual requirement, and annealing for 1 hour is usually enough.
According to a specific embodiment of the present invention, the annealing treatment may not be performed after the completion of the pre-diffusion treatment.
According to a specific embodiment of the present invention, in the step c), the coating layer is a field oxide layer formed by a thermal oxidation process, and the pre-diffusion temperature of phosphorus is 900 ℃ and the pre-diffusion time is 30min when the surface phosphorus is treated; the filling material in step d) is selected from polysilicon; and (3) corroding the field oxide layer by adopting a corrosive liquid BOE (6:1), and selecting proper corrosion time to enable an included angle alpha between the slope of the residual field oxide layer and the axial direction of the depth of the groove to be 12 degrees, as shown in (a) of fig. 5.
According to a specific embodiment of the present invention, in the step c), the coating layer is a field oxide layer formed by a thermal oxidation process, and the pre-diffusion temperature of phosphorus is 920 ℃ and the pre-diffusion time is 50min when the surface phosphorus is treated; the filling material in step d) is selected from polysilicon; and (3) corroding the field oxide layer by adopting a corrosive liquid BOE (6:1), and selecting proper corrosion time to enable the included angle alpha between the slope of the residual field oxide layer and the axial direction of the depth of the groove to be 9 degrees, as shown in (b) of fig. 5.
According to a specific embodiment of the present invention, as shown in fig. 6, there is provided a trench MOSFET device to which the trench gradient side oxygen structure of the present invention is applied, the trench of which extends into the withstand voltage drift region of the trench MOSFET, the trench side oxygen being formed into a stepped shape having a certain angle by wet etching. The MOSFET device active area provided in fig. 6 comprises a plurality of periodically arranged cells, each of which comprises a trench, a source metal layer, an n+ source region, a p+ region, a P well region, a drift region, and n+ substrate and drain metal layers. Wherein the trench structure extends from the surface into the drift region of the cell; the trench comprises a polysilicon gate, a gate oxide layer at the side of the P well region and a field oxide layer with a slope shape; the polysilicon gate is isolated from the source metal S by an insulating oxide layer.
According to a specific embodiment of the present invention, as shown in fig. 7 (a) and (b), another type of MOSFET device using the trench gradient side oxygen structure of the present invention is provided, the trench includes polysilicon and insulating material, the polysilicon may be divided into an upper portion and a lower portion by the insulating material, the upper portion is gate G polysilicon, the lower portion is field plate polysilicon, and the field plate polysilicon is connected to the source S of the trench MOSFET.
According to a specific embodiment of the present invention, as shown in fig. 8, there is provided a diode device to which the trench gradient side oxygen structure of the present invention is applied, the trench extends into a voltage-resistant drift region of the diode, the trench side oxygen is composed of 3 layers of insulating media, and a dielectric layer near one side of the field polysilicon is formed into a stepped shape with a certain angle by wet etching, so as to optimize electric field distribution in the voltage-resistant drift region.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limited thereto; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (17)
1. The preparation method of the groove gradient side oxygen structure is characterized by comprising the following steps:
a) Forming a mask layer on the surface of the silicon wafer, wherein a groove definition area is formed on the mask layer;
b) Etching the groove definition area to form a groove and removing the mask layer;
c) Forming at least one layer of coating layer on the surface of the groove, and carrying out surface phosphorus treatment on the coating layer on the surface of the groove;
d) Filling the groove with a filling material;
e) Corroding the coating layer and obtaining a required corrosion effect;
f) Removing part or all of the filling material to obtain a groove gradient side oxygen structure;
in the step c), the coating layer comprises a dielectric layer;
in step d), the filler material is selected from polysilicon or an organic material; the organic material is selected from at least one of photoresist or polyimide.
2. The method according to claim 1, wherein in step a), the silicon wafer is selected from a single wafer or an epitaxial wafer.
3. The method of claim 1 wherein in step a) the silicon wafer is an N-type silicon wafer.
4. A method according to any one of claims 1 to 3, wherein in step c) at least one of the coating layers is formed by thermal oxidation and/or vapour deposition.
5. The method of claim 1, wherein the cladding layer comprises a field oxide layer.
6. The method of claim 4, wherein in step c), at least one field oxide layer is formed by thermal oxidation and at least one dielectric layer is formed by vapor deposition.
7. The method according to claim 1, wherein in step c), the method of surface phosphorus treatment comprises:
at 850-1100 deg.c, pre-diffusion treatment with phosphorus source is performed for over 10 min.
8. The method of claim 7, wherein the phosphorus source is selected from the group consisting of POCl 3 Or pH of 3 。
9. The method of claim 7, further comprising an annealing process after the pre-diffusion process; the annealing treatment method comprises the following steps:
heat treatment is carried out for 0min to 60min under the conditions of annealing atmosphere and the temperature higher than the pre-diffusion treatment temperature; the annealing atmosphere is selected from oxygen and/or nitrogen.
10. The method according to claim 1, wherein in step e), the cladding layer is subjected to wet etching, and the residual cladding layer slope forms an angle alpha with the axial direction of the trench depth after wet etching; the included angle alpha is 6-40 degrees.
11. A trench gradient side oxygen structure prepared by the method of any one of claims 1 to 10.
12. A semiconductor device comprising a substrate; the substrate having disposed thereon at least one trench gradient side oxygen structure as defined in claim 11.
13. The semiconductor device of claim 12, further comprising an insulating dielectric layer and a conductive electrode material disposed within the trench.
14. The semiconductor device according to claim 13, wherein a thickness of the insulating dielectric layer increases linearly in a depth direction of the trench.
15. The semiconductor device of claim 13, wherein the insulating dielectric layer is sloped with a slope length of 0.5 μm to 5 μm, and an angle between the slope and an axial direction of the trench depth is less than 40 degrees.
16. The semiconductor device of claim 13, wherein the conductive electrode material is connected to an electrode on the surface of the substrate or the conductive electrode material is floating.
17. The semiconductor device of claim 16, wherein the conductive electrode material is integral or separated into segments by the insulating dielectric layer.
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| JPH11260905A (en) * | 1998-03-12 | 1999-09-24 | Nec Corp | Manufacture of semiconductor device |
| TW200419801A (en) * | 2003-03-28 | 2004-10-01 | Advanced Power Electronics Corp | Trench power MOSFET and method thereof |
| JP2010103552A (en) * | 2009-12-22 | 2010-05-06 | Renesas Technology Corp | Semiconductor device, and method of manufacturing the same |
| CN108010964A (en) * | 2017-11-29 | 2018-05-08 | 吉林华微电子股份有限公司 | A kind of IGBT device and manufacture method |
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| US8587054B2 (en) * | 2011-12-30 | 2013-11-19 | Force Mos Technology Co., Ltd. | Trench MOSFET with resurf stepped oxide and diffused drift region |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH11260905A (en) * | 1998-03-12 | 1999-09-24 | Nec Corp | Manufacture of semiconductor device |
| TW200419801A (en) * | 2003-03-28 | 2004-10-01 | Advanced Power Electronics Corp | Trench power MOSFET and method thereof |
| JP2010103552A (en) * | 2009-12-22 | 2010-05-06 | Renesas Technology Corp | Semiconductor device, and method of manufacturing the same |
| CN108010964A (en) * | 2017-11-29 | 2018-05-08 | 吉林华微电子股份有限公司 | A kind of IGBT device and manufacture method |
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