CN103928346A - Method for preparing UMOSFET device with N-type heavy doping drift layer table top formed through epitaxial growth - Google Patents
Method for preparing UMOSFET device with N-type heavy doping drift layer table top formed through epitaxial growth Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 36
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 20
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000005516 engineering process Methods 0.000 claims abstract description 11
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 42
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 claims description 38
- 229910052757 nitrogen Inorganic materials 0.000 claims description 37
- 239000007789 gas Substances 0.000 claims description 34
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 22
- 229910000077 silane Inorganic materials 0.000 claims description 22
- -1 nitrogen ion Chemical class 0.000 claims description 20
- 239000012159 carrier gas Substances 0.000 claims description 19
- 239000001294 propane Substances 0.000 claims description 19
- 238000002360 preparation method Methods 0.000 claims description 17
- 239000001257 hydrogen Substances 0.000 claims description 16
- 229910052739 hydrogen Inorganic materials 0.000 claims description 16
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims description 16
- 238000004026 adhesive bonding Methods 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- 239000007788 liquid Substances 0.000 claims description 11
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 9
- 230000013011 mating Effects 0.000 claims description 9
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 3
- YTAHJIFKAKIKAV-XNMGPUDCSA-N [(1R)-3-morpholin-4-yl-1-phenylpropyl] N-[(3S)-2-oxo-5-phenyl-1,3-dihydro-1,4-benzodiazepin-3-yl]carbamate Chemical compound O=C1[C@H](N=C(C2=C(N1)C=CC=C2)C1=CC=CC=C1)NC(O[C@H](CCN1CCOCC1)C1=CC=CC=C1)=O YTAHJIFKAKIKAV-XNMGPUDCSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical group 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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Abstract
The invention relates to a method for preparing an UMOSFET device with an N-type heavy doping drift layer table top formed through epitaxial growth. The method comprises the steps that an N-type drift region is formed through epitaxial growth; an N+ drift layer of the table top is formed through epitaxial growth; the N+ drift layer is etched so as to serve as the table top; a P- epitaxial layer is formed through epitaxial growth; an N+ source region layer is formed through epitaxial growth; a groove is formed through etching; a source region is formed through etching; a groove gate is formed through oxidization; polycrystalline silicon is deposited; contact holes are formed, wherein a passivation layer is prepared and the electrode contact holes are formed; electrodes are prepared, wherein metal is evaporated and the electrodes are prepared. Through the epitaxial growth technology and the etching technology, the doping density of an N-type drift region table top in the silicon carbide UMOSFET device with an N- drift layer table top is improved and the on resistance of the device is reduced.
Description
Technical field
The present invention relates to microelectronics technology, relate in particular to a kind of UMOSFET device preparation method of epitaxial growth formation N-type heavy doping drift layer table top.
Background technology
Third generation semiconductor material with wide forbidden band carborundum has broad-band gap, high critical breakdown electric field, and the good physics and chemistry character such as high electronics saturation drift velocity and higher thermal conductivity, at high temperature, high pressure, in the application of large power semiconductor device, tool has great advantage.
Power MOSFET is as switch, its forward conduction resistance and reverse breakdown voltage are conflict relations, and the UMOSFET of vertical structure has eliminated parasitic accumulation layer resistance and JFET resistance, so UMOSFET compares and has certain advantage with the MOSFET of transversary in this respect.
Also existent defect of UMOSFET self, the electric field concentration effect of Qi Cao grid corner causes device to puncture in advance, has reduced the reliability of device.The carborundum UMOSFET device with N-type drift layer table top that can reduce groove grid turning electric field, through being invented, the P-epitaxial loayer of this device has wrapped up groove grid turning, has replaced the SiO at turning with SiC PN junction interface
2/ SiC bears reverse voltage in interface, has improved the reliability of device.
But because P-epitaxial loayer in this scheme has wrapped up groove grid turning, conductive path is narrowed at table top place, and the impurity concentration at table top place is equal with drift layer concentration, doping content is lower, and this is all to the disadvantageous factor of conducting resistance.
In view of above-mentioned defect, creator of the present invention has obtained this creation finally through long research and practice.
Summary of the invention
The object of the present invention is to provide a kind of UMOSFET device preparation method of epitaxial growth formation N-type heavy doping drift layer table top, in order to overcome above-mentioned technological deficiency.
For achieving the above object, the invention provides a kind of UMOSFET device preparation method of epitaxial growth formation N-type heavy doping drift layer table top, this detailed process is:
Step a, epitaxial growth N-type drift region: epitaxial growth thickness is about 10 μ m～20 μ m on silicon carbide N+substrate print, and nitrogen ion doping concentration is 1 × 10
15cm
-3～5 × 10
15cm
-3n-type drift region;
Step b, epitaxial growth forms the N+ drift layer of table top: the heavily doped N+ drift layer of epitaxial growth one deck on N-type drift region, thickness is 1 μ m～2 μ m, nitrogen ion doping concentration is 1 × 10
17cm
-3～5 × 10
17cm
-3;
Step c, N+ drift layer etching is table top: N+ drift layer is etched into a table top, the deep equality of table surface height and N+ drift layer, mesa width is 3 μ m～4 μ m;
Steps d, epitaxial growth P-epitaxial loayer: one deck P-epitaxial loayer of growing on N-type drift region and N+ drift layer table top, thickness is 3 μ m, Al-doping concentration is 5 × 10
17cm
-3～1 × 10
18cm
-3;
Step e, epitaxial growth N+ source region layer: one deck N+ source region layer of growing on P-epitaxial loayer, thickness is 0.5 μ m, doping content is 5 × 10
18cm
-3;
Step f, etching grooving: adopt ICP etching to form groove directly over N-type heavy doping drift layer table top, width is 6 μ m, and the degree of depth is 3 μ m, and two of groove base angles are wrapped up by P-epitaxial loayer like this;
Step g, etching forms source region: adopt ICP etching to form source region contact;
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO
2, thickness is 100nm;
Step I, depositing polysilicon: the groove gate medium SiO in groove grid
2upper deposit polySi layer;
Step j, opening contact hole: prepare passivation layer, open electrode contact hole;
Step k, prepares electrode: evaporated metal, prepare electrode.
Further, in above-mentioned steps a, first the silicon carbide substrates sheet of N-type is carried out to RCA standard cleaning, then on whole substrate slice, epitaxial growth thickness is 10 μ m～20 μ m, and nitrogen ion doping concentration is 1 × 10
15cm
-3～5 × 10
15cm
-3n-drift layer, its process conditions are: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts liquid nitrogen.
Further, in above-mentioned steps b,
Epitaxial growth forms the N+ drift layer of table top, and thickness is 1～2 μ m, and nitrogen ion doping concentration is 1 × 10
17cm
-3～5 × 10
17cm
-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane.
Further, in above-mentioned steps c, process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Further, in above-mentioned steps d, one deck P-epitaxial loayer of growing on N-type drift region and N+ drift layer table top, thickness is 3 μ m, Al-doping concentration is 5 × 10
17cm
-3～1 × 10
18cm
-3; Its process conditions are that temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane, and carrier gas adopts pure hydrogen, and doped source adopts trimethyl aluminium.。
Further, in above-mentioned steps e, a layer thickness of growing on P-epitaxial loayer is 0.5 μ m, and nitrogen ion doping concentration is 5 × 10
18cm
-3n-type silicon carbide epitaxial layers, as N+ source region layer, its process conditions are: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts liquid nitrogen.
Further, in above-mentioned steps f, first magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, the width that etches groove is 6 μ m, the degree of depth is 3 μ m, finally removes photoresist, and goes etch mask, is washed to mating plate; Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Further, in above-mentioned steps g, first magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, forms source region contact hole, finally removes photoresist, and goes etch mask, is washed to mating plate; Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Further, in above-mentioned steps h, adopt dry oxygen technique to prepare SiO at 1150 DEG C
2grid, thickness is 100nm, then at 1050 DEG C, N
2under atmosphere, anneal, reduce SiO
2the roughness of film surface.
Further, in above-mentioned steps i, adopt low pressure hot wall chemical vapor deposition method growth ploySi to fill up groove, deposition temperature is 600～650 DEG C, deposit pressure is 60～80Pa, reacting gas is silane and hydrogen phosphide, and carrier gas is helium, then gluing photoetching, etching ploySi layer, form polysilicon gate, finally remove photoresist, clean.
Beneficial effect of the present invention is compared with prior art: the present invention has improved the doping content with the N-type drift region table top in the carborundum UMOSFET device of N-drift layer table top by epitaxial growth and etching technics, has reduced the conducting resistance of this device.Adopt the N+ drift layer of epitaxial growth (CVD) technology formation table top, can form the film of high uniformity; Epitaxial growth can be avoided the high-temperature annealing activation process after Implantation and Implantation in addition, thereby reduces the lattice damage being brought by Implantation.
Brief description of the drawings
Fig. 1 is the structural representation of the present invention with the carborundum UMOSFET device of N-type drift layer table top;
Fig. 2 is the fabrication processing figure of the present invention with the carborundum UMOSFET device of N-type drift layer table top.
Embodiment
Below in conjunction with accompanying drawing, technical characterictic and the advantage with other above-mentioned to the present invention are described in more detail.
Refer to shown in Fig. 2, it is for the present invention is with the structural representation of the carborundum UMOSFET device of N-type drift layer table top, and this detailed process is:
Step a, epitaxial growth N-type drift region: epitaxial growth thickness is about 10 μ m～20 μ m on silicon carbide N+substrate print, and nitrogen ion doping concentration is 1 × 10
15cm
-3～5 × 10
15cm
-3n-type drift region;
Step b, epitaxial growth forms the N+ drift layer of table top: the heavily doped N+ drift layer of epitaxial growth one deck on N-type drift region, thickness is 1 μ m～2 μ m, nitrogen ion doping concentration is 1 × 10
17cm
-3～5 × 10
17cm
-3; Epitaxial growth forms the N+ drift layer of table top, and thickness is 1～2 μ m, and nitrogen ion doping concentration is 1 × 10
17cm
-3～5 × 10
17cm
-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane;
Step c, N+ drift layer etching is table top: N+ drift layer is etched into a table top, the deep equality of table surface height and N+ drift layer, mesa width is 3 μ m～4 μ m; Its process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Steps d, epitaxial growth P-epitaxial loayer: one deck P-epitaxial loayer of growing on N-type drift region and N+ drift layer table top, thickness is 3 μ m, Al-doping concentration is 5 × 10
17cm
-3～1 × 10
18cm
-3;
Step e, epitaxial growth N+ source region layer: one deck N+ source region layer of growing on P-epitaxial loayer, thickness is 0.5 μ m, doping content is 5 × 10
18cm
-3;
Step f, etching grooving: adopt ICP etching to form groove directly over N-type heavy doping drift layer table top, width is 6 μ m, and the degree of depth is 3 μ m, and two of groove base angles are wrapped up by P-epitaxial loayer like this;
Step g, etching forms source region: adopt ICP etching to form source region contact;
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO
2, thickness is 100nm;
Step I, depositing polysilicon: the groove gate medium SiO in groove grid
2upper deposit polySi layer;
Step j, opening contact hole: prepare passivation layer, open electrode contact hole;
Step k, prepares electrode: evaporated metal, prepare electrode.
Based on each embodiment of above-mentioned steps, as described below:
Embodiment mono-:
Step a1, epitaxial growth N-type drift region, as shown in a in Fig. 2;
First the silicon carbide substrates sheet of N-type is carried out to RCA standard cleaning, then on whole substrate slice, epitaxial growth thickness is 10 μ m, and nitrogen ion doping concentration is 1 × 10
15cm
-3n-drift layer, its process conditions are: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts liquid nitrogen.
Step b1, epitaxial growth forms the N+ drift layer of table top, as shown in the b in Fig. 2;
The thick N+ drift layer of 1 μ m of growing on N-drift layer, nitrogen ion doping concentration is 1 × 10
17cm
-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane, and carrier gas adopts pure hydrogen, and doped source adopts liquid nitrogen.
Step c1, N+ drift layer etching forms table top, as shown in the c in Fig. 2;
First magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, and N+ trap is etched into mesa structure, it is 3 μ m that table surface height equals N+ well depth degree mesa width.Finally remove photoresist, go etch mask, be washed to mating plate.ICP etch technological condition is: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Steps d 1, epitaxial growth P-epitaxial loayer, as shown in the d in Fig. 2;
The a layer thickness of growing on N-type drift region and heavily doped drift region table top is 3 μ m, and Al-doping concentration is 5 × 10
17cm
-3p-epitaxial loayer, its epitaxial growth technology condition is: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts trimethyl aluminium.
Step e1, epitaxial growth N+ source region layer, as shown in the e in Fig. 2;
The a layer thickness of growing on P-epitaxial loayer is 0.5 μ m, and nitrogen ion doping concentration is 5 × 10
18cm
-3n-type silicon carbide epitaxial layers, as N+ source region layer, its process conditions are: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts liquid nitrogen.
Step f1, etching grooving, as shown in the f in Fig. 2;
First magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, the width that etches groove is 6 μ m, the degree of depth is 3 μ m, finally removes photoresist, and goes etch mask, is washed to mating plate.Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Step g 1, etching forms source region, as shown in the g in Fig. 2;
First magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, forms source region contact hole, finally removes photoresist, and goes etch mask, is washed to mating plate.Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Step h1, oxidation forms groove grid, as shown in the h in Fig. 2;
Adopt dry oxygen technique to prepare SiO at 1150 DEG C
2grid, thickness is 100nm, then at 1050 DEG C, N
2under atmosphere, anneal, reduce SiO
2the roughness of film surface.
Step I 1, depositing polysilicon, as shown in the i in Fig. 2;
Adopt low pressure hot wall chemical vapor deposition method growth ploySi to fill up groove, deposition temperature is 600～650 DEG C, and deposit pressure is 60～80Pa, and reacting gas is silane and hydrogen phosphide, carrier gas is helium, then gluing photoetching, etching ploySi layer, form polysilicon gate, finally remove photoresist, clean.
Step j1, opening contact hole, as shown in the j in Fig. 2;
At device surface deposit one deck field oxygen or Si
3n
4layer, then gluing photoetching, corrosion and passivation layer is opened electrode contact hole, finally removes photoresist, and cleans.
Step k1, prepares electrode, as shown in the k in Fig. 2;
Electron beam evaporation Ti/Ni/Au makes front grid, source electrode, and then gluing photoetching, corrosion of metals forms front grid, and source electrode contact figure, removes photoresist, and cleans.
Electron beam evaporation Ti/Ni/Au makes back side drain electrode overleaf, then makes front grid, and source electrode finally encloses short annealing 3min in Ar atmosphere, and temperature is 1050 DEG C.
Embodiment bis-:
Step a2, epitaxial growth N-type drift region;
First the silicon carbide substrates sheet of N-type is carried out to RCA standard cleaning, then on whole substrate slice, epitaxial growth thickness is 20 μ m, and nitrogen ion doping concentration is 5 × 10
15cm
-3n-drift layer, its process conditions are: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts liquid nitrogen.
Step b2, epitaxial growth forms the N+ drift layer of table top;
The thick N+ drift layer of 2 μ m of growing on N-drift layer, nitrogen ion doping concentration is 5 × 10
17cm
-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane, and carrier gas adopts pure hydrogen, and doped source adopts liquid nitrogen.
Step c2, N+ drift layer etching forms table top;
First magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, and N+ drift layer is etched into mesa structure, table surface height equals N+ drift layer thickness, mesa width is 4 μ m.Finally remove photoresist, go etch mask, be washed to mating plate.ICP etch technological condition is: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Steps d 2, epitaxial growth P-epitaxial loayer;
The a layer thickness of growing on N-type drift region and heavily doped drift region table top is 3 μ m, and Al-doping concentration is 1 × 10
18cm
-3p-epitaxial loayer, its epitaxial growth technology condition is: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts trimethyl aluminium.
Step e2 is identical with the step e1 of embodiment mono-.
Step f2 is identical with the step f1 of embodiment mono-.
Step g 2 is identical with the step g 1 of embodiment mono-.
Step h2 is identical with the step h1 of embodiment mono-.
Step I 2 is identical with the step I 1 of embodiment mono-.
Step j2 is identical with the step j1 of embodiment mono-.
Step k2 is identical with the step k1 of embodiment mono-.
Embodiment tri-:
Step a3, epitaxial growth N-type drift region;
First the silicon carbide substrates sheet of N-type is carried out to RCA standard cleaning, then on whole substrate slice, epitaxial growth thickness is 15 μ m, and nitrogen ion doping concentration is 3 × 10
15cm
-3n-drift layer, its process conditions are: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts liquid nitrogen.
Step b3, epitaxial growth forms the N+ drift layer of table top;
The thick N+ drift layer of 1.5 μ m of growing on N-drift layer, nitrogen ion doping concentration is 3 × 10
17cm
-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane, and carrier gas adopts pure hydrogen, and doped source adopts liquid nitrogen.
Step c3, N+ drift layer etching forms table top;
First magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, and N+ drift layer is etched into mesa structure, table surface height equals N+ drift layer thickness, mesa width is 3.5 μ m.Finally remove photoresist, go etch mask, be washed to mating plate.ICP etch technological condition is: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
Steps d 3, epitaxial growth P-epitaxial loayer;
The a layer thickness of growing on N-type drift region and heavily doped drift region table top is 3 μ m, and Al-doping concentration is 8 × 10
17cm
-3p-epitaxial loayer, its epitaxial growth technology condition is: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts trimethyl aluminium.
Step e3 is identical with the step e1 of embodiment mono-.
Step f3 is identical with the step f1 of embodiment mono-.
Step g 3 is identical with the step g 1 of embodiment mono-.
Step h3 is identical with the step h1 of embodiment mono-.
Step I 3 is identical with the step I 1 of embodiment mono-.
Step j3 is identical with the step j1 of embodiment mono-.
Step k3 is identical with the step k1 of embodiment mono-.
The foregoing is only preferred embodiment of the present invention, is only illustrative for invention, and nonrestrictive.Those skilled in the art is understood, and in the spirit and scope that limit, can carry out many changes to it in invention claim, amendment, and even equivalence, but all will fall within the scope of protection of the present invention.
Claims (10)
1. epitaxial growth forms a UMOSFET device preparation method for N-type heavy doping drift layer table top, it is characterized in that, this detailed process is:
Step a, epitaxial growth N-type drift region: epitaxial growth thickness is about 10 μ m～20 μ m on silicon carbide N+substrate print, and nitrogen ion doping concentration is 1 × 10
15cm
-3～5 × 10
15cm
-3n-type drift region;
Step b, epitaxial growth forms the N+ drift layer of table top: the heavily doped N+ drift layer of epitaxial growth one deck on N-type drift region, thickness is 1 μ m～2 μ m, nitrogen ion doping concentration is 1 × 10
17cm
-3～5 × 10
17cm
-3;
Step c, N+ drift layer etching is table top: N+ drift layer is etched into a table top, the deep equality of table surface height and N+ drift layer, mesa width is 3 μ m～4 μ m;
Steps d, epitaxial growth P-epitaxial loayer: one deck P-epitaxial loayer of growing on N-type drift region and N+ drift layer table top, thickness is 3 μ m, Al-doping concentration is 5 × 10
17cm
-3～1 × 10
18cm
-3;
Step e, epitaxial growth N+ source region layer: one deck N+ source region layer of growing on P-epitaxial loayer, thickness is 0.5 μ m, doping content is 5 × 10
18cm
-3;
Step f, etching grooving: adopt ICP etching to form groove directly over N-type heavy doping drift layer table top, width is 6 μ m, and the degree of depth is 3 μ m, and two of groove base angles are wrapped up by P-epitaxial loayer like this;
Step g, etching forms source region: adopt ICP etching to form source region contact;
Step h, oxidation forms groove grid: by thermal oxidation technology preparation vessel gate medium SiO
2, thickness is 100nm;
Step I, depositing polysilicon: the groove gate medium SiO in groove grid
2upper deposit polySi layer;
Step j, opening contact hole: prepare passivation layer, open electrode contact hole;
Step k, prepares electrode: evaporated metal, prepare electrode.
2. epitaxial growth according to claim 1 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, in above-mentioned steps a, first the silicon carbide substrates sheet of N-type is carried out to RCA standard cleaning, then on whole substrate slice, epitaxial growth thickness is 10 μ m～20 μ m, and nitrogen ion doping concentration is 1 × 10
15cm
-3～5 × 10
15cm
-3n-drift layer, its process conditions are: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts liquid nitrogen.
3. epitaxial growth according to claim 1 and 2 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, and in above-mentioned steps b,
Epitaxial growth forms the N+ drift layer of table top, and thickness is 1～2 μ m, and nitrogen ion doping concentration is 1 × 10
17cm
-3～5 × 10
17cm
-3, its process conditions are: temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane.
4. epitaxial growth according to claim 3 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, in above-mentioned steps c, process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
5. epitaxial growth according to claim 3 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, in above-mentioned steps d, one deck P-epitaxial loayer of growing on N-type drift region and N+ drift layer table top, thickness is 3 μ m, and Al-doping concentration is 5 × 10
17cm
-3～1 × 10
18cm
-3; Its process conditions are that temperature is 1600 DEG C, and pressure is 100mbar, and reacting gas adopts silane and propane, and carrier gas adopts pure hydrogen, and doped source adopts trimethyl aluminium.
6. epitaxial growth according to claim 3 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, in above-mentioned steps e, a layer thickness of growing on P-epitaxial loayer is 0.5 μ m, and nitrogen ion doping concentration is 5 × 10
18cm
-3n-type silicon carbide epitaxial layers, as N+ source region layer, its process conditions are: temperature is 1600 DEG C, pressure is 100mbar, reacting gas adopts silane and propane, carrier gas adopts pure hydrogen, doped source adopts liquid nitrogen.
7. epitaxial growth according to claim 6 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, and in above-mentioned steps f, first magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, the width that etches groove is 6 μ m, the degree of depth is 3 μ m, finally removes photoresist, and goes etch mask, is washed to mating plate; Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
8. epitaxial growth according to claim 6 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, and in above-mentioned steps g, first magnetron sputtering one deck
ti film as ICP etch mask, then gluing photoetching, carries out ICP etching, forms source region contact hole, finally removes photoresist, and goes etch mask, is washed to mating plate; Process conditions are: ICP coil power 850W, source power 100W, reacting gas SF
6and O
2be respectively 48sccm and 12sccm.
9. epitaxial growth according to claim 8 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, in above-mentioned steps h, adopts dry oxygen technique to prepare SiO at 1150 DEG C
2grid, thickness is 100nm, then at 1050 DEG C, N
2under atmosphere, anneal, reduce SiO
2the roughness of film surface.
10. epitaxial growth according to claim 8 forms the UMOSFET device preparation method of N-type heavy doping drift layer table top, it is characterized in that, in above-mentioned steps i, adopt low pressure hot wall chemical vapor deposition method growth ploySi to fill up groove, deposition temperature is 600～650 DEG C, and deposit pressure is 60～80Pa, and reacting gas is silane and hydrogen phosphide, carrier gas is helium, then gluing photoetching, etching ploySi layer, forms polysilicon gate, finally remove photoresist, clean.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110212020A (en) * | 2019-05-29 | 2019-09-06 | 西安电子科技大学 | A kind of MOSFET element and preparation method thereof of the unilateral depth L shape base region structure of silicon carbide |
| CN111834462A (en) * | 2018-06-28 | 2020-10-27 | 华为技术有限公司 | Semiconductor device and manufacturing method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060038223A1 (en) * | 2001-07-03 | 2006-02-23 | Siliconix Incorporated | Trench MOSFET having drain-drift region comprising stack of implanted regions |
| US20090280609A1 (en) * | 2008-04-14 | 2009-11-12 | Denso Corporation | Method of making silicon carbide semiconductor device |
| CN103426924A (en) * | 2012-05-14 | 2013-12-04 | 无锡华润上华半导体有限公司 | Groove-type power MOSFET and manufacturing method thereof |
-
2014
- 2014-04-21 CN CN201410166481.3A patent/CN103928346B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060038223A1 (en) * | 2001-07-03 | 2006-02-23 | Siliconix Incorporated | Trench MOSFET having drain-drift region comprising stack of implanted regions |
| US20090280609A1 (en) * | 2008-04-14 | 2009-11-12 | Denso Corporation | Method of making silicon carbide semiconductor device |
| CN103426924A (en) * | 2012-05-14 | 2013-12-04 | 无锡华润上华半导体有限公司 | Groove-type power MOSFET and manufacturing method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111834462A (en) * | 2018-06-28 | 2020-10-27 | 华为技术有限公司 | Semiconductor device and manufacturing method |
| CN111834462B (en) * | 2018-06-28 | 2024-02-09 | 华为技术有限公司 | Semiconductor device and manufacturing method |
| CN110212020A (en) * | 2019-05-29 | 2019-09-06 | 西安电子科技大学 | A kind of MOSFET element and preparation method thereof of the unilateral depth L shape base region structure of silicon carbide |
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