JP2002057310A - Method of forming soi substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce manufacturing cost by making formation of a poly Si layer for flattening a step-difference unnecessary and improving yield of sticking, in the case that an SOI substrate having a back gate electrode is formed by using a sticking method. SOLUTION: In a forming method of the SOI substrate by using a sticking method, a step-difference is formed on a first semiconductor substrate 1. An insulating film 3 for polishing stopper which has a bored part 8 of a prescribed depth is formed on a forming surface of the step-difference. Poly Si is deposited on the insulating film 3, and the bored part 8 is filled with the poly Si. An oxide film 9 for preventing dishing is formed and flattened, thereby forming a back gate electrode BG. A second semiconductor substrate 7 is stuck on the flattened surface via an oxide film 10 for sticking, thereby forming the SOI substrate 100A having the back gate electrode BG.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an SOI substrate having a back gate electrode by a bonding method.

[0002]

2. Description of the Related Art An SOI (Sion Insulator) substrate is formed by forming a single-crystal Si semiconductor layer (SOI layer) on an insulating film. Has been made.

[0003] One method of manufacturing an SOI substrate is a bonding method. FIG. 4 is a manufacturing process diagram when an SOI substrate having a back gate electrode is formed by a bonding method.

In this method, first, the first semiconductor substrate 1
A recess 2 is formed by a trench method (dry etching method), and SiO _{2 is used} as an insulating film 3 for a polishing stopper.
A film is formed with a thickness of about 50 nm (FIG. 4A).

Next, C is deposited on the polishing stopper insulating film 3.
PolySi deposited by VD method and PolyS for back gate
An i-layer 4 is formed with a thickness of about 300 nm (FIG. 4B).

A resist is patterned on the back gate PolySi layer 4 and the back gate PolySi layer 4 is etched to leave the back gate PolySi layer 4 only at the gate electrode portion, thereby forming a back gate electrode BG ( FIG. 4 (c)).

Next, an insulating oxide film 5 is deposited to a thickness of about 600 nm on the back gate electrode BG and the insulating film 3 for the polishing stopper, and the insulating oxide film 5 completely surrounds the back gate electrode BG (FIG. 4D). ). In this state, the step of the oxide insulating film 5 corresponding to the total thickness of the back gate electrode BG and the stopper insulating film 3 is 350 nm.

In order to fill the step, a step flattening Poly is used.
An Si layer 6 is formed by a CVD method (FIG. 4E). The thickness of the step flattening PolySi layer 6 may be a step 35
A total of about 5 μm is formed by combining 0 nm and a margin of 2 to 3 μm.

[0009] The claw portion of the CVD furnace, which supported the semiconductor substrate 1 by forming the step flattening polySi layer 6, has po
lySi grows in a projection shape. Since these projections have a bad influence on polishing and bonding later, they are removed before flattening polishing in the next step.

After removing the projections of polySi, the PolySi layer 6 for flattening a step is flattened by flattening polishing, and its surface is finished to a surface that can be bonded (FIG. 4).
(F)). This flattening polishing is performed using a polishing pad made of a polyurethane foam polishing pad and colloidal silica having an average particle diameter of 80 nm. Finishing of the surface after removing the step by flattening polishing is performed using a polishing slurry of colloidal silica having an average particle diameter of 40 nm, and the surface roughness Ra is set to a level of Ra = 0.4 nm.

The first semiconductor substrate 1 having the flattened step and the second semiconductor substrate 7 are bonded together (FIG. 4G). At the time of this bonding, RCA cleaning or the like is performed in advance so that particles and the like are not attached to the surface to be bonded, and OH is present on the surface so that bubbles are not generated at the time of bonding. In addition, as a bonding method, first, both substrates are overlapped, and then heat-treated at 1100 ° C. for 30 minutes to 120 minutes in an oxygen or nitrogen atmosphere to form a strong bonding state.

Next, the first semiconductor substrate 1 is ground and polished from the non-bonded surface side (FIG. 4 (h)). The remaining portion of the first semiconductor substrate 1 after the grinding and polishing becomes an SOI layer serving as an active layer, and the grinding depth is set to a depth at which damage during grinding does not reach the SOI layer. More specifically, the first semiconductor substrate 1 is left with a thickness of about 7 μm. Polishing is performed at about 3 μm.

As a grinding method, it is preferable to use a diamond grindstone (grindstone # 2000) while rotating at a high speed because the grinding speed is high and the precision of the ground surface is good. However, even in this case, polishing is performed after the grinding because the ground surface is deeply damaged by diamond and the surface roughness is not enough to form a transistor.

Further, in order to make the remaining film thickness of the semiconductor substrate 1 on the stopper insulating film 3 uniform, PACE processing by a plasma etching method is performed, and the film thickness of the semiconductor substrate 1 on the stopper insulating film 3 is set to 200 nm. Finish to ± 50 nm. After that, by selective polishing, the semiconductor substrate 1 is left only in the concave portion of the step of the insulating film 3 for polishing stopper, and the SOI
An SOI substrate having a layer is obtained (FIG. 4 (i)).

The selective polishing is performed using a polishing pad and a polishing liquid. The polishing liquid includes the semiconductor substrate 1 (S
A polishing liquid (for example, an alkaline polishing liquid such as ethylenediamine) having a high polishing rate ratio between Si forming the OI layer and SiO ₂ forming the insulating film 3 for the polishing stopper is used. As a result, the progress of the polishing is stopped when the polishing reaches the convex portions of the stopper insulating film 3.

[0016]

However, according to the conventional method shown in FIG.
In order to form a thickness of 5 μm by the VD method (FIG. 4E),
There is a problem that a large amount of gas and time are required.

The poly-Si layer 6 for flattening the step is 5 μm thick.
Since it is necessary to flow gas into the CVD furnace for a long time in order to form to a thickness of
lySi deposits. For this reason, frequent cleaning in the furnace is required, and the working efficiency is very low.

Further, polySi grows in a protruding manner at the claw portion of the CVD furnace which has supported the semiconductor substrate 1 when the step flattening polySi layer 6 is formed, and this protruding material is flattened in the next step. There is a complication that it must be removed before polishing.

Although there is a method of forming an oxide film for flattening the step in place of the polySi layer 6 for flattening the step, a great amount of time and gas are required for forming the oxide film in this case (Japanese Patent Application Laid-Open No. HEI 9-163572). No. 8-153780).

When the flattening polishing (FIG. 4F) of the step flattening polySi layer 6 is performed, polySi
Since the layer 6 becomes thinner and becomes thicker in the concave portions, the planarized and polished surface polySi which is to be bonded to the second semiconductor substrate 7 is formed.
Grain size becomes uneven, and the bonding yield decreases.

A method of manufacturing an SOI substrate different from the manufacturing method of FIG. 4 is a SIMOX method. However, according to this method, oxygen ions are implanted into the entire surface, so that the crystal is damaged and the crystallinity is significantly impaired. .

Therefore, according to the present invention, when an SOI substrate having a back gate electrode is formed by the bonding method, the formation of the step flattening polySi layer 6 is not required, the yield of bonding is improved, and the manufacturing cost is improved. Is intended to be significantly reduced.

[0023]

In order to form an SOI substrate having a back gate electrode by a bonding method, the inventor of the present invention has designed to fill an opening formed in an insulating film on the substrate with polySi. Form a polySi layer and open the po
By forming the back gate electrode by flattening the polySi layer so that the lySi remains, the conventional step flattening po
It has been found that it is not necessary to form a lySi layer, and in particular, it is effective to form an oxide film for preventing dishing on the polySi layer in advance and then planarize the polySi layer in a specific procedure when planarizing the polySi layer. Was.

That is, the present invention relates to a method for manufacturing an SOI substrate by a substrate bonding method, wherein a step is formed on a first semiconductor substrate and a predetermined depth is formed on a step forming surface of the first semiconductor substrate. Forming an insulating film for a polishing stopper having an opening portion of polycrystalline silicon; depositing polySi on the insulating film for a polishing stopper to form a polySi layer for a back gate; filling the opening portion with polySi; An oxide film for preventing dishing is formed on the polySi layer, and a po for back gate is formed.
The lySi layer and the dishing prevention oxide film are polished so that the dishing prevention oxide film remains in the concave portions to flatten the surface, and the back gate polySi layer is further polished to expose a polishing stopper insulating film, thereby dishing. Removing the oxide film for prevention and planarizing the surface of the first semiconductor substrate to form a back gate electrode; forming an oxide film for bonding on the planarized surface or on the second semiconductor substrate;
Provided is a method for manufacturing an SOI substrate having a back gate electrode, which includes bonding a first semiconductor substrate and a second semiconductor substrate through a bonding oxide film.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings. In each of the drawings, the same reference numerals represent the same or equivalent components.

FIG. 1 is a manufacturing process diagram of one embodiment of the present invention. In this method, first, a concave portion 2 is formed in a first semiconductor substrate 1 by a trench method (dry etching method), and then a first polishing stopper insulating film 3a is formed of Si.
An O ₂ film is formed to a thickness of about 50 nm to 100 nm by a thermal oxidation method, and a SiO ₂ layer is formed by a CVD method as a second polishing stopper insulating film 3b having a lower density than the first polishing stopper insulating film 3a. A thickness corresponding to the thickness of a predetermined back gate electrode BG (for example, 300 nm)
(FIG. 1A).

Next, a second polishing stopper insulating film 3b is formed.
The step formed on the surface of the substrate is polished and flattened by the CMP method (FIG. 1B). In this case, polishing is performed, for example, by using ICI0.
Polishing slurry SC112 (manufactured by Cabot) is performed using a polishing pad of No. 00 and Suba400 (manufactured by Rodelnita).

Next, an opening 8 for embedding the back gate electrode BG is formed in the planarized second insulating film 3b for polishing stopper (FIG. 1C). The opening 8 is the second
A resist is applied to the polishing stopper insulating film according to an opening pattern and etched. The size and depth of the opening 8 can be controlled by the etching rate and the etching time of the first polishing stopper insulating film 3a and the second polishing stopper insulating film 3b.

The insulating film 3 for the polishing stopper having the opening 8 as described above (the first insulating film 3 for the polishing stopper)
As a method for forming the second polishing stopper insulating film 3b) and the second polishing stopper insulating film 3b, the first semiconductor substrate 1 exposes the etching of the second polishing stopper insulating film 3b and the first polishing stopper insulating film 3a. To the opening 8 by thermal oxidation.
An iO ₂ layer may be formed.

Next, a poly is formed on the polishing stopper insulating film 3.
The opening 8 is filled with polySi by depositing Si to form the back gate polySi layer 4 (FIG. 1).
(D)). Forming the back gate polySi layer 4
A doped polySi is used for controlling the resistance. Doping is S doped from the beginning
This may be performed by forming a layer using i, or by implanting ions after forming the layer. The thickness of the back gate polySi layer 4 is made substantially equal to the thickness of the second polishing stopper insulating film 3b.

Next, the polySi layer 4 for the back gate is flattened. When the back gate polySi layer 4 is simply flattened by CMP, the flattened surface is not flattened as shown in FIG.
ing) easily occurs. Therefore, in the present invention, the dishing preventing oxide film 9 is formed on the back gate polySi layer (FIG. 1E). As the dishing preventing oxide film 9, SiO ₂ , Si ₃ N ₄ or the like can be formed by a CVD method. The thickness of the dishing preventing oxide film 9 is preferably a thickness that can be easily removed with a polishing slurry containing abrasive grains, and more specifically, 10 to 200.
It is preferably set to nm. The dishing prevention oxide film 9 is polished by CMP, and the back gate poly is
The Si layer 4 is exposed, and the dishing preventing oxide film 9 is formed in the concave portion.
(FIG. 1F). Further, by selectively polishing the back gate polySi layer 4 of the convex portion, the second polishing stopper insulating film 3b is exposed, and the dishing preventing oxide film 9 is left (FIG. 1 (g)). In this selective polishing, the back gate polySi layer 4 is polished, but the second polishing stopper insulating film (SiO ₂ film) 3b
So that the polishing is stopped by
2nd insulating film for polishing stopper (SiO ₂ film)
Use an abrasive that sufficiently slows polishing of 3b. For example, a polishing pad of a nonwoven fabric substrate cloth and an ethylenediamine solution are used. The dishing preventing oxide film 9 remaining by the selective polishing is removed by wet etching or the like (FIG. 1).
(H)), a second polishing stopper insulating film (SiO 2
_The step formed between the ( ₂ film) 3b and the back gate polySi layer 4 is flattened by a CMP method or the like (FIG. 1 (i)).

Next, an SiO ₂ layer is formed on the flattened surface as a bonding oxide film 10 by 50 to 300 nm by CVD.
m (FIG. 1 (j)). In the present invention, the first semiconductor substrate 1 and the second semiconductor substrate 7 are bonded via the bonding oxide film 10, and the non-bonded surface of the first semiconductor substrate 1 is polished by an arbitrary method. The first semiconductor substrate remaining on the step portion of the insulating film 3 for polishing stopper is
An SOI substrate having a back gate electrode as a layer can be manufactured.
By forming the O ₂ film, the bonding surface of the first semiconductor substrate 1 and the second semiconductor substrate 7 becomes a Si—SiO ₂ junction, so that the bonding becomes more stable than the conventional Si—Si junction, The yield of bonding substrates can be improved.

In the present invention, when bonding the first semiconductor substrate 1 and the second semiconductor substrate 7 via the bonding oxide film 10, the bonding oxide film 10 is used.
May be formed on either the first semiconductor substrate 1 or the second semiconductor substrate 7, but preferably, the bonding oxide film 10 is formed on the first semiconductor substrate 1 as described below. Before bonding the first semiconductor substrate 1 and the second semiconductor substrate 7, hydrogen ions are implanted from the bonding oxide film 10 side of the first semiconductor substrate 1, and unnecessary portions of the first semiconductor substrate 1 are Is preferably removed.

That is, hydrogen ions are implanted from above the bonding oxide film 10 to form the peeling layer 11.
(K)). The depth of the peeling surface of the peeling layer 11 is set to be about 200 nm below the first polishing stopper insulating film 3a, and a polishing allowance 12 is left.

Next, a second layer is formed on the bonding oxide film 10.
2 and the two substrates are joined together (FIG. 2).
(L)). As a bonding method, by performing RCA cleaning in advance, particles and the like are not attached to the bonding surface, and an OH group is present on the bonding surface to prevent bubbles from entering during bonding. After the two substrates are overlapped with each other, the substrates are temporarily bonded by performing a heat treatment at about 350 to 450 ° C. in an oxygen or nitrogen atmosphere, and the temporarily bonded substrates are further heat treated at 550 to 650 ° C. Thereby, the first semiconductor substrate 1 is peeled off at the implanted hydrogen portion (FIG. 2).
(M)). Thereafter, heat treatment is performed at 800 ° C. to 1100 ° C. in a nitrogen atmosphere in order to strengthen the bonding between the bonding surfaces.

After the first semiconductor substrate 1 is peeled off, the remaining 100-500 on the first polishing stopper insulating film 3a.
The first semiconductor substrate 1 having a thickness of about nm is selectively polished, and the first semiconductor substrate 1 is left on the step difference of the first stopper insulating film 3a to obtain an SOI substrate 100A having an SOI layer (FIG. 2 (n)). ).

As a method of selective polishing, it is preferable to perform polishing using a polishing pad of a nonwoven fabric substrate and ethylenediamine. In this case, ethylenediamine has a concentration of 0.000.
Although the Si constituting the first semiconductor substrate 1 can be polished by diluting to 5 to 0.5%, the first polishing stopper insulating film 3 is formed.
The SiO ₂ constituting a is hardly polished. Thus, the polishing can be completed in a state where the polishing is stopped in the stopper insulating film 3. As a specific example of a preferable polishing pad, for example, a nonwoven fabric substrate cloth (Hardness 82 ((As
ker-c))-based on JISK-6301).

After the selective polishing, in order to improve the surface roughness of the SOI layer, it is preferable to polish the very surface of the SOI layer using a polishing slurry containing abrasive grains and a soft polishing pad. Thereby, the SOI substrate 100A with few surface defects
Can be obtained.

The release layer 11 peeled off from the first semiconductor substrate 1 can be reused by polishing the surface and reducing the roughness.

The present invention can take various aspects other than the aspect shown in FIG. For example, the first step forming a step
A semiconductor substrate having a Si layer formed by an epitaxial growth method may be used as the semiconductor substrate 1 of the above, and the SOI layer may be made of Si by the epitaxial growth method. Thus, surface defects of the SOI layer of the SOI substrate can be reduced.

In the method of manufacturing an SOI substrate according to the present invention, the methods such as grinding, polishing, and etching are not limited to the above-described methods.

[0042]

According to the method of the present invention, when an SOI substrate having a back gate electrode is formed by a bonding method, it is not necessary to form a polySi layer for flattening a step, and the yield of bonding is improved. And the manufacturing cost is significantly reduced.

[Brief description of the drawings]

FIG. 1 is a process explanatory diagram of one embodiment of the present invention.

FIG. 2 is a process explanatory diagram of one embodiment of the present invention.

FIG. 3 is an explanatory diagram of dishing caused by flattening a back gate polySi layer.

FIG. 4 is a manufacturing process diagram of an SOI substrate by a conventional bonding method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st semiconductor substrate, 2 ... concave part, 3 ... insulating film for polishing stoppers, 3a ... insulating film for 1st polishing stoppers 3b ... insulating film for 2nd polishing stoppers, 4 ... polySi layer for back gates, 5 ... insulating oxide film 6 ... polySi layer for flattening steps 7 ... second semiconductor substrate 8 ...
Opening portion, 9: Oxidation film for preventing dishing, 10: Oxide film for bonding, 11: Release layer, 12: Polishing allowance, 100A: SOI substrate, BG: Back gate electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336

Claims (4)

[Claims] 1. A method for manufacturing an SOI substrate by a substrate bonding method, wherein a step is formed in a first semiconductor substrate, and an opening having a predetermined depth is formed on a step forming surface of the first semiconductor substrate. Forming an insulating film for the polishing stopper having a surface, and depositing polySi on the insulating film for the polishing stopper to form a back gate po.
The opening is filled with polySi by forming a lySi layer, a dishing preventing oxide film is formed on the back gate polySi layer, and the back gate polySi layer and the dishing preventing oxide film are prevented from being dished in the concave portion. The surface of the first semiconductor substrate is polished by polishing so as to leave an oxide film for polishing, flattening the surface, further polishing the polySi layer for the back gate to expose an insulating film for a polishing stopper, removing the dishing prevention oxide film. A back gate electrode is formed by flattening the surface, an oxide film for bonding is formed on the flattened surface or on the second semiconductor substrate, and the first semiconductor substrate is bonded to the first semiconductor substrate via the oxide film for bonding. SO having a back gate electrode consisting of bonding a second semiconductor substrate
Method for manufacturing I substrate. 2. An insulating film for a polishing stopper having an opening having a predetermined depth is formed by forming an insulating film for a first polishing stopper on a step forming surface of a first semiconductor substrate. This is performed by forming a second polishing stopper insulating film having a lower density than the first polishing stopper insulating film on the polishing stopper insulating film, and opening the second polishing stopper insulating film. A method for manufacturing an SOI substrate according to claim 1. 3. An oxide film for bonding is formed on the planarized surface of the first semiconductor substrate, and then hydrogen ions are implanted from the side of the oxide film for bonding to form a peeling layer on the first semiconductor substrate. 3. The S according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate are bonded to each other via a bonding oxide film, and then the release layer of the first semiconductor substrate is removed.
A method for manufacturing an OI substrate. 4. The method for manufacturing an SOI substrate according to claim 1, wherein a semiconductor substrate having an Si layer formed by an epitaxial growth method is used as the first semiconductor substrate forming the step.