WO2021096114A1 - Method of manufacturing soi substrate - Google Patents

Method of manufacturing soi substrate Download PDF

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Publication number
WO2021096114A1
WO2021096114A1 PCT/KR2020/014917 KR2020014917W WO2021096114A1 WO 2021096114 A1 WO2021096114 A1 WO 2021096114A1 KR 2020014917 W KR2020014917 W KR 2020014917W WO 2021096114 A1 WO2021096114 A1 WO 2021096114A1
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Prior art keywords
single crystal
crystal silicon
epitaxial layer
layer
silicon epitaxial
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PCT/KR2020/014917
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French (fr)
Korean (ko)
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박진원
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(주)더숨
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Priority claimed from KR1020200022835A external-priority patent/KR102533585B1/en
Priority claimed from KR1020200032770A external-priority patent/KR102204732B1/en
Application filed by (주)더숨 filed Critical (주)더숨
Priority to CN202080003712.2A priority Critical patent/CN113133326A/en
Publication of WO2021096114A1 publication Critical patent/WO2021096114A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Definitions

  • the present invention relates to a method of manufacturing an SOI substrate. More specifically, it relates to a method for manufacturing an SOI substrate capable of improving productivity by having excellent surface uniformity and simplifying the manufacturing process.
  • SIMOX Seperation by Implanted Oxygen
  • Smart Cut forms a layer to be separated by growing a thermal oxide film on a silicon wafer, and implanting hydrogen ions to pass through the oxide film.
  • This method has a simple manufacturing process, but has a disadvantage in that the surface uniformity of the boundary of the ion implanted portion is not excellent.
  • FIG. 1 is a conceptual diagram showing a conventional SOI manufacturing process.
  • Conventional SOI wafers generally form an active SOI region through a photoresist/etch process while SOI is formed on the entire surface. Accordingly, since a separate process for forming the active SOI is required, productivity is lowered, and there is a problem in that the quality of the SOI is deteriorated in the process of forming the active SOI region.
  • an object of the present invention is to provide a method of manufacturing an SOI substrate capable of forming an SOI layer only in an active region from the beginning.
  • an object of the present invention is to provide a method of manufacturing an SOI substrate capable of simplifying the manufacturing process, reducing process time and cost, and improving productivity.
  • the above object of the present invention is, (a) forming a silicon release layer on one surface of the first single crystal silicon substrate; (b) forming a first single crystal silicon epitaxial layer on the silicon exfoliation layer; (c) forming a plurality of insulating patterns on one surface of the first single crystal silicon epitaxial layer; (d) forming a second single crystal silicon epitaxial layer on the first single crystal silicon epitaxial layer and the insulating pattern; (e) planarizing the second single crystal silicon epitaxial layer; (f) bonding a first single crystal silicon substrate and a second single crystal silicon substrate having an oxide layer formed thereon; (g) applying energy to the silicon exfoliation layer to separate and remove the first single crystal silicon substrate; (h) removing the first single crystal silicon epitaxial layer while reducing its thickness in one surface direction from the other surface of the first single crystal silicon epitaxial layer.
  • steps (a) and (b) (1) oxidizing the pores and the surface of the silicon release layer; (2) removing oxides on the surface of the silicon release layer; (3) The step of recrystallizing the surface of the silicon release layer may be further included.
  • the thickness of the second single crystal silicon epitaxial layer may be reduced and planarized up to the portion where the insulating pattern is formed.
  • the insulating pattern may be made of at least one of silicon oxide and silicon nitride.
  • the planarization in step (e) may be performed by H 2 annealing, Ar annealing, or CMP method.
  • the silicon release layer is cut by applying energy by a water-jet method or a mechanical shock, mechanical lift method, and a first single crystal silicon substrate It may be a step of separating and removing them.
  • the thickness may be reduced to the portion where the insulating pattern is formed.
  • the insulating pattern may function as a stopper for reducing the thickness.
  • steps (e) and (f) between steps (e) and (f), (e2) forming a dishing oxide layer on at least the second single crystal silicon epitaxial layer; may be further included.
  • the dishing oxide layer in step (e2), may be formed in the groove portion of the second single crystal silicon epitaxial layer planarized to a height lower than the height of the insulating pattern.
  • the dishing oxide layer may be formed on the groove portion and the insulating pattern of the second single crystal silicon epitaxial layer planarized to a height lower than the height of the insulating pattern.
  • the step of flattening and reducing the thickness of the dishing oxide layer may be further included.
  • the present invention has the effect of simplifying the manufacturing process, reducing process time and cost, and improving productivity.
  • FIG. 1 is a conceptual diagram illustrating a conventional SOI process.
  • FIGS. 2 to 9 are schematic diagrams showing a manufacturing process of an SOI substrate according to an embodiment of the present invention.
  • 10 to 15 are schematic diagrams showing a manufacturing process of an SOI substrate according to another embodiment of the present invention.
  • 2 to 9 are schematic diagrams showing a manufacturing process of the SOI substrate 100 according to an embodiment of the present invention.
  • 2 to 9 show side cross-sectional views of a portion of the SOI substrate, but the actual SOI substrate 100 may have a larger scale, and the insulating pattern 140 may have a larger number of plural numbers in the horizontal and vertical directions on the plane. It should be noted that the pattern can be formed apart from each other.
  • the method of manufacturing the SOI substrate 100 includes the steps of: (a) forming a silicon release layer 120 on one surface of the first single crystal silicon substrate 110, (b) a silicon release layer Forming a first single crystal silicon epitaxial layer 130 on 120, (c) forming a plurality of insulating patterns 140 on one surface of the first single crystal silicon epitaxial layer 130, ( d) forming a second single crystal silicon epitaxial layer 150' on the first single crystal silicon epitaxial layer 130 and the insulating pattern 140, (e) the second single crystal silicon epitaxial layer 150' (F) bonding the first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 having the oxide layer 220 formed thereon; (g) applying energy (S) to the silicon peeling layer 120 to separate and remove the first single crystal silicon substrate 110, (h) from the other surface of the first single crystal silicon epitaxial layer 130 to one surface direction It characterized in that it comprises the step of removing while reducing the thickness.
  • the SOI substrate 100 includes the steps of: (a
  • a first single crystal silicon substrate 110 may be prepared.
  • the first single crystal silicon substrate 110 may be a single crystal silicon wafer, or a single crystal silicon substrate such as a square may be used.
  • a silicon exfoliation layer 120 may be formed on one surface (eg, an upper surface) of the first single crystal silicon substrate 110.
  • the silicon release layer 120 may be formed on the first single crystal silicon substrate 110 by using a known method such as anodizing.
  • a first single crystal silicon epitaxial layer 130 may be formed on the silicon exfoliation layer 120.
  • the first single crystal silicon epitaxial layer 130 may be formed using a known epitaxial method.
  • a first single crystal silicon epitaxial layer 130 may be formed from one surface (eg, an upper surface) of the silicon exfoliation layer 120.
  • the first single crystal silicon epitaxial layer 130 may be formed to a thickness of about 0.5 to 1 ⁇ m.
  • a process of blocking pores on the upper surface of the silicon peeling layer 120 may be further performed.
  • oxidation is performed on the silicon peeling layer 120 to form an oxide layer (not shown) on the voids and the surface, and the oxide layer formed on the surface portion with HF or the like may be removed.
  • hydrogen heat treatment may be performed at about 1,000° C. or higher to perform recrystallization of the upper surface voids of the silicon release layer 120. Accordingly, when forming the first single crystal silicon epitaxial layer 130 on the upper surface of the silicon exfoliation layer 120, there is an advantage that it is easy to form a thinner thickness without defects.
  • a plurality of insulating patterns 140 may be formed on one surface (eg, an upper surface) of the first single crystal silicon epitaxial layer 130.
  • the insulating pattern 140 is preferably made of a silicon oxide material, but is not limited thereto, and a silicon nitride material may be used.
  • the insulating pattern 140 may be formed using a known thin film forming method such as deposition or printing without limitation.
  • the plurality of insulating patterns 140 may be formed to be spaced apart from each other. If the target range serves as a stopper for reducing the thickness of the first and second single crystal silicon epitaxial layers 130 and 150 to be described later and the range for separating the active SOI regions, the first single crystal silicon epitaxial layer There is no limitation on the form in which the plurality of insulating patterns 140 are formed, such as formed parallel to or intersecting in one direction on one surface of the seam layer 130. According to an embodiment, the insulating pattern 140 may be formed on the first single crystal silicon epitaxial layer 130 to have a thickness of about 30 nm and a width of about 5 to 10 ⁇ m.
  • a second single crystal silicon epitaxial layer 150 ′ may be formed on the first single crystal silicon epitaxial layer 130 and the insulating pattern 140.
  • the second single crystal silicon epitaxial layer 150 ′ may be formed using a known epitaxial method.
  • a second single crystal silicon epitaxial layer 150 ′ may be formed from the exposed surface of the first single crystal silicon epitaxial layer 130.
  • the second single crystal silicon epitaxial layer 150 ′ may be formed to a thickness of about 10 to 50 nm.
  • the second single crystal silicon epitaxial layer 150 ′ may be planarized (P).
  • one surface (upper surface) of the second single crystal silicon epitaxial layer 150 ′ is mirror-finished and at the same time, a portion of the upper portion of the second single crystal silicon epitaxial layer 150 ′ is partially removed to reduce the thickness to be thin (150). '-> 150).
  • the planarization (P) is preferably performed through Chemical Mechanical Polishing (CMP), hydrogen heat treatment (H 2 anneal), and argon heat treatment (Ar anneal), but is not limited thereto.
  • the second single crystal silicon epitaxial layer 150 ′ is planarized (P), a thickness variation may be reduced and a thickness may be reduced (150 ′ -> 150 ′) to be thin.
  • the planarization (P) is not performed at least to the extent that the insulating pattern 140 is removed, and the insulating pattern 140 functions as a stopper and may be performed up to the height of the insulating pattern 140.
  • the second single crystal silicon epitaxial layer 150 may have a thickness of about 30 nm through hydrogen heat treatment at 1,100 to 1,150°C, argon heat treatment at 1,200°C, or CMP.
  • a second single crystal silicon substrate 210 may be prepared.
  • a single crystal silicon wafer such as the first single crystal silicon substrate 110 may be used, or a single crystal silicon substrate such as a square may be used.
  • the second single crystal silicon substrate 210 preferably has the same size and shape as the first single crystal silicon substrate 110, but is not limited thereto.
  • the second single crystal silicon substrate 210 may have an area corresponding to the sum of the areas of the plurality of first single crystal silicon substrates 110.
  • the silicon peeling layer 120 of FIG. 5, the first single crystal silicon epitaxial layer 130, the insulating pattern 140, the first single crystal silicon epitaxial layer 150, and A subsequent process may be performed by bonding a plurality of first single crystal silicon substrates 110 on which the oxide layer 160 is formed at predetermined intervals.
  • the oxide layer 220 is formed on the surface of the second single crystal silicon substrate 210.
  • the oxide layer 220 may be formed on the surface of the second single crystal silicon substrate 210 through a known thin film formation method. According to an embodiment, the oxide layer 220 may be formed to a thickness of about 10 nm to 20 nm.
  • first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 may be bonded.
  • the surfaces of the first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 are not bonded to each other, and the first and second single crystal silicon epitaxial layers 130 and 150 and the oxide layers 160 and 220 are interposed. Can be joined. Bonding may be performed through heat treatment at a temperature of several hundreds to °C under an environment such as vacuum or inert gas. Since the material of the oxide layer 160 and the oxide layer 220 is the same, bonding may be better performed at the interface. In addition, after the bonding is completed, the oxide layers 230 (160, 220) (see FIG. 7) may act as an insulator in the SOI substrate 100.
  • the first single crystal silicon substrate 110 may be separated and removed by applying (S) energy to the silicon peeling layer 120.
  • the application of energy (S) may be performed by a water-jet method.
  • the application of energy (S) may be performed by a mechanical shock (mechanical lift) method of applying vibration, shock, or the like.
  • the silicon peeling layer 120 can be easily cut when energy is applied (S) from the side because of its porous property. As the silicon exfoliation layer 120 is cut, the first single crystal silicon substrate 110 may be separated.
  • the present invention has the advantage of reusability by cleaning and removing porous silicon remaining on one surface of the first single crystal silicon substrate 110.
  • the first single crystal silicon epitaxial layer 130 may be removed (G) while reducing the thickness in one surface direction from the other surface.
  • One surface of the first single crystal silicon epitaxial layer 130 is a surface on which the insulating pattern 140 and the second single crystal silicon epitaxial layer 150 are formed, and the other surface is a silicon release layer 120 by cutting the silicon release layer 120. ') corresponds to the remaining side. That is, after the first single crystal silicon substrate 110 is separated, the remaining silicon peeling layer 120 ′ and the first single crystal silicon epitaxial layer 130 are removed and the second single crystal silicon epitaxial layer 150 is removed.
  • the other surface (the upper surface in FIG. 8) can be flattened (G).
  • the thickness reduction and removal (G) of the first single crystal silicon epitaxial layer 130 may be performed using a method such as grinding, polishing, or etching. For example, after the first rough grinding is performed up to the thickness of the ⁇ m unit, the thickness reduction can be finely controlled by using CMP and etching in the second order from the ⁇ m to the thickness of the nm level.
  • thickness reduction and removal (G) it is preferable to perform thickness reduction and removal (G) up to the portion where the insulating pattern 140 is formed. That is, oxides and nitrides of the insulating pattern 140 may serve as a stopper for reducing the thickness.
  • manufacturing of the SOI substrate 100 may be completed after thickness reduction and removal (G).
  • the insulating pattern 140 partitions the second single crystal silicon epitaxial layer 150, and regions of the partitioned second single crystal silicon epitaxial layer 150 may be used as an active SOI (active SOI). Thereafter, a process of forming a semiconductor or a memory may be further performed.
  • 10 to 15 are schematic diagrams showing a manufacturing process of an SOI substrate according to another embodiment of the present invention.
  • a method of manufacturing an SOI substrate includes (a) forming a silicon release layer 120 on one surface of the first single crystal silicon substrate 110, (b) on the silicon release layer 120 Forming a first single crystal silicon epitaxial layer 130 on the surface, (c) forming a plurality of insulating patterns 140 on one surface of the first single crystal silicon epitaxial layer 130, (d) a first Forming a second single crystal silicon epitaxial layer 150' on the single crystal silicon epitaxial layer 130 and the insulating pattern 140, (e) planarizing one surface of the second single crystal silicon epitaxial layer 150' (P), (f) forming an oxide layer 160 on at least an upper portion (V) of the second single crystal silicon epitaxial layer 150, (g) on the first single crystal silicon substrate 110 and the surface Bonding the second single crystal silicon substrate 210 on which the oxide layer 220 is formed, (h) applying energy to the silicon release layer 120 (S) to separate and remove the first single crystal silicon substrate 110, and (i) removing (G
  • Steps (a) to (e) are the same as those of FIGS. 2 to 5, and thus detailed descriptions are omitted.
  • FIG. 5 there may be a case in which planarization is not performed so that the second single crystal silicon epitaxial layer 150 is accurately reduced to the same level as the height of the insulating pattern 140.
  • the second single crystal silicon epitaxial layer 150 does not have the same height as the insulating pattern 140 and may be dished to become more pitted.
  • an empty space V is formed on the second single crystal silicon epitaxial layer 150 and the surface of the upper surface is not a mirror surface, the second single crystal silicon substrate 210 and the second single crystal silicon substrate 210 are Problems of poor bonding may occur.
  • the dishing oxide layer 160 may be further formed.
  • a dishing oxide layer 160 may be formed on the second single crystal silicon epitaxial layer 150 and the insulating pattern 140.
  • a dishing oxide layer 160 ′ may be formed on at least the upper portion V of the second single crystal silicon epitaxial layer 150.
  • the dishing oxide layer 160 may be formed through a known thin film formation method such as thermal oxidation or CVD.
  • (a) of FIG. 11 is a dishing oxide layer 160 formed on the second single crystal silicon epitaxial layer 150 and the insulating pattern 140 through a CVD method.
  • b) may correspond to the formation of the dishing oxide layer 160 ′ on the second single crystal silicon epitaxial layer 150 through a thermal oxidation method.
  • the dishing oxide layers 160 and 160 ′ may be formed to have a thickness of about 10 nm to 20 nm.
  • the dishing oxide layer 160 fills the empty space V of the second single crystal silicon epitaxial layer 150 and at the same time, the second single crystal silicon epitaxial layer 150 and the insulating pattern 140 are formed. It can be formed flat on the top. Alternatively, after the dishing oxide layer 160 is formed, the dishing oxide layer 160 may be flattened by further performing a CMP process or the like. In (b) of FIG. 11, the dishing oxide layer 160 ′ is formed flat on the second single crystal silicon epitaxial layer 150 while filling the empty space V of the second single crystal silicon epitaxial layer 150. I can.
  • a second single crystal silicon substrate 210 may be prepared. This can be done in the same manner as in FIG. 6.
  • first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 may be bonded.
  • the surfaces of the first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 are not bonded to each other, and the first and second single crystal silicon epitaxial layers 130 and 150 and the dishing oxide/oxide layer 160 and 220 are It can be joined by means of. Bonding may be performed through heat treatment at a temperature of several hundreds to °C under an environment such as vacuum or inert gas. Since the material of the dishing oxide layer 160 and the oxide layer 220 is the same, bonding may be better performed at the interface.
  • the oxide layers 230 160, 220
  • FIG. 13 may function as an insulator in the SOI substrate 100.
  • the first single crystal silicon substrate 110 may be separated and removed by applying (S) energy to the silicon peeling layer 120. This can be done in the same manner as in FIG. 7.
  • the first single crystal silicon epitaxial layer 130 may be removed (G) while reducing the thickness in one direction from the other surface. This can be done in the same manner as in FIG. 8.
  • manufacturing of the SOI substrate 100 may be completed after thickness reduction and removal (G).
  • the insulating pattern 140 partitions the second single crystal silicon epitaxial layer 150, and regions of the partitioned second single crystal silicon epitaxial layer 150 may be used as an active SOI. Thereafter, a process of forming a semiconductor or a memory may be further performed.
  • an SOI layer can be formed only in the active area from the beginning, an SOI substrate having excellent surface uniformity can be manufactured, and the manufacturing process can be simplified to reduce process time and cost, and improve productivity. There is.

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Abstract

The present invention relates to a method of manufacturing a multi-SOI substrate, the method comprising the steps of: (a) forming a silicon exfoliation layer on one surface of a first single crystal silicon substrate; (b) forming a first single crystal silicon epitaxial layer on the silicon exfoliation layer; (c) forming a plurality of insulating patterns on one surface of the first single crystal silicon epitaxial layer; (d) forming a second single crystal silicon epitaxial layer on the first single crystal silicon epitaxial layer and the insulating patterns; (e) flattening the second single crystal silicon epitaxial layer; (f) bonding the first single crystal silicon substrate and a second single crystal silicon substrate having an oxide layer formed on the surface thereof; (g) separating and removing the first single crystal silicon substrate by applying energy to the silicon exfoliation layer; and (h) removing the first single crystal silicon epitaxial layer while reducing the thickness in one direction from the other surface thereof.

Description

SOI 기판 제조 방법SOI substrate manufacturing method
본 발명은 SOI 기판 제조 방법에 관한 것이다. 보다 상세하게는, 표면 균일도가 우수하고, 제조 공정을 단순하여 생산성을 향상시킬 수 있는 SOI 기판 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing an SOI substrate. More specifically, it relates to a method for manufacturing an SOI substrate capable of improving productivity by having excellent surface uniformity and simplifying the manufacturing process.
반도체 소자의 고집적화 및 고성능화가 진행됨에 따라, 벌크 실리콘으로 이루어진 실리콘 웨이퍼를 대신하여 SOI(Silicon On Insulator) 웨이퍼를 이용한 반도체 집적 기술이 주목되고 있다. 이러한 SOI 기판 웨이퍼 상에 형성된 반도체 소자는 완전한 소자 분리와 기생 용량의 감소로 인하여, 고속 동작이 가능한 장점을 갖는다.BACKGROUND ART As semiconductor devices are highly integrated and high-performance advanced, a semiconductor integration technology using a silicon on insulator (SOI) wafer instead of a silicon wafer made of bulk silicon has been attracting attention. The semiconductor device formed on the SOI substrate wafer has the advantage of enabling high-speed operation due to complete device isolation and reduction in parasitic capacitance.
종래에는, SOI 웨이퍼를 제조하기 위한 방법으로서, SIMOX(Seperation by Implanted Oxygen)법, Smart Cut 등의 방법이 있다. SIMOX는 산소 이온주입을 이용하고, 실리콘 층의 결정성 복구를 위해 고온 열처리를 수행하며, 실리콘 층과 매몰 산화막의 두께가 얇게 형성되므로 thin-SOI 기판의 제조에 유리한 것으로 평가되는 반면, 제조 시간이 길게 되는 단점이 있다. Smart Cut은 실리콘 웨이퍼 위에 열 산화막을 성장시킨 후, 산화막을 통과하도록 수소 이온을 주입하여 분리될 층을 형성하며, 다른 실리콘 웨이퍼의 접합 후 이온 주입 부분을 경계로 하여 실리콘 기판을 분리하여 SOI 웨이퍼를 제조한다. 이 방법은 제조 공정은 단순한 편이나, 이온 주입 부분의 경계의 표면 균일도가 우수하지 않은 단점이 있다.Conventionally, as a method for manufacturing an SOI wafer, there are methods such as SIMOX (Seperation by Implanted Oxygen) method and Smart Cut. SIMOX uses oxygen ion implantation, performs high-temperature heat treatment to recover the crystallinity of the silicon layer, and is evaluated to be advantageous for the manufacture of thin-SOI substrates because the silicon layer and buried oxide layer are formed to be thin. There is a shortcoming of lengthening. Smart Cut forms a layer to be separated by growing a thermal oxide film on a silicon wafer, and implanting hydrogen ions to pass through the oxide film. To manufacture. This method has a simple manufacturing process, but has a disadvantage in that the surface uniformity of the boundary of the ion implanted portion is not excellent.
따라서, 제조 공정을 단순화 하면서도 표면 균일도가 우수한 SOI 기판의 제조 방법이 필요한 실정이다. Accordingly, there is a need for a method of manufacturing an SOI substrate having excellent surface uniformity while simplifying the manufacturing process.
한편, 도 1은 종래의 SOI 제조 프로세스를 나타내는 개념도이다. 종래의 SOI 웨이퍼들은 전면에 SOI가 형성된 상태에서, 포토레지스트/식각 공정 등을 통해 액티브(active) SOI 영역을 형성하는 것이 일반적이다. 이에, 액티브 SOI를 형성하기 위한 별도의 공정이 필요하므로, 생산성이 낮아지고, 액티브 SOI 영역을 형성하는 과정에서 SOI의 품질이 저하되는 문제점이 있었다.Meanwhile, FIG. 1 is a conceptual diagram showing a conventional SOI manufacturing process. Conventional SOI wafers generally form an active SOI region through a photoresist/etch process while SOI is formed on the entire surface. Accordingly, since a separate process for forming the active SOI is required, productivity is lowered, and there is a problem in that the quality of the SOI is deteriorated in the process of forming the active SOI region.
따라서, 본 발명은 상기와 같은 종래 기술의 제반 문제점을 해결하기 위하여 안출된 것으로서, 처음부터 액티브 영역에만 SOI 층을 형성할 수 있는 SOI 기판의 제조 방법을 제공하는 것을 그 목적으로 한다.Accordingly, the present invention has been devised to solve the problems of the prior art as described above, and an object of the present invention is to provide a method of manufacturing an SOI substrate capable of forming an SOI layer only in an active region from the beginning.
또한, 본 발명은 제조 공정을 단순화하여 공정 시간, 원가를 절감하고 생산성을 향상시킬 수 있는 SOI 기판의 제조 방법을 제공하는 것을 그 목적으로 한다.In addition, an object of the present invention is to provide a method of manufacturing an SOI substrate capable of simplifying the manufacturing process, reducing process time and cost, and improving productivity.
그러나 이러한 과제는 예시적인 것으로, 이에 의해 본 발명의 범위가 한정되는 것은 아니다.However, these problems are exemplary, and the scope of the present invention is not limited thereby.
본 발명의 상기의 목적은, (a) 제1 단결정 실리콘 기판의 일면 상에 실리콘 박리층을 형성하는 단계; (b) 실리콘 박리층 상에 제1 단결정 실리콘 에피택셜층을 형성하는 단계; (c) 제1 단결정 실리콘 에피택셜층의 일면 상에 복수의 절연 패턴을 형성하는 단계; (d) 제1 단결정 실리콘 에피택셜층 및 절연 패턴 상에 제2 단결정 실리콘 에피택셜층을 형성하는 단계; (e) 제2 단결정 실리콘 에피택셜층을 평탄화하는 단계; (f) 제1 단결정 실리콘 기판 및 표면 상에 산화층이 형성된 제2 단결정 실리콘 기판을 접합하는 단계; (g) 실리콘 박리층에 에너지를 인가하여 제1 단결정 실리콘 기판을 분리 제거하는 단계; (h) 제1 단결정 실리콘 에피택셜층의 타면으로부터 일면 방향으로 두께를 감축하면서 제거하는 단계를 포함하는, SOI 기판 제조 방법에 의해 달성된다.The above object of the present invention is, (a) forming a silicon release layer on one surface of the first single crystal silicon substrate; (b) forming a first single crystal silicon epitaxial layer on the silicon exfoliation layer; (c) forming a plurality of insulating patterns on one surface of the first single crystal silicon epitaxial layer; (d) forming a second single crystal silicon epitaxial layer on the first single crystal silicon epitaxial layer and the insulating pattern; (e) planarizing the second single crystal silicon epitaxial layer; (f) bonding a first single crystal silicon substrate and a second single crystal silicon substrate having an oxide layer formed thereon; (g) applying energy to the silicon exfoliation layer to separate and remove the first single crystal silicon substrate; (h) removing the first single crystal silicon epitaxial layer while reducing its thickness in one surface direction from the other surface of the first single crystal silicon epitaxial layer.
본 발명의 일 실시예에 따르면, (a) 단계와 (b) 단계 사이에, (1) 실리콘 박리층의 공극(pore) 및 표면 상을 산화 처리하는 단계; (2) 실리콘 박리층의 표면 상의 산화물을 제거하는 단계; (3) 실리콘 박리층의 표면을 재결정화하는 단계를 더 포함할 수 있다.According to an embodiment of the present invention, between steps (a) and (b), (1) oxidizing the pores and the surface of the silicon release layer; (2) removing oxides on the surface of the silicon release layer; (3) The step of recrystallizing the surface of the silicon release layer may be further included.
본 발명의 일 실시예에 따르면, (e) 단계에서, 절연 패턴이 형성된 부분까지 제2 단결정 실리콘 에피택셜층의 두께를 감축하며 평탄화 할 수 있다.According to an embodiment of the present invention, in step (e), the thickness of the second single crystal silicon epitaxial layer may be reduced and planarized up to the portion where the insulating pattern is formed.
본 발명의 일 실시예에 따르면, 절연 패턴은 산화 실리콘, 질화 실리콘 중 적어도 어느 하나의 재질일 수 있다.According to an embodiment of the present invention, the insulating pattern may be made of at least one of silicon oxide and silicon nitride.
본 발명의 일 실시예에 따르면, (e) 단계의 평탄화는 H 2 어닐링, Ar 어닐링 또는 CMP 방법으로 수행할 수 있다.According to an embodiment of the present invention, the planarization in step (e) may be performed by H 2 annealing, Ar annealing, or CMP method.
본 발명의 일 실시예에 따르면, (g) 단계는, 워터젯(water-jet) 방법 또는 기계적 충격(mechanical shock, mechanical lift) 방법으로 에너지를 인가하여 실리콘 박리층을 절단하고, 제1 단결정 실리콘 기판을 분리 제거하는 단계일 수 있다.According to an embodiment of the present invention, in step (g), the silicon release layer is cut by applying energy by a water-jet method or a mechanical shock, mechanical lift method, and a first single crystal silicon substrate It may be a step of separating and removing them.
본 발명의 일 실시예에 따르면, (h) 단계에서, 절연 패턴이 형성된 부분까지 두께를 감축할 수 있다.According to an embodiment of the present invention, in step (h), the thickness may be reduced to the portion where the insulating pattern is formed.
본 발명의 일 실시예에 따르면, 절연 패턴이 두께 감축의 스톱퍼(stopper)로 기능할 수 있다.According to an embodiment of the present invention, the insulating pattern may function as a stopper for reducing the thickness.
본 발명의 일 실시예에 따르면, (e) 단계와 (f) 단계 사이에, (e2) 적어도 제2 단결정 실리콘 에피택셜층의 상부에 디싱 산화층을 형성하는 단계;를 더 포함할 수 있다.According to an embodiment of the present invention, between steps (e) and (f), (e2) forming a dishing oxide layer on at least the second single crystal silicon epitaxial layer; may be further included.
본 발명의 일 실시예에 따르면, (e2) 단계에서, 디싱 산화층은 절연 패턴의 높이보다 낮은 높이까지 평탄화된 제2 단결정 실리콘 에피택셜층의 홈부에 형성할 수 있다.According to an embodiment of the present invention, in step (e2), the dishing oxide layer may be formed in the groove portion of the second single crystal silicon epitaxial layer planarized to a height lower than the height of the insulating pattern.
(e2) 단계에서, 디싱 산화층은 절연 패턴의 높이보다 낮은 높이까지 평탄화된 제2 단결정 실리콘 에피택셜층의 홈부 및 절연 패턴 상부에 형성할 수 있다.In step (e2), the dishing oxide layer may be formed on the groove portion and the insulating pattern of the second single crystal silicon epitaxial layer planarized to a height lower than the height of the insulating pattern.
(e2) 단계와 (f) 단계 사이에, 디싱 산화층의 두께를 감축하며 평탄화하는 단계를 더 포함할 수 있다.Between (e2) and (f), the step of flattening and reducing the thickness of the dishing oxide layer may be further included.
상기와 같이 구성된 본 발명에 따르면, 처음부터 액티브 영역에만 SOI 층을 형성할 수 있는 효과가 있다.According to the present invention configured as described above, there is an effect of forming an SOI layer only in the active region from the beginning.
또한, 본 발명은 제조 공정을 단순화하여 공정 시간, 원가를 절감하고 생산성을 향상시킬 수 있는 효과가 있다.In addition, the present invention has the effect of simplifying the manufacturing process, reducing process time and cost, and improving productivity.
물론 이러한 효과에 의해 본 발명의 범위가 한정되는 것은 아니다.Of course, the scope of the present invention is not limited by these effects.
도 1은 종래의 SOI process를 나타내는 개념도이다.1 is a conceptual diagram illustrating a conventional SOI process.
도 2 내지 도 9는 본 발명의 일 실시예에 따른 SOI 기판의 제조 과정을 나타내는 개략도이다.2 to 9 are schematic diagrams showing a manufacturing process of an SOI substrate according to an embodiment of the present invention.
도 10 내지 도 15는 본 발명의 다른 실시예에 따른 SOI 기판의 제조 과정을 나타내는 개략도이다.10 to 15 are schematic diagrams showing a manufacturing process of an SOI substrate according to another embodiment of the present invention.
<부호의 설명><Explanation of code>
100: SOI 기판100: SOI substrate
110: 제1 단결정 실리콘 기판110: first single crystal silicon substrate
120: 실리콘 박리층120: silicone release layer
130: 제1 단결정 실리콘 에피택셜층130: first single crystal silicon epitaxial layer
140: 절연 패턴140: insulation pattern
150: 제2 단결정 실리콘 에피택셜층150: second single crystal silicon epitaxial layer
160, 220, 230: 산화층160, 220, 230: oxide layer
210: 제2 단결정 실리콘 기판210: second single crystal silicon substrate
후술하는 본 발명에 대한 상세한 설명은, 본 발명이 실시될 수 있는 특정 실시예를 예시로서 도시하는 첨부 도면을 참조한다. 이들 실시예는 당업자가 본 발명을 실시할 수 있기에 충분하도록 상세히 설명된다. 본 발명의 다양한 실시예는 서로 다르지만 상호 배타적일 필요는 없음이 이해되어야 한다. 예를 들어, 여기에 기재되어 있는 특정 형상, 구조 및 특성은 일 실시예에 관련하여 본 발명의 정신 및 범위를 벗어나지 않으면서 다른 실시예로 구현될 수 있다. 또한, 각각의 개시된 실시예 내의 개별 구성요소의 위치 또는 배치는 본 발명의 정신 및 범위를 벗어나지 않으면서 변경될 수 있음이 이해되어야 한다. 따라서, 후술하는 상세한 설명은 한정적인 의미로서 취하려는 것이 아니며, 본 발명의 범위는, 적절하게 설명된다면, 그 청구항들이 주장하는 것과 균등한 모든 범위와 더불어 첨부된 청구항에 의해서만 한정된다. 도면에서 유사한 참조부호는 여러 측면에 걸쳐서 동일하거나 유사한 기능을 지칭하며, 길이 및 면적, 두께 등과 그 형태는 편의를 위하여 과장되어 표현될 수도 있다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The detailed description of the present invention described below refers to the accompanying drawings, which illustrate specific embodiments in which the present invention may be practiced. These embodiments are described in detail sufficient to enable a person skilled in the art to practice the present invention. It should be understood that the various embodiments of the present invention are different from each other, but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention in relation to one embodiment. In addition, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present invention. Accordingly, the detailed description to be described below is not intended to be taken in a limiting sense, and the scope of the present invention, if appropriately described, is limited only by the appended claims, along with all ranges equivalent to those claimed by the claims. In the drawings, similar reference numerals refer to the same or similar functions over various aspects, and the length, area, thickness, and the like may be exaggerated and expressed for convenience.
이하에서는, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있도록 하기 위하여, 본 발명의 바람직한 실시예들에 관하여 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to enable those of ordinary skill in the art to easily implement the present invention.
도 2 내지 도 9는 본 발명의 일 실시예에 따른 SOI 기판(100)의 제조 과정을 나타내는 개략도이다. 도 2 내지 도 9는 SOI 기판의 일부분에 대한 측단면도를 나타내지만, 실제 SOI 기판(100)은 이보다 큰 스케일일 수 있으며, 절연 패턴(140)은 평면상에서 가로, 세로 방향으로 더 많은 수의 복수 패턴이 이격되어 형성될 수 있음을 밝혀둔다. 2 to 9 are schematic diagrams showing a manufacturing process of the SOI substrate 100 according to an embodiment of the present invention. 2 to 9 show side cross-sectional views of a portion of the SOI substrate, but the actual SOI substrate 100 may have a larger scale, and the insulating pattern 140 may have a larger number of plural numbers in the horizontal and vertical directions on the plane. It should be noted that the pattern can be formed apart from each other.
본 발명의 일 실시예에 따른SOI 기판(100)의 제조 방법은, (a) 제1 단결정 실리콘 기판(110)의 일면 상에 실리콘 박리층(120)을 형성하는 단계, (b) 실리콘 박리층(120) 상에 제1 단결정 실리콘 에피택셜층(130)을 형성하는 단계, (c) 제1 단결정 실리콘 에피택셜층(130)의 일면 상에 복수의 절연 패턴(140)을 형성하는 단계, (d) 제1 단결정 실리콘 에피택셜층(130) 및 절연 패턴(140) 상에 제2 단결정 실리콘 에피택셜층(150')을 형성하는 단계, (e) 제2 단결정 실리콘 에피택셜층(150')을 평탄화(P)하는 단계, (f) 제1 단결정 실리콘 기판(110) 및 표면 상에 산화층(220)이 형성된 제2 단결정 실리콘 기판(210)을 접합하는 단계; (g) 실리콘 박리층(120)에 에너지를 인가(S)하여 제1 단결정 실리콘 기판(110)을 분리 제거하는 단계, (h) 제1 단결정 실리콘 에피택셜층(130)의 타면으로부터 일면 방향으로 두께를 감축하면서 제거하는 단계를 포함하는 것을 특징으로 한다. 그리하여, 별도의 공정없이 액티브 SOI 영역이 형성된 SOI 기판(100)을 제조할 수 있다. The method of manufacturing the SOI substrate 100 according to an embodiment of the present invention includes the steps of: (a) forming a silicon release layer 120 on one surface of the first single crystal silicon substrate 110, (b) a silicon release layer Forming a first single crystal silicon epitaxial layer 130 on 120, (c) forming a plurality of insulating patterns 140 on one surface of the first single crystal silicon epitaxial layer 130, ( d) forming a second single crystal silicon epitaxial layer 150' on the first single crystal silicon epitaxial layer 130 and the insulating pattern 140, (e) the second single crystal silicon epitaxial layer 150' (F) bonding the first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 having the oxide layer 220 formed thereon; (g) applying energy (S) to the silicon peeling layer 120 to separate and remove the first single crystal silicon substrate 110, (h) from the other surface of the first single crystal silicon epitaxial layer 130 to one surface direction It characterized in that it comprises the step of removing while reducing the thickness. Thus, the SOI substrate 100 in which the active SOI region is formed can be manufactured without a separate process.
먼저, 도 2를 참조하면, 제1 단결정 실리콘 기판(110)을 준비할 수 있다. 제1 단결정 실리콘 기판(110)은 단결정 실리콘 웨이퍼(wafer)를 사용할 수도 있고, 사각형 등의 단결정 실리콘 기판을 사용할 수도 있다.First, referring to FIG. 2, a first single crystal silicon substrate 110 may be prepared. The first single crystal silicon substrate 110 may be a single crystal silicon wafer, or a single crystal silicon substrate such as a square may be used.
이어서, 제1 단결정 실리콘 기판(110)의 일면(예를 들어, 상부면) 상에 실리콘 박리층(120)[다공질 실리콘층(porous silicon)]을 형성할 수 있다. 양극 반응(anodizing) 등의 공지의 방법을 사용하여 제1 단결정 실리콘 기판(110) 상에 실리콘 박리층(120)을 형성할 수 있다.Subsequently, a silicon exfoliation layer 120 (porous silicon) may be formed on one surface (eg, an upper surface) of the first single crystal silicon substrate 110. The silicon release layer 120 may be formed on the first single crystal silicon substrate 110 by using a known method such as anodizing.
이어서, 실리콘 박리층(120) 상에 제1 단결정 실리콘 에피택셜층(130)을 형성할 수 있다. 제1 단결정 실리콘 에피택셜층(130)은 공지의 에피택셜 방법을 사용하여 형성할 수 있다. 실리콘 박리층(120)의 일면(예를 들어, 상부면)으로부터 제1 단결정 실리콘 에피택셜층(130)이 형성될 수 있다. 일 실시예에 따르면, 제1 단결정 실리콘 에피택셜층(130)은 약 0.5~1 ㎛의 두께로 형성될 수 있다.Subsequently, a first single crystal silicon epitaxial layer 130 may be formed on the silicon exfoliation layer 120. The first single crystal silicon epitaxial layer 130 may be formed using a known epitaxial method. A first single crystal silicon epitaxial layer 130 may be formed from one surface (eg, an upper surface) of the silicon exfoliation layer 120. According to an embodiment, the first single crystal silicon epitaxial layer 130 may be formed to a thickness of about 0.5 to 1 μm.
한편, 실리콘 박리층(120) 상에 제1 단결정 실리콘 에피택셜층(130)을 형성하기 전에, 실리콘 박리층(120) 상부 표면의 공극(pore)을 막는 공정을 더 수행할 수 있다. 먼저, 실리콘 박리층(120)에 산화를 수행하여 공극 및 표면 상에 산화층(미도시)을 형성하고 HF 등으로 표면 부분에 형성된 산화층을 제거할 수 있다. 이어서, 약 1,000℃ 이상에서 수소 열처리를 수행하여 실리콘 박리층(120) 상부 표면 공극 부분의 재결정화를 수행할 수 있다. 이에 따라, 실리콘 박리층(120) 상부 표면 상에서 제1 단결정 실리콘 에피택셜층(130)을 형성할 때 결함없이 더 얇은 두께로 형성하기 용이해지는 이점이 있다.Meanwhile, before forming the first single crystal silicon epitaxial layer 130 on the silicon peeling layer 120, a process of blocking pores on the upper surface of the silicon peeling layer 120 may be further performed. First, oxidation is performed on the silicon peeling layer 120 to form an oxide layer (not shown) on the voids and the surface, and the oxide layer formed on the surface portion with HF or the like may be removed. Subsequently, hydrogen heat treatment may be performed at about 1,000° C. or higher to perform recrystallization of the upper surface voids of the silicon release layer 120. Accordingly, when forming the first single crystal silicon epitaxial layer 130 on the upper surface of the silicon exfoliation layer 120, there is an advantage that it is easy to form a thinner thickness without defects.
다음으로, 도 3을 참조하면, 제1 단결정 실리콘 에피택셜층(130)의 일면(예를 들어, 상부면) 상에 복수의 절연 패턴(140)을 형성할 수 있다. 절연 패턴(140)은 실리콘 산화물(silicon oxide) 재질인 것이 바람직하나, 이에 제한되는 것은 아니며 실리콘 질화물 재질을 사용할 수도 있다. 절연 패턴(140)은 증착, 프린팅 등 공지의 박막 형성 방법을 제한없이 사용하여 형성할 수 있다.Next, referring to FIG. 3, a plurality of insulating patterns 140 may be formed on one surface (eg, an upper surface) of the first single crystal silicon epitaxial layer 130. The insulating pattern 140 is preferably made of a silicon oxide material, but is not limited thereto, and a silicon nitride material may be used. The insulating pattern 140 may be formed using a known thin film forming method such as deposition or printing without limitation.
복수의 절연 패턴(140)은 상호 간격을 이루어 형성될 수 있다. 후술할 제1, 2 단결정 실리콘 에피택셜층(130, 150)에 대한 두께 감축의 스톱퍼(stopper) 역할을 하는 목적의 범위 및 액티브 SOI 영역들을 분리해내는 목적의 범위라면, 제1 단결정 실리콘 에피택셜층(130)의 일면 상에서 일 방향으로 평행하게 형성되거나, 교차되도록 형성되는 등, 복수의 절연 패턴(140)이 형성되는 형태에 대해서는 제한이 없다. 일 실시예에 따르면, 절연 패턴(140)은 제1 단결정 실리콘 에피택셜층(130) 상에 약 30nm의 두께, 약 5~10㎛의 폭을 가지고 형성될 수 있다.The plurality of insulating patterns 140 may be formed to be spaced apart from each other. If the target range serves as a stopper for reducing the thickness of the first and second single crystal silicon epitaxial layers 130 and 150 to be described later and the range for separating the active SOI regions, the first single crystal silicon epitaxial layer There is no limitation on the form in which the plurality of insulating patterns 140 are formed, such as formed parallel to or intersecting in one direction on one surface of the seam layer 130. According to an embodiment, the insulating pattern 140 may be formed on the first single crystal silicon epitaxial layer 130 to have a thickness of about 30 nm and a width of about 5 to 10 μm.
다음으로, 도 4를 참조하면, 제1 단결정 실리콘 에피택셜층(130) 및 절연 패턴(140) 상에 제2 단결정 실리콘 에피택셜층(150')을 형성할 수 있다. 제2 단결정 실리콘 에피택셜층(150')은 공지의 에피택셜 방법을 사용하여 형성할 수 있다. 제1 단결정 실리콘 에피택셜층(130)의 노출된 면으로부터 제2 단결정 실리콘 에피택셜층(150')이 형성될 수 있다. 일 실시예에 따르면, 제2 단결정 실리콘 에피택셜층(150')은 약 10~50 nm 의 두께로 형성될 수 있다.Next, referring to FIG. 4, a second single crystal silicon epitaxial layer 150 ′ may be formed on the first single crystal silicon epitaxial layer 130 and the insulating pattern 140. The second single crystal silicon epitaxial layer 150 ′ may be formed using a known epitaxial method. A second single crystal silicon epitaxial layer 150 ′ may be formed from the exposed surface of the first single crystal silicon epitaxial layer 130. According to an embodiment, the second single crystal silicon epitaxial layer 150 ′ may be formed to a thickness of about 10 to 50 nm.
다음으로, 제2 단결정 실리콘 에피택셜층(150')을 평탄화(P) 할 수 있다. 여기서 평탄화(P)는 제2 단결정 실리콘 에피택셜층(150')의 일면(상면)을 경면화 하면서 동시에 제2 단결정 실리콘 에피택셜층(150')의 상부를 일부 제거하여 두께를 얇게 감축(150' -> 150)시키는 것을 의미한다. 평탄화(P)는 CMP(Chemical Mechanical Polishing), 수소 열처리(H 2 anneal), 아르곤 열처리(Ar anneal)를 통해 수행하는 것이 바람직하나, 이에 제한되지 않는다.Next, the second single crystal silicon epitaxial layer 150 ′ may be planarized (P). In the planarization (P), one surface (upper surface) of the second single crystal silicon epitaxial layer 150 ′ is mirror-finished and at the same time, a portion of the upper portion of the second single crystal silicon epitaxial layer 150 ′ is partially removed to reduce the thickness to be thin (150). '-> 150). The planarization (P) is preferably performed through Chemical Mechanical Polishing (CMP), hydrogen heat treatment (H 2 anneal), and argon heat treatment (Ar anneal), but is not limited thereto.
도 5를 참조하면, 제2 단결정 실리콘 에피택셜층(150')이 평탄화(P)되어 두께 편차가 줄어듦과 동시에 두께가 얇게 감축(150' -> 150)될 수 있다. 평탄화(P)는 적어도 절연 패턴(140)을 제거할 정도까지는 수행되지 않고, 절연 패턴(140)이 스톱퍼(stopper)로 기능하여 절연 패턴(140)의 높이까지 수행될 수 있다. 일 실시예에 따르면, 1,100 ~ 1,150℃의 수소 열처리, 1,200℃의 아르곤 열처리 또는 CMP를 통해, 제2 단결정 실리콘 에피택셜층(150)이 약 30 nm 정도의 두께를 가질 수 있다.Referring to FIG. 5, since the second single crystal silicon epitaxial layer 150 ′ is planarized (P), a thickness variation may be reduced and a thickness may be reduced (150 ′ -> 150 ′) to be thin. The planarization (P) is not performed at least to the extent that the insulating pattern 140 is removed, and the insulating pattern 140 functions as a stopper and may be performed up to the height of the insulating pattern 140. According to an embodiment, the second single crystal silicon epitaxial layer 150 may have a thickness of about 30 nm through hydrogen heat treatment at 1,100 to 1,150°C, argon heat treatment at 1,200°C, or CMP.
다음으로, 도 6을 참조하면, 제2 단결정 실리콘 기판(210)을 준비할 수 있다. 제2 단결정 실리콘 기판(210)은 제1 단결정 실리콘 기판(110)과 같은 단결정 실리콘 웨이퍼(wafer)를 사용할 수도 있고, 사각형 등의 단결정 실리콘 기판을 사용할 수도 있다. 또한, 제2 단결정 실리콘 기판(210)은 제1 단결정 실리콘 기판(110)과 동일한 크기, 형태를 가지는 것이 바람직하나, 이에 제한되지 않는다.Next, referring to FIG. 6, a second single crystal silicon substrate 210 may be prepared. As the second single crystal silicon substrate 210, a single crystal silicon wafer such as the first single crystal silicon substrate 110 may be used, or a single crystal silicon substrate such as a square may be used. Further, the second single crystal silicon substrate 210 preferably has the same size and shape as the first single crystal silicon substrate 110, but is not limited thereto.
한편, 제2 단결정 실리콘 기판(210)은 복수의 제1 단결정 실리콘 기판(110)의 면적을 합한 것과 대응하는 면적을 가질 수도 있다. 이 경우, 제2 단결정 실리콘 기판(210)에 도 5의 실리콘 박리층(120), 제1 단결정 실리콘 에피택셜층(130), 절연 패턴(140), 제1 단결정 실리콘 에피택셜층(150) 및 산화층(160)이 형성된 제1 단결정 실리콘 기판(110)을 일정 간격을 두고 복수개 접합하여 후속 공정을 진행할 수도 있다.Meanwhile, the second single crystal silicon substrate 210 may have an area corresponding to the sum of the areas of the plurality of first single crystal silicon substrates 110. In this case, the silicon peeling layer 120 of FIG. 5, the first single crystal silicon epitaxial layer 130, the insulating pattern 140, the first single crystal silicon epitaxial layer 150, and A subsequent process may be performed by bonding a plurality of first single crystal silicon substrates 110 on which the oxide layer 160 is formed at predetermined intervals.
제2 단결정 실리콘 기판(210)은 표면 상에 산화층(220)이 형성된 것이 바람직하다. 산화층(220)은 공지의 박막 형성 방법을 통해 제2 단결정 실리콘 기판(210)의 표면 상에 형성될 수 있다. 일 실시예에 따르면, 산화층(220)은 약 10nm ~ 20nm의 두께로 형성될 수 있다. It is preferable that the oxide layer 220 is formed on the surface of the second single crystal silicon substrate 210. The oxide layer 220 may be formed on the surface of the second single crystal silicon substrate 210 through a known thin film formation method. According to an embodiment, the oxide layer 220 may be formed to a thickness of about 10 nm to 20 nm.
다음으로, 제1 단결정 실리콘 기판(110)과 제2 단결정 실리콘 기판(210)을 접합(bonding)할 수 있다. 제1 단결정 실리콘 기판(110)과 제2 단결정 실리콘 기판(210)의 표면이 상호 접합되는 것은 아니며, 제1, 2 단결정 실리콘 에피택셜층(130, 150) 및 산화층(160, 220)을 매개하여 접합될 수 있다. 진공, 불활성 가스 등의 환경 하에서 수백~ ℃의 온도로 열처리를 통해 접합을 수행할 수 있다. 산화층(160)과 산화층(220)의 재질이 동일하므로 계면에서 접합이 보다 잘 수행될 수 있다. 또한, 접합이 완료된 후에 산화층(230: 160, 220)[도 7 참조]은 SOI 기판(100)에서 절연체(insulator)로서 작용할 수 있다.Next, the first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 may be bonded. The surfaces of the first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 are not bonded to each other, and the first and second single crystal silicon epitaxial layers 130 and 150 and the oxide layers 160 and 220 are interposed. Can be joined. Bonding may be performed through heat treatment at a temperature of several hundreds to ℃ under an environment such as vacuum or inert gas. Since the material of the oxide layer 160 and the oxide layer 220 is the same, bonding may be better performed at the interface. In addition, after the bonding is completed, the oxide layers 230 (160, 220) (see FIG. 7) may act as an insulator in the SOI substrate 100.
다음으로, 도 7을 참조하면, 실리콘 박리층(120)에 에너지를 인가(S)하여 제1 단결정 실리콘 기판(110)을 분리제거할 수 있다. 에너지의 인가(S)는 워터젯(water-jet) 방법으로 수행될 수 있다. 또는, 에너지의 인가(S)는 진동, 충격 등을 인가하는 기계적 충격(mechanical shock, mechanical lift) 방법으로 수행될 수 있다. 실리콘 박리층(120)은 다공성(porous) 특성 때문에 측면에서 에너지가 인가(S)되면 쉽게 절단될 수 있다. 실리콘 박리층(120)이 절단되면서 제1 단결정 실리콘 기판(110)이 분리될 수 있다. 본 발명은 제1 단결정 실리콘 기판(110)의 일면에 잔류한 다공질 실리콘을 세정제거함으로써 재사용이 가능한 이점이 있다.Next, referring to FIG. 7, the first single crystal silicon substrate 110 may be separated and removed by applying (S) energy to the silicon peeling layer 120. The application of energy (S) may be performed by a water-jet method. Alternatively, the application of energy (S) may be performed by a mechanical shock (mechanical lift) method of applying vibration, shock, or the like. The silicon peeling layer 120 can be easily cut when energy is applied (S) from the side because of its porous property. As the silicon exfoliation layer 120 is cut, the first single crystal silicon substrate 110 may be separated. The present invention has the advantage of reusability by cleaning and removing porous silicon remaining on one surface of the first single crystal silicon substrate 110.
다음으로, 도 8을 참조하면, 제1 단결정 실리콘 에피택셜층(130)의 타면으로부터 일면 방향으로 두께를 감축하면서 제거(G)할 수 있다. 제1 단결정 실리콘 에피택셜층(130)의 일면은 절연 패턴(140) 및 제2 단결정 실리콘 에피택셜층(150)이 형성된 면이고, 타면은 실리콘 박리층(120)이 절단되어 실리콘 박리층(120')이 잔류하는 면에 대응한다. 즉, 제1 단결정 실리콘 기판(110)이 분리된 후에, 잔존하는 실리콘 박리층(120') 및 제1 단결정 실리콘 에피택셜층(130)을 제거함과 동시에 제2 단결정 실리콘 에피택셜층(150)의 타면(도 8에서 상면)을 평탄화(G)할 수 있다.Next, referring to FIG. 8, the first single crystal silicon epitaxial layer 130 may be removed (G) while reducing the thickness in one surface direction from the other surface. One surface of the first single crystal silicon epitaxial layer 130 is a surface on which the insulating pattern 140 and the second single crystal silicon epitaxial layer 150 are formed, and the other surface is a silicon release layer 120 by cutting the silicon release layer 120. ') corresponds to the remaining side. That is, after the first single crystal silicon substrate 110 is separated, the remaining silicon peeling layer 120 ′ and the first single crystal silicon epitaxial layer 130 are removed and the second single crystal silicon epitaxial layer 150 is removed. The other surface (the upper surface in FIG. 8) can be flattened (G).
제1 단결정 실리콘 에피택셜층(130)은 ㎛ 스케일의 두께를 가지므로, 도 4의 평탄화(P)보다는 빠르게 두께를 감축할 수 있는 방법을 사용할 필요가 있다. 이를 고려하여, 제1 단결정 실리콘 에피택셜층(130)의 두께 감축 및 제거(G)는 그라인딩(grinding), 폴리싱(polishing), 식각(etching) 등의 방법을 사용할 수 있다. 일 예로, ㎛ 단위의 두께까지는 1차로 러프하게 그라인딩을 수행한 후, ㎛에서 nm 수준의 두께까지는 2차로 CMP, 식각을 사용하여 미세하게 두께 감축을 컨트롤 할 수 있다.Since the first single crystal silicon epitaxial layer 130 has a thickness of µm scale, it is necessary to use a method capable of reducing the thickness faster than the planarization (P) of FIG. 4. In consideration of this, the thickness reduction and removal (G) of the first single crystal silicon epitaxial layer 130 may be performed using a method such as grinding, polishing, or etching. For example, after the first rough grinding is performed up to the thickness of the µm unit, the thickness reduction can be finely controlled by using CMP and etching in the second order from the µm to the thickness of the nm level.
두께 감축 및 제거(G)는 절연 패턴(140)이 형성된 부분까지 수행하는 것이 바람직하다. 즉, 절연 패턴(140)의 산화물, 질화물이 두께 감축의 스톱퍼(stopper) 역할을 할 수 있다.It is preferable to perform thickness reduction and removal (G) up to the portion where the insulating pattern 140 is formed. That is, oxides and nitrides of the insulating pattern 140 may serve as a stopper for reducing the thickness.
도 9를 참조하면, 두께 감축 및 제거(G) 후에 SOI 기판(100)의 제조를 완료할 수 있다. 절연 패턴(140)은 제2 단결정 실리콘 에피택셜층(150)을 구획하고, 구획된 제2 단결정 실리콘 에피택셜층(150)의 각 영역들은 액티브 SOI(active SOI)로 사용될 수 있다. 이후에, 반도체, 메모리 형성 공정을 더 수행할 수 있다.Referring to FIG. 9, manufacturing of the SOI substrate 100 may be completed after thickness reduction and removal (G). The insulating pattern 140 partitions the second single crystal silicon epitaxial layer 150, and regions of the partitioned second single crystal silicon epitaxial layer 150 may be used as an active SOI (active SOI). Thereafter, a process of forming a semiconductor or a memory may be further performed.
도 10 내지 도 15는 본 발명의 다른 실시예에 따른 SOI 기판의 제조 과정을 나타내는 개략도이다.10 to 15 are schematic diagrams showing a manufacturing process of an SOI substrate according to another embodiment of the present invention.
본 발명의 다른 실시예에 따른 SOI 기판 제조 방법은, (a) 제1 단결정 실리콘 기판(110)의 일면 상에 실리콘 박리층(120)을 형성하는 단계, (b) 실리콘 박리층(120) 상에 제1 단결정 실리콘 에피택셜층(130)을 형성하는 단계, (c) 제1 단결정 실리콘 에피택셜층(130)의 일면 상에 복수의 절연 패턴(140)을 형성하는 단계, (d) 제1 단결정 실리콘 에피택셜층(130) 및 절연 패턴(140) 상에 제2 단결정 실리콘 에피택셜층(150')을 형성하는 단계, (e) 제2 단결정 실리콘 에피택셜층(150')의 일면을 평탄화(P)하는 단계, (f) 적어도 제2 단결정 실리콘 에피택셜층(150)의 상부(V)에 산화층(160)을 형성하는 단계, (g) 제1 단결정 실리콘 기판(110) 및 표면 상에 산화층(220)이 형성된 제2 단결정 실리콘 기판(210)을 접합하는 단계, (h) 실리콘 박리층(120)에 에너지를 인가(S)하여 제1 단결정 실리콘 기판(110)을 분리 제거하는 단계, (i) 제1 단결정 실리콘 에피택셜층(150)의 타면으로부터 일면 방향으로 두께를 감축하면서 제거(G)하는 단계를 포함하는 것을 특징으로 한다. 그리하여, 별도의 공정없이 액티브 SOI 영역이 형성된 SOI 기판을 제조하는 방법을 제공할 수 있다.A method of manufacturing an SOI substrate according to another embodiment of the present invention includes (a) forming a silicon release layer 120 on one surface of the first single crystal silicon substrate 110, (b) on the silicon release layer 120 Forming a first single crystal silicon epitaxial layer 130 on the surface, (c) forming a plurality of insulating patterns 140 on one surface of the first single crystal silicon epitaxial layer 130, (d) a first Forming a second single crystal silicon epitaxial layer 150' on the single crystal silicon epitaxial layer 130 and the insulating pattern 140, (e) planarizing one surface of the second single crystal silicon epitaxial layer 150' (P), (f) forming an oxide layer 160 on at least an upper portion (V) of the second single crystal silicon epitaxial layer 150, (g) on the first single crystal silicon substrate 110 and the surface Bonding the second single crystal silicon substrate 210 on which the oxide layer 220 is formed, (h) applying energy to the silicon release layer 120 (S) to separate and remove the first single crystal silicon substrate 110, and (i) removing (G) the thickness from the other surface of the first single crystal silicon epitaxial layer 150 while reducing the thickness in one surface direction. Thus, it is possible to provide a method of manufacturing an SOI substrate in which an active SOI region is formed without a separate process.
상기 (a) 단계 내지 (e) 단계는 도 2 내지 도 5와 같으므로 구체적인 설명을 생략한다. 하지만, 도 5처럼 제2 단결정 실리콘 에피택셜층(150)이 정확하게 절연 패턴(140)의 높이와 동일한 수준으로 감축되도록 평탄화가 수행되지 않는 경우가 발생할 수 있다. 도 10에 도시된 바와 같이, 평탄화 공정 후에 제2 단결정 실리콘 에피택셜층(150)이 절연 패턴(140)과 동일 선상의 높이를 가지지 않고, 디싱(dishing)되어 더 움푹파이게 될 수 있다. 이 경우, 제2 단결정 실리콘 에피택셜층(150)의 상부에는 빈 공간(V)이 생기고, 상부면의 표면이 경면이 아니기 때문에, 도 6의 접합 공정에서처럼 제2 단결정 실리콘 기판(210)과의 접합이 잘 되지 않는 문제점이 발생할 수 있다.Steps (a) to (e) are the same as those of FIGS. 2 to 5, and thus detailed descriptions are omitted. However, as shown in FIG. 5, there may be a case in which planarization is not performed so that the second single crystal silicon epitaxial layer 150 is accurately reduced to the same level as the height of the insulating pattern 140. As shown in FIG. 10, after the planarization process, the second single crystal silicon epitaxial layer 150 does not have the same height as the insulating pattern 140 and may be dished to become more pitted. In this case, since an empty space V is formed on the second single crystal silicon epitaxial layer 150 and the surface of the upper surface is not a mirror surface, the second single crystal silicon substrate 210 and the second single crystal silicon substrate 210 are Problems of poor bonding may occur.
따라서, 본 발명은 제2 단결정 실리콘 에피택셜층(150)의 평탄화(P) 이후에 디싱 산화층(160)을 더 형성할 수 있다.Accordingly, according to the present invention, after planarization (P) of the second single crystal silicon epitaxial layer 150, the dishing oxide layer 160 may be further formed.
도 11의 (a)를 참조하면, 제2 단결정 실리콘 에피택셜층(150) 및 절연 패턴(140)의 상부에 디싱 산화층(160)을 형성할 수 있다. 또는, 도 11의 (b)를 참조하면, 적어도 제2 단결정 실리콘 에피택셜층(150)의 상부(V)에 디싱 산화층(160')을 형성할 수 있다. 디싱 산화층(160)은 열 산화(thermal oxidation), CVD 등 공지의 박막 형성 방법을 통해 형성할 수 있다. 일 실시예에 따르면, 도 11의 (a)는 CVD 방법을 통해 제2 단결정 실리콘 에피택셜층(150) 및 절연 패턴(140)의 상부에 디싱 산화층(160)을 형성한 것이고, 도 11의 (b)는 열 산화 방법을 통해 제2 단결정 실리콘 에피택셜층(150)의 상부에 디싱 산화층(160')을 형성한 것에 대응할 수 있다. 일 실시예에 따르면, 디싱 산화층(160, 160')은 약 10nm ~ 20nm의 두께로 형성될 수 있다.Referring to FIG. 11A, a dishing oxide layer 160 may be formed on the second single crystal silicon epitaxial layer 150 and the insulating pattern 140. Alternatively, referring to FIG. 11B, a dishing oxide layer 160 ′ may be formed on at least the upper portion V of the second single crystal silicon epitaxial layer 150. The dishing oxide layer 160 may be formed through a known thin film formation method such as thermal oxidation or CVD. According to an embodiment, (a) of FIG. 11 is a dishing oxide layer 160 formed on the second single crystal silicon epitaxial layer 150 and the insulating pattern 140 through a CVD method. b) may correspond to the formation of the dishing oxide layer 160 ′ on the second single crystal silicon epitaxial layer 150 through a thermal oxidation method. According to an embodiment, the dishing oxide layers 160 and 160 ′ may be formed to have a thickness of about 10 nm to 20 nm.
도 11의 (a)에서 디싱 산화층(160)은 제2 단결정 실리콘 에피택셜층(150)의 빈 공간(V)을 채움과 동시에 제2 단결정 실리콘 에피택셜층(150) 및 절연 패턴(140)의 상부에 평평하게 형성될 수 있다. 또는, 디싱 산화층(160)을 형성한 후에 CMP 공정 등을 더 수행하여 디싱 산화층(160)을 평평하게 할 수 있다. 도 11의 (b)에서 디싱 산화층(160')은 제2 단결정 실리콘 에피택셜층(150)의 빈 공간(V)을 채우면서 제2 단결정 실리콘 에피택셜층(150)의 상부에 평평하게 형성될 수 있다.In FIG. 11A, the dishing oxide layer 160 fills the empty space V of the second single crystal silicon epitaxial layer 150 and at the same time, the second single crystal silicon epitaxial layer 150 and the insulating pattern 140 are formed. It can be formed flat on the top. Alternatively, after the dishing oxide layer 160 is formed, the dishing oxide layer 160 may be flattened by further performing a CMP process or the like. In (b) of FIG. 11, the dishing oxide layer 160 ′ is formed flat on the second single crystal silicon epitaxial layer 150 while filling the empty space V of the second single crystal silicon epitaxial layer 150. I can.
다음으로, 도 12를 참조하면, 제2 단결정 실리콘 기판(210)을 준비할 수 있다. 이는 도 6과 동일하게 진행될 수 있다.Next, referring to FIG. 12, a second single crystal silicon substrate 210 may be prepared. This can be done in the same manner as in FIG. 6.
다음으로, 제1 단결정 실리콘 기판(110)과 제2 단결정 실리콘 기판(210)을 접합(bonding)할 수 있다. 제1 단결정 실리콘 기판(110)과 제2 단결정 실리콘 기판(210)의 표면이 상호 접합되는 것은 아니며, 제1, 2 단결정 실리콘 에피택셜층(130, 150) 및 디싱 산화층/산화층(160, 220)을 매개하여 접합될 수 있다. 진공, 불활성 가스 등의 환경 하에서 수백~ ℃의 온도로 열처리를 통해 접합을 수행할 수 있다. 디싱 산화층(160)과 산화층(220)의 재질이 동일하므로 계면에서 접합이 보다 잘 수행될 수 있다. 또한, 접합이 완료된 후에 산화층(230: 160, 220)[도 13 참조]은 SOI 기판(100)에서 절연체(insulator)로서 작용할 수 있다.Next, the first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 may be bonded. The surfaces of the first single crystal silicon substrate 110 and the second single crystal silicon substrate 210 are not bonded to each other, and the first and second single crystal silicon epitaxial layers 130 and 150 and the dishing oxide/ oxide layer 160 and 220 are It can be joined by means of. Bonding may be performed through heat treatment at a temperature of several hundreds to ℃ under an environment such as vacuum or inert gas. Since the material of the dishing oxide layer 160 and the oxide layer 220 is the same, bonding may be better performed at the interface. In addition, after the bonding is completed, the oxide layers 230 (160, 220) (see FIG. 13) may function as an insulator in the SOI substrate 100.
다음으로, 도 13을 참조하면, 실리콘 박리층(120)에 에너지를 인가(S)하여 제1 단결정 실리콘 기판(110)을 분리제거할 수 있다. 이는 도 7과 동일하게 진행될 수 있다.Next, referring to FIG. 13, the first single crystal silicon substrate 110 may be separated and removed by applying (S) energy to the silicon peeling layer 120. This can be done in the same manner as in FIG. 7.
다음으로, 도 14를 참조하면, 제1 단결정 실리콘 에피택셜층(130)의 타면으로부터 일면 방향으로 두께를 감축하면서 제거(G)할 수 있다. 이는 도 8과 동일하게 진행될 수 있다.Next, referring to FIG. 14, the first single crystal silicon epitaxial layer 130 may be removed (G) while reducing the thickness in one direction from the other surface. This can be done in the same manner as in FIG. 8.
다음으로, 도 15를 참조하면, 두께 감축 및 제거(G) 후에 SOI 기판(100)의 제조를 완료할 수 있다. 절연 패턴(140)은 제2 단결정 실리콘 에피택셜층(150)을 구획하고, 구획된 제2 단결정 실리콘 에피택셜층(150)의 각 영역들은 액티브 SOI로 사용될 수 있다. 이후에, 반도체, 메모리 형성 공정을 더 수행할 수 있다.Next, referring to FIG. 15, manufacturing of the SOI substrate 100 may be completed after thickness reduction and removal (G). The insulating pattern 140 partitions the second single crystal silicon epitaxial layer 150, and regions of the partitioned second single crystal silicon epitaxial layer 150 may be used as an active SOI. Thereafter, a process of forming a semiconductor or a memory may be further performed.
위와 같이 본 발명은, 처음부터 active 영역에만 SOI 층을 형성할 수 있고, 표면 균일도가 우수한 SOI 기판을 제조할 수 있으며, 제조 공정을 단순화하여 공정 시간, 원가를 절감하고 생산성을 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, an SOI layer can be formed only in the active area from the beginning, an SOI substrate having excellent surface uniformity can be manufactured, and the manufacturing process can be simplified to reduce process time and cost, and improve productivity. There is.
본 발명은 상술한 바와 같이 바람직한 실시예를 들어 도시하고 설명하였으나, 상기 실시예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양한 변형과 변경이 가능하다. 그러한 변형예 및 변경예는 본 발명과 첨부된 특허청구범위의 범위 내에 속하는 것으로 보아야 한다.Although the present invention has been illustrated and described with reference to a preferred embodiment as described above, it is not limited to the above embodiment, and within the scope not departing from the spirit of the present invention, various It can be transformed and changed. Such modifications and variations should be viewed as falling within the scope of the present invention and the appended claims.

Claims (12)

  1. (a) 제1 단결정 실리콘 기판의 일면 상에 실리콘 박리층을 형성하는 단계;(a) forming a silicon release layer on one surface of the first single crystal silicon substrate;
    (b) 실리콘 박리층 상에 제1 단결정 실리콘 에피택셜층을 형성하는 단계;(b) forming a first single crystal silicon epitaxial layer on the silicon exfoliation layer;
    (c) 제1 단결정 실리콘 에피택셜층의 일면 상에 복수의 절연 패턴을 형성하는 단계;(c) forming a plurality of insulating patterns on one surface of the first single crystal silicon epitaxial layer;
    (d) 제1 단결정 실리콘 에피택셜층 및 절연 패턴 상에 제2 단결정 실리콘 에피택셜층을 형성하는 단계;(d) forming a second single crystal silicon epitaxial layer on the first single crystal silicon epitaxial layer and the insulating pattern;
    (e) 제2 단결정 실리콘 에피택셜층을 평탄화하는 단계;(e) planarizing the second single crystal silicon epitaxial layer;
    (f) 제1 단결정 실리콘 기판 및 표면 상에 산화층이 형성된 제2 단결정 실리콘 기판을 접합하는 단계;(f) bonding a first single crystal silicon substrate and a second single crystal silicon substrate having an oxide layer formed thereon;
    (g) 실리콘 박리층에 에너지를 인가하여 제1 단결정 실리콘 기판을 분리 제거하는 단계;(g) applying energy to the silicon exfoliation layer to separate and remove the first single crystal silicon substrate;
    (h) 제1 단결정 실리콘 에피택셜층의 타면으로부터 일면 방향으로 두께를 감축하면서 제거하는 단계(h) removing the first single crystal silicon epitaxial layer while reducing its thickness in one direction from the other surface
    를 포함하는, SOI 기판 제조 방법.Containing, SOI substrate manufacturing method.
  2. 제1항에 있어서,The method of claim 1,
    (a) 단계와 (b) 단계 사이에,Between steps (a) and (b),
    (1) 실리콘 박리층의 공극(pore) 및 표면 상을 산화 처리하는 단계;(1) oxidizing the pores and the surface of the silicon release layer;
    (2) 실리콘 박리층의 표면 상의 산화물을 제거하는 단계;(2) removing oxides on the surface of the silicon release layer;
    (3) 실리콘 박리층의 표면을 재결정화하는 단계(3) recrystallization of the surface of the silicon release layer
    를 더 포함하는, SOI 기판 제조 방법. Further comprising, SOI substrate manufacturing method.
  3. 제1항에 있어서,The method of claim 1,
    (e) 단계에서, 절연 패턴이 형성된 부분까지 제2 단결정 실리콘 에피택셜층의 두께를 감축하며 평탄화하는, SOI 기판 제조 방법.In step (e), the thickness of the second single crystal silicon epitaxial layer is reduced and planarized to the portion where the insulating pattern is formed.
  4. 제1항에 있어서,The method of claim 1,
    절연 패턴은 산화 실리콘, 질화 실리콘 중 적어도 어느 하나의 재질인, SOI 기판 제조 방법.The insulating pattern is a material of at least one of silicon oxide and silicon nitride, a method of manufacturing an SOI substrate.
  5. 제1항에 있어서,The method of claim 1,
    (e) 단계의 평탄화는 H 2 어닐링, Ar 어닐링 또는 CMP 방법으로 수행하는, SOI 기판 제조 방법.The planarization of step (e) is performed by H 2 annealing, Ar annealing, or CMP method.
  6. 제1항에 있어서,The method of claim 1,
    (g) 단계는, 워터젯(water-jet) 방법 또는 기계적 충격(mechanical shock, mechanical lift) 방법으로 에너지를 인가하여 실리콘 박리층을 절단하고, 제1 단결정 실리콘 기판을 분리 제거하는 단계인, SOI 기판 제조 방법.Step (g) is a step of cutting the silicon release layer by applying energy by a water-jet method or a mechanical shock, mechanical lift method, and separating and removing the first single crystal silicon substrate, the SOI substrate Manufacturing method.
  7. 제1항에 있어서,The method of claim 1,
    (h) 단계에서, 절연 패턴이 형성된 부분까지 두께를 감축하는, SOI 기판 제조 방법.In step (h), reducing the thickness to the portion where the insulating pattern is formed, SOI substrate manufacturing method.
  8. 제3항 또는 제7항에 있어서,The method according to claim 3 or 7,
    절연 패턴이 두께 감축의 스톱퍼(stopper)로 기능하는, SOI 기판 제조 방법.The method of manufacturing an SOI substrate in which the insulating pattern functions as a stopper for reducing the thickness.
  9. 제1항에 있어서,The method of claim 1,
    (e) 단계와 (f) 단계 사이에,Between step (e) and step (f),
    (e2) 적어도 제2 단결정 실리콘 에피택셜층의 상부에 디싱 산화층을 형성하는 단계;(e2) forming a dishing oxide layer on at least the second single crystal silicon epitaxial layer;
    를 더 포함하는, SOI 기판 제조 방법.Further comprising a, SOI substrate manufacturing method.
  10. 제9항에 있어서,The method of claim 9,
    (e2) 단계에서, 디싱 산화층은 절연 패턴의 높이보다 낮은 높이까지 평탄화된 제2 단결정 실리콘 에피택셜층의 홈부에 형성하는, SOI 기판 제조 방법.In step (e2), the dishing oxide layer is formed in the groove portion of the second single crystal silicon epitaxial layer planarized to a height lower than the height of the insulating pattern.
  11. 제9항에 있어서,The method of claim 9,
    (e2) 단계에서, 디싱 산화층은 절연 패턴의 높이보다 낮은 높이까지 평탄화된 제2 단결정 실리콘 에피택셜층의 홈부 및 절연 패턴 상부에 형성하는, SOI 기판 제조 방법.In step (e2), the dishing oxide layer is formed on the groove portion and the insulating pattern of the second single crystal silicon epitaxial layer planarized to a height lower than the height of the insulating pattern.
  12. 제9항에 있어서,The method of claim 9,
    (e2) 단계와 (f) 단계 사이에, 디싱 산화층의 두께를 감축하며 평탄화하는 단계를 더 포함하는, SOI 기판 제조 방법.Between (e2) and (f) steps, further comprising the step of flattening and reducing the thickness of the dishing oxide layer, SOI substrate manufacturing method.
PCT/KR2020/014917 2019-11-11 2020-10-29 Method of manufacturing soi substrate WO2021096114A1 (en)

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JP2000349264A (en) * 1998-12-04 2000-12-15 Canon Inc Method for manufacturing, use and utilizing method of semiconductor wafer
JP2002057310A (en) * 2000-08-08 2002-02-22 Sony Corp Method of forming soi substrate
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JP4272796B2 (en) * 1999-03-25 2009-06-03 キヤノン株式会社 Substrate processing method

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JP4272796B2 (en) * 1999-03-25 2009-06-03 キヤノン株式会社 Substrate processing method
JP2002057310A (en) * 2000-08-08 2002-02-22 Sony Corp Method of forming soi substrate
JP2004096044A (en) * 2002-09-04 2004-03-25 Canon Inc Substrate and manufacturing method thereof
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