JP2010153896A - Solid-state imaging device, production method of the same and semiconductor device, production method process of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device, its production method and a semiconductor device, its production method that are capable of allowing the thickness of a semiconductor substrate to be reduced without using an SOI substrate to reduce costs. <P>SOLUTION: The solid-state imaging device includes an imaging region in which pixels composed of a photoelectric conversion element and multiple MOS transistors are arrayed, peripheral circuits, and columnar termination detectors 63 extending from the surface of a semiconductor substrate 21 in the thickness direction, having a higher hardness than the semiconductor substrate 21 and formed with a material film 66 with further higher hardness on the bottom surface in the thickness direction, on the semiconductor substrate 21, and is produced by reducing the thickness of the semiconductor substrate by chemically and mechanically polishing the back surface to a position in which the termination detector 63 is exposed, by forming MOS transistors Tr1 on the top surface of the semiconductor substrate 21, and by allowing incident light to be taken in through the backside of the semiconductor substrate 21. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the same, and a semiconductor device and a method for manufacturing the same, which require a thin semiconductor substrate.

  Typical examples of the solid-state imaging device include a CMOS solid-state imaging device that reads by specifying an XY address, and a CCD solid-state imaging device that is a charge transfer type. Any of these solid-state imaging devices photoelectrically converts light incident on a two-dimensionally arranged photodiode, and one of the charges (for example, electrons) is used as a signal charge.

  The CMOS solid-state imaging device is generally a front-illuminated type CMOS solid-state imaging device that irradiates light from the surface side where the wiring layer of the semiconductor substrate is formed and detects the light with a photodiode formed on the semiconductor substrate. However, in this surface irradiation type CMOS solid-state imaging device, there is a multilayer wiring in the path of the irradiated light, particularly the oblique light path in the periphery of the effective pixel region, and light is kicked by this multilayer wiring. It is known that the light utilization efficiency is lowered and the sensitivity is lowered. For this reason, a back-illuminated CMOS solid-state imaging device that irradiates light from the back side of a semiconductor substrate having a multilayer wiring formed on the front side is promising (see Patent Document 1).

  Also in CCD solid-state imaging devices, it is known that light is absorbed by the interlayer insulating layer on the device and the sensitivity is lowered, and a structure is proposed in which light is incident and photoelectrically converted from the back side of the substrate. (See Patent Document 2).

JP 2003-31785 A JP-A-6-29506

  By the way, in a CMOS solid-state imaging device, for example, when light is irradiated from the back surface of the substrate, the thickness of the silicon substrate is usually several hundred μm and cannot transmit light, so the silicon substrate is thinned to, for example, 10 μm or less. There is a need to. When the film thickness of the silicon layer varies, the incident intensity of light varies and the color unevenness causes a problem.

  On the other hand, a method using an SOI (Silicon On Insulator) substrate has been considered in order to prevent variations in the thickness of the silicon layer. In other words, mechanical polishing with a high etching rate using an SOI substrate, subsequent CMP (chemical mechanical polishing) treatment, and subsequent wet etching are performed to stop the thinning of the SiO2 layer, thereby suppressing variations in the thickness of the silicon layer. I am doing so.

A manufacturing method of a backside illumination type CMOS solid-state imaging device using an SOI substrate will be described with reference to FIGS.
First, as shown in FIG. 17A, an SOI substrate 4 in which a thin silicon layer 3 is formed on a silicon substrate 1 via a silicon oxide film (SiO2 film) 2 is prepared. An alignment mark 5 is formed at a required position of the silicon layer 3 of the SOI substrate 4.
Next, as shown in FIG. 17B, the pixel separation region (not shown), the semiconductor well region (not shown), the photoelectric conversion element of the imaging region with reference to the alignment mark 5 from the surface side of the silicon layer 3. A plurality of MOS transistors Tr and the like constituting the pixel are formed together with the photodiode PD and the photodiode PD having a HAD (Hole Accumulation Diode) structure. Furthermore, a multilayer wiring layer 6 in which a multilayer wiring 8 is formed via an interlayer insulating layer 7 is laminated thereon.

Next, as shown in FIG. 18C, a support substrate 9 made of, for example, a silicon substrate is bonded onto the multilayer wiring layer 6.
Next, as shown in FIG. 18D, the SOI substrate 4 is inverted, and the silicon substrate 1 is polished and removed by back grinding (mechanical roughing) and wet etching using the silicon oxide film 2 as a stopper film. Further, the silicon oxide film 2 is removed by wet etching.

Next, as shown in FIG. 19E, for example, a silicon nitride film 10 serving as a passivation film is formed on the back surface of the silicon layer 3, and an electrode is derived from a part of the silicon layer 3, that is, the wiring layer 8 a together with the silicon nitride film 10. An opening 11 reaching the wiring layer 8a is formed in the portion to be etched by selective etching. Further, an insulating film 12 such as a silicon oxide film is formed so as to cover the surface of the silicon nitride film 10 from the inner wall of the opening 11. A conductor layer 13 connected to the wiring layer 8a in the opening 11 is formed and an electrode pad 14 connected to the conductor layer 13 and facing the back surface is formed to form a so-called back electrode 15.
Next, as shown in FIG. 19F, a color filter 16 and an on-chip lens 17 are formed on the back surface at a position corresponding to the photodiode PD of each pixel to obtain a back-illuminated CMOS solid-state imaging device 18.

  However, when a back-illuminated CMOS solid-state imaging device is manufactured using an SOI substrate, there is a problem that the manufacturing cost increases because the SOI substrate is more expensive than a silicon substrate.

  Such a problem using an SOI substrate also occurs in a back-illuminated CCD solid-state imaging device, and is not limited to a solid-state imaging device. For example, a semiconductor device or / and a multilayer wiring are formed on both front and back surfaces of a semiconductor substrate. This can also occur in the semiconductor integrated circuit device.

  In view of the above, the present invention provides a solid-state imaging device, a manufacturing method thereof, a semiconductor device, and a manufacturing method thereof, which can reduce the thickness of a semiconductor substrate without using an SOI substrate and reduce costs. It is.

  The solid-state imaging device according to the present invention is a so-called back-illuminated type, and includes an imaging region in which pixels including a photoelectric conversion element and a plurality of MOS transistors are arranged on a semiconductor substrate, a peripheral circuit, and a surface of the semiconductor substrate. And a columnar terminal detection part having a material film having a higher hardness on the bottom surface in the thickness direction and having a higher hardness than the semiconductor substrate in the thickness direction, and the semiconductor substrate is subjected to chemical mechanical polishing from the back side. The film is thinned to a position where the end detection portion is exposed, the MOS transistor is formed on the surface of the semiconductor substrate, and incident light is captured from the back surface of the semiconductor substrate.

  A method for manufacturing a solid-state imaging device according to the present invention includes: an imaging region in which pixels each including a photoelectric conversion element and a plurality of MOS transistors existing on a surface of the semiconductor substrate are arranged on a semiconductor substrate; a peripheral circuit; A step of forming a columnar termination detector having a material film having a hardness higher than that of the semiconductor substrate in the thickness direction from the surface and having a higher hardness on the bottom surface in the thickness direction; and the termination detection unit from the back surface of the semiconductor substrate. And a step of thinning the semiconductor substrate by chemical mechanical polishing to a position where the semiconductor substrate is exposed, and the back surface of the semiconductor substrate is used as a surface for capturing incident light.

In the solid-state imaging device and the method for manufacturing the same, it is preferable that the termination detection unit is formed also as an element isolation region. It is desirable to form the end detection part with a columnar layer different from the element isolation region.
It is desirable that the end detection unit be formed to have a length corresponding to the thickness of the photoelectric conversion element that performs photoelectric conversion by light absorption.
It is desirable to form the end detection portions by the plurality of columnar layers at intervals that do not cause uneven thickness in the chemical mechanical polishing process.

  A semiconductor device according to the present invention includes a semiconductor substrate and a columnar end detection unit in which a material film having a hardness greater than that of the semiconductor substrate in the thickness direction from the surface of the semiconductor substrate and having a greater hardness on the bottom surface in the thickness direction is formed. And components of the semiconductor device formed on the front surface and the back surface of the semiconductor substrate that have been thinned to a position where the termination detector is exposed by chemical mechanical polishing from the back surface.

  In the method for manufacturing a semiconductor device according to the present invention, a columnar end detection unit having a material film having a hardness higher than that of the semiconductor substrate in the thickness direction from the surface and having a higher hardness on the bottom surface in the thickness direction is formed on the semiconductor substrate. A step of forming a part of a component of the semiconductor device on the front surface side of the semiconductor substrate, a step of attaching a support substrate to the front surface side of the semiconductor substrate, and chemical mechanical polishing from the back surface of the semiconductor substrate. Performing a process of thinning the semiconductor substrate by stopping chemical mechanical polishing in a self-aligned manner when the bottom surface of the termination detection unit appears on the back surface, and a component of the semiconductor device on the back surface side of the semiconductor substrate. Forming other parts.

  In the semiconductor device and the manufacturing method thereof, it is desirable that the termination detection unit is formed also as an element isolation region. It is desirable that the end detection unit is formed of a columnar layer different from the element isolation region. The interval between the end detection portions by the columnar layer is preferably set to an interval that does not cause unevenness in thickness during the chemical mechanical polishing process.

  According to the solid-state imaging device of the present invention, without using an SOI substrate, a semiconductor substrate thinned to a position where the termination detection unit is exposed by chemical mechanical polishing by providing a termination detection unit with high hardness on the semiconductor substrate is used. Since the structure is a back-illuminated structure, the cost can be reduced, and a back-illuminated solid-state image sensor with high accuracy can be provided. Since the film is thinned by chemical mechanical polishing, it is easy to form a thin film from a thick semiconductor substrate. Since a harder material film is formed on the bottom surface of the end detection unit, the stopper function as the end detection unit can be further enhanced. Therefore, it is possible to provide a solid-state imaging device that can simplify the manufacturing process.

According to the method for manufacturing a solid-state imaging device according to the present invention, the termination detection unit having a high hardness is formed on the semiconductor substrate, the chemical mechanical polishing is performed from the back surface of the semiconductor substrate, and the bottom surface of the termination detection unit appears on the back surface. By stopping the chemical mechanical polishing in a self-aligning manner and reducing the thickness of the semiconductor substrate, the thickness of the semiconductor substrate can be reduced without using an SOI substrate. Therefore, the manufacturing process of the solid-state imaging device can be simplified and the manufacturing cost can be greatly reduced. Since the material film having higher hardness is formed on the bottom surface of the end detection unit, the stopper function as the end detection unit can be further enhanced. Since a thin film is formed by chemical mechanical polishing, a thin film from a thick semiconductor substrate can be formed only by chemical mechanical polishing, and the manufacturing process can be further simplified. Chemical mechanical polishing is advantageous for thinning a thick semiconductor substrate because a large amount of slurry is processed at normal pressure.
When this manufacturing method is applied to the manufacture of a CMOS solid-state imaging device, the general-purpose CMOS process technology can be used as it is.

The structure and the manufacturing process can be simplified by forming the end detection part also as the element isolation region.
By forming the end detection part with a columnar layer different from the element isolation region, it is possible to provide a back-illuminated solid-state imaging device including a photoelectric conversion element that can obtain a desired potential depth.
By making the length in the depth direction of the terminal detection part a length corresponding to the thickness of the photoelectric conversion element, it is possible to form a semiconductor thin film substrate corresponding to the thickness of the photoelectric conversion element.
By forming the interval between the end detection portions by the columnar layer at an interval that does not cause unevenness in chemical mechanical polishing, a thinned semiconductor substrate having a uniform thickness can be obtained.

  According to the semiconductor device according to the present invention, without using an SOI substrate, a semiconductor substrate thinned to a position where the termination detection unit is exposed by chemical mechanical polishing is provided by providing a termination detection unit with high hardness on the semiconductor substrate. Since the constituent elements are formed on both the front and back surfaces, it is possible to reduce the cost and provide a highly accurate semiconductor device. Since the film is thinned by chemical mechanical polishing, it is easy to form a thin film from a thick semiconductor substrate. Since a harder material film is formed on the bottom surface of the end detection unit, the stopper function as the end detection unit can be further enhanced. Therefore, a semiconductor device that can simplify the manufacturing process can be provided.

According to the method for manufacturing a semiconductor device of the present invention, a termination detector having high hardness is formed on a semiconductor substrate, chemical mechanical polishing is performed from the back surface of the semiconductor substrate, and the bottom surface of the termination detector appears on the back surface. By stopping the mechanical polishing in a self-aligning manner and reducing the thickness of the semiconductor substrate, it is possible to reduce the thickness of the semiconductor substrate without using an SOI substrate. Therefore, the manufacturing process of the semiconductor device can be simplified and the manufacturing cost can be greatly reduced. Since the material film having higher hardness is formed on the bottom surface of the end detection unit, the stopper function as the end detection unit can be further enhanced. Since a thin film is formed by chemical mechanical polishing, a thin film from a thick semiconductor substrate can be formed only by chemical mechanical polishing, and the manufacturing process can be further simplified. Chemical mechanical polishing is advantageous for thinning a thick semiconductor substrate because a large amount of slurry is processed at normal pressure.
When this manufacturing method is applied to the manufacture of a CMOS integrated circuit device, the general-purpose CMOS process technology can be used as it is.

The structure and the manufacturing process can be simplified by forming the end detection part also as the element isolation region.
By forming the end detection part with a columnar layer different from the element isolation region, it is possible to provide a semiconductor device including components on a semiconductor substrate thinned to a desired thickness.
By forming the interval between the end detection portions by the columnar layer at an interval that does not cause unevenness in chemical mechanical polishing, a thinned semiconductor substrate having a uniform thickness can be obtained.

FIG. 6 is a manufacturing process diagram (part 1) illustrating the method for manufacturing the solid-state imaging element according to the first embodiment of the present invention; It is a manufacturing process figure (the 2) which shows the manufacturing method of the solid-state image sensing device concerning a 1st embodiment of the present invention. It is a manufacturing process figure (the 3) which shows the manufacturing method of the solid-state image sensing device concerning a 1st embodiment of the present invention. FIG. 7 is a manufacturing process diagram (part 4) illustrating the method for manufacturing the solid-state imaging element according to the first embodiment of the present invention; It is a manufacturing process figure (the 5) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment of this invention. It is a manufacturing process figure (the 6) which shows the manufacturing method of the solid-state image sensor which concerns on 1st Embodiment of this invention. It is sectional drawing which shows one example of the unit pixel of a back irradiation type CMOS solid-state image sensor. FIGS. 8A to 8C are manufacturing process diagrams illustrating an example of a termination detection unit using a columnar layer according to the present invention. FIGS. It is a manufacturing process figure which shows the other example of the termination | terminus detection part by the columnar layer which concerns on AB. It is a manufacturing-process figure (the 1) which shows the manufacturing method of the solid-state image sensor which concerns on 2nd Embodiment of this invention. It is a manufacturing-process figure (the 2) which shows the manufacturing method of the solid-state image sensor which concerns on 2nd Embodiment of this invention. It is a manufacturing-process figure (the 3) which shows the manufacturing method of the solid-state image sensor which concerns on 2nd Embodiment of this invention. It is a manufacturing process figure (the 4) which shows the manufacturing method of the solid-state image sensor which concerns on 2nd Embodiment of this invention. It is a block diagram which shows the principal part of the solid-state image sensor which concerns on 3rd Embodiment of this invention. It is a block diagram which shows the principal part of the solid-state image sensor which concerns on 4th Embodiment of this invention. It is a block diagram which shows the principal part of the semiconductor device which concerns on 4th Embodiment of this invention. It is a manufacturing process figure (the 1) of the back surface irradiation type CMOS solid-state image sensor of AB comparative example. C to D are manufacturing process diagrams (part 2) of the backside illumination type CMOS solid-state imaging device of the comparative example. EF is a manufacturing process diagram (No. 3) of the backside illumination type CMOS solid-state imaging device of the comparative example;

  Embodiments of the present invention will be described below with reference to the drawings.

1 to 6 show a first embodiment in which the solid-state imaging device according to the present invention is applied to a backside illumination type CMOS solid-state imaging device. Here, a backside illumination type CMOS solid-state imaging device will be described together with a manufacturing method thereof.
In this embodiment, first, as shown in FIG. 1, a semiconductor substrate (for example, a silicon wafer) 21 is prepared, and an element isolation region 22 that also serves as a termination detection unit is formed on the semiconductor substrate 21. The element isolation region 22 is used for pixel separation for separating each pixel. The end detection unit is formed of a material having a hardness higher than that of the semiconductor substrate, and can be formed of an insulator such as a silicon oxide film or a silicon nitride film. Therefore, the element isolation region 22 also serving as the termination detection unit can be formed by a trench isolation region or a LOCOS (selective oxidation) isolation region in which a silicon oxide film is embedded. In this case, an element isolation region 22 having a depth d1 of the same level as the depth (depth from the substrate surface) of the photodiode PD that will be the finally formed photoelectric conversion element is formed. That is, the length d1 in the depth direction of the element isolation region 22 is a length corresponding to the thickness of the photodiode PD.

  Next, as shown in FIG. 2, a plurality of MOS transistors Tr for reading signal charges from the photodiode PD to be formed later are formed in each unit pixel region 23 partitioned by the element isolation region 22 of the semiconductor substrate 21. . The plurality of MOS transistors Tr are formed on the substrate surface side.

  The plurality of MOS transistors Tr are composed of various numbers, and may be composed of four transistors, for example, a charge read transistor, a reset transistor, an amplifier transistor, and a vertical selection transistor. The photodiode PD, the source / drain region 24, and the gate electrode 25 between them form a charge readout transistor, and the other pair of source / drain regions 24 and the gate electrode 26 between them constitute another transistor. . After the photodiode PD and the MOS transistor Tr are formed, an interlayer insulating layer 27 is formed, and a contact hole 28 is formed at a position corresponding to a required region (for example, a source / drain region, a gate electrode). A detailed configuration of the unit pixel will be described later.

Next, as shown in FIG. 3, a multilayer wiring 30 connected to a required region and a multilayer wiring layer 31 composed of an interlayer insulating film 27 are formed.
Next, as shown in FIG. 4, a support substrate 33 such as a silicon substrate is bonded onto the multilayer wiring layer 31.

  Next, as shown in FIG. 5, the semiconductor substrate 21 is inverted and the back surface side of the semiconductor substrate 21 is shaved by a chemical mechanical polishing (CMP) method. In this case, the polishing is performed up to a position where the bottom surface of the element isolation region 22 that also serves as the termination detection unit is exposed. The silicon on the back surface to be polished and the silicon oxide (SiO2) layer forming the element isolation region 22 have a difference in hardness when polished by CMP, and the silicon oxide layer has a higher hardness. Since there is a difference in hardness, the silicon oxide layer in the element isolation region 22 that appears on the surface by backside polishing acts as a stopper, and the silicon substrate 22 appears in a self-aligned manner without further polishing. . That is, the end of polishing is detected in a self-aligned manner by the bottom surface of the element isolation region 22. When the bottom surface of the element isolation region 22 appears, the CMP polishing is stopped.

  Next, as shown in FIG. 6, a photodiode PD is formed on the semiconductor substrate 21 by ion implantation from the back surface of the substrate. The photodiode PD is formed to the same depth as the depth d1 of the element isolation region 22. The photodiode PD can also be formed by ion implantation from the substrate surface side in the step of FIG. Further, a protective insulating film 35 is formed on the surface of the substrate, and a color filter 36 and an on-chip lens 37 are formed thereon to obtain a target backside illuminating type CMOS solid-state imaging device 38.

  Note that the termination detection unit can be formed on an element isolation region, a scribe line, or the like.

  FIG. 7 shows an example of a unit pixel composed of a photodiode PD and a plurality of MOS transistors Tr. The unit pixel includes, for example, a plurality of MOS transistors including a p-type semiconductor well region 41, an n + source / drain region 42, a gate insulating film 43, and a gate electrode 44 in a region surrounded by the element isolation region 22 of the n-type semiconductor substrate 21. A transistor Tr is formed, and a photodiode PD is formed so as to extend from the back surface of the substrate to the front surface and to extend under the p-type semiconductor well region 41 in which the MOS transistor Tr is formed. The photodiode PD is formed by an n + charge storage region 46 and an n semiconductor region 47, and p + semiconductor regions 48 and 49 serving as accumulation layers for suppressing dark current formed on both the front and back surfaces.

  An example of the case where the element isolation region 22 serving as the termination detection portion is formed in the trench isolation region is as shown in FIG. 8, after forming a groove (trench) 51 in the silicon substrate 21 (FIG. A), For example, a silicon oxide film 52 is formed by CVD (chemical vapor deposition) so as to be buried (FIG. B), and then the silicon oxide film 52 is etched back to leave the silicon oxide film 52 only in the trench 51. In this way, the trench isolation region 221 is formed.

  As shown in FIG. 9, another example of the case where the element isolation region 22 serving as the end detection portion is formed in the trench isolation region is as follows. After forming a groove (trench) 51 in the silicon substrate 21, the inner wall surface of the groove and the substrate are formed. A silicon nitride film 53 is formed by CVD, for example, so as to cover the surface (see FIG. A), and then a silicon oxide film 52 is formed by CVD, for example, so as to be embedded in the trench 51. Thereafter, the silicon oxide film 52 and the silicon nitride film are formed. The silicon nitride film 53 and the silicon oxide film 52 are left only in the trench 51 by etching back 53 (see FIG. B). In this manner, a trench isolation region 222 in which the silicon nitride film 53 is formed on the bottom surface of the groove 51 is formed. In the trench isolation region 222, the silicon nitride film 53 has a higher hardness than the silicon oxide film 52, so that it is more suitable as a termination detection unit.

  When the element isolation region 22 serving as the termination detection unit is formed in the LOCOS isolation region, although not shown, a silicon nitride film patterned on a silicon substrate or a two-layer film structure of a silicon nitride film and a polysilicon film as usual After forming, a silicon oxide (SiO2) layer is formed on the surface of the substrate on which the silicon nitride film is not formed, and then the silicon nitride film is removed to form a LOCOS isolation region by the silicon oxide film.

According to the back-illuminated CMOS solid-state imaging device 38 according to the first embodiment described above, a silicon substrate that is thinned by an element isolation region that also serves as a termination detection unit provided on the silicon substrate 21 without using an SOI substrate. Since each component of the solid-state imaging device is formed and configured, it is possible to provide a backside illumination type CMOS solid-state imaging device that is inexpensive and accurate.
According to the manufacturing method of the first embodiment, an SOI substrate is not required and the manufacturing process can be simplified, so that the manufacturing cost can be greatly reduced. General-purpose CMOS process technology can be used as it is.

  Since the end detection portion is formed in the element isolation region, when the semiconductor substrate 21 is thinned by chemical mechanical polishing, it is possible to prevent so-called in-plane variation of the film thickness in which the thickness of the semiconductor substrate varies locally. A uniform thin film can be formed over the entire area. Since chemical polishing is used, it is easy to reduce the thickness of the semiconductor substrate, such as shortening the time for thinning.

10 to 13 show a second embodiment in which the solid-state imaging device according to the present invention is applied to a back-illuminated CMOS solid-state imaging device. Here again, a back-illuminated CMOS solid-state imaging device will be described together with its manufacturing method.
In this embodiment, first, as shown in FIG. 10, a semiconductor substrate (for example, a silicon wafer) 21 is prepared, and an element isolation region 62 for separating each pixel is formed on the semiconductor substrate 21. Further, a termination detecting portion 63 made of a columnar layer is formed on the semiconductor substrate 21 from the substrate surface to a required depth. The element isolation region 62 can be formed by a trench isolation region or a LOCOS (selective oxidation) isolation region in which a silicon oxide film is embedded as described above. The end detection unit 63 is formed deeper than the element isolation region 62 and is formed of a material having a hardness higher than that of the semiconductor substrate 21 as described above. The end detection unit 62 can be formed of, for example, a silicon oxide film or a silicon nitride film. The end detection unit 63 is formed at a depth d1 that is the same as the depth (depth from the substrate surface) of the photodiode PD to be finally formed as a photoelectric conversion element. That is, the length d1 of the end detection unit 63 in the depth direction is a length corresponding to the thickness of the photodiode PD.

  A plurality of the end detection units 63 are formed on the semiconductor substrate 21, and the interval w1 between the adjacent end detection units 63 is set to an interval that does not cause local thickness unevenness in back surface polishing by the CMP method described later. The end detection unit 63 can be formed on any of the semiconductor substrates 21, but it is desirable to form the end detection unit 63 in a region to be a solid-state imaging chip in order to prevent unevenness in thickness of each solid-state imaging chip. In the case of illustration, in order to understand the explanation, it is formed outside the element isolation region 62 that divides the unit pixel, but it may be formed in a range that does not give thickness unevenness during back surface polishing. When miniaturization and high integration of pixels are considered, in the case of a solid-state image sensor in which an imaging region (pixel region), a peripheral circuit portion, and the like are formed, the pixel is provided outside the imaging region (outside that does not affect the pixel). Is preferred.

  The end detection unit 63 using a columnar layer forms a trench in the semiconductor substrate 21, and a silicon oxide film (see FIG. 8), a silicon nitride film, or a silicon nitride film similar to that described in FIG. And embedded with a silicon oxide film.

  Next, as shown in FIG. 11, a plurality of MOS transistors Tr, such as charge readout transistors, constituting the pixel are formed on the substrate surface side of each unit pixel region partitioned by the element isolation region 62 of the semiconductor substrate 21 as described above. , Four transistors of a reset transistor, an amplifier transistor, and a vertical selection transistor are formed. Next, after forming the multilayer wiring layer 31 including the interlayer insulating film 27 and the multilayer wiring 30, a support substrate 33 made of, for example, a silicon substrate is bonded onto the multilayer wiring layer 31.

  Next, as shown in FIG. 12, the semiconductor substrate 21 is inverted and the back side of the semiconductor substrate 21 is scraped off by CMP. In this case, the polishing is performed until the bottom surface of the end detection unit 63 is exposed, and the polishing end is detected when the end detection unit 63 is exposed due to the hardness difference between the end detection unit 63 and the semiconductor substrate 21, and the polishing is stopped. .

  Next, as shown in FIG. 13, a photodiode PD is formed on the semiconductor substrate 21 by ion implantation from the back surface of the substrate. The photodiode PD is formed to the same depth as the depth d1 of the element isolation region 22. Note that the photodiode PD can also be formed by ion implantation from the substrate surface side in the step of FIG. A semiconductor element dividing region 65 can be formed under the element isolation region 62 by the insulator. Further, a protective insulating film 35 is formed on the surface of the substrate, and a color filter 36 and an on-chip lens 37 are formed thereon to obtain a target backside illumination type CMOS solid-state imaging device 64. The unit pixel configuration of the present embodiment is the same as the configuration of FIG. 7 described above.

  According to the second embodiment described above, by properly arranging a plurality of terminal polishing portions 63 by columnar layers serving as polishing stoppers in chemical mechanical polishing (CMP) separately from the element isolation regions 62, the CMP process is performed. At this time, even if the silicon substrate 21 is excessively shaved, CMP control can be performed without causing uneven thickness. In addition, the same effects as those of the first embodiment described above are obtained.

  FIG. 14 shows a third embodiment of a backside illumination type CMOS solid-state imaging device according to the present invention. In the present embodiment, a region 63B where the end detection units 63 are densely gathered is partially formed in the configuration of the end detection unit 63 shown in FIG. That is, as the end detection unit 63 using a columnar layer, a dense region 63B in which the end detection unit 63 has a high density is partially formed in a state where a sparse region 63A in which the end detection unit 63 has a low concentration is uniformly formed. To do. Since other configurations are the same as those in the figure, the corresponding parts are denoted by the same reference numerals and redundant description is omitted.

According to the third embodiment, by forming the dense region 63B of the end detection unit 63, the accuracy of CMP can be further increased. That is, the semiconductor substrate 21 can be thinned by CMP with a more uniform film thickness. In addition, the same effects as those of the second embodiment are obtained.

  FIG. 15 shows a fourth embodiment of a back-illuminated CMOS solid-state imaging device according to the present invention. In the present embodiment, as the configuration of the termination detection unit 63 by the columnar layer of FIG. 13 described above, a silicon nitride film (SiN film) or the like with respect to the silicon substrate 21 is particularly formed on the bottom surface of the columnar layer, that is, the bottom surface exposed on the substrate backside. The material film 66 having high selectivity (high hardness) is formed. As the material film 66, for example, polysilicon, tungsten (W), SiW, Ti, TiSi, TiN, NSi, CoSi, and other metal silicide films can be used in addition to SiN. The film thickness t1 of the material film 66 can be set in a range of 1/10 to 1 / 20th of the depth d1 of the end detection part 63 (d1 / 10 to d1 / 20 = t1).

  For example, the termination detector 63 can be formed of the silicon oxide film 67 and the silicon nitride film 66. In this case, after forming the trench, a silicon nitride film 66 is formed on the entire surface of the substrate including the inner wall surface of the trench, and a silicon oxide film 67 is formed on the entire surface of the substrate so as to be embedded in the trench. By etching back the entire silicon oxide film 67 to the substrate surface, the end detection unit 63 can be formed. Other configurations are the same as those of the first embodiment described above, and corresponding portions are denoted by the same reference numerals and redundant description is omitted.

  According to the fourth embodiment, by forming the material film 66 having a high hardness on the bottom surface of the end detection unit 63, the stopper function as the end detection unit 63 can be further enhanced. In addition, the same effects as those of the second embodiment are obtained.

  Note that the width w1 of the end detection unit 63 can be greater than or equal to the minimum line width of the solid-state imaging device. Incidentally, the light incident distance to the semiconductor substrate by backside illumination is, for example, about 0.5 μm for blue light, about 3 μm for green light, about 5 μm for red light, and 10 μm for infrared light. Degree. Therefore, in the red, green, and blue color solid-state imaging devices, the length d1 of the end detection units 22 and 63 in the depth direction can be set to about 5.0 μm. When the infrared light is required, the length d1 of the end detection units 22 and 63 in the depth direction can be set to about 10 .mu.m.

  In the above-described embodiment, the present invention is applied to the back-illuminated CMOS solid-state image sensor. However, the present invention can also be applied to other solid-state image sensors, for example, a back-illuminated CCD solid-state image sensor.

  FIG. 16 shows a fifth embodiment in which the present invention is applied to a semiconductor device, that is, a semiconductor integrated circuit device. The semiconductor integrated circuit device 71 according to the present embodiment serves as an element isolation region provided in the same manner as described above, or a termination detection unit different from the element isolation region, in this example, a termination detection unit 72 also serving as an element isolation region. Is used, and the surface of the silicon substrate 73 is thinned by polishing to a position where the bottom surface of the end detection unit 72 is exposed by a chemical mechanical polishing method, via a MOS transistor group Tr21 having a gate electrode 75 and an interlayer insulating film 76. A multilayer wiring layer 78 having a multilayer wiring 77 is formed, a support substrate 79 made of, for example, a silicon substrate is bonded to the multilayer wiring layer 78, and a MOS transistor group Tr22 having a gate electrode 81 on the back side of the silicon substrate 73. In addition, a multilayer wiring layer 84 in which a multilayer wiring 83 is disposed is formed through an interlayer insulating film 82. Reference numeral 85 denotes a passivation film.

  In the example of FIG. 16, the present invention is applied to a semiconductor integrated circuit device having a configuration in which MOS transistor groups Tr 21 and Tr 22 and multilayer wiring layers 78 and 84 are formed on both surfaces of the silicon substrate 73. The present invention can also be applied to various forms of semiconductor device integrated circuit devices such as forming a MOS transistor or other semiconductor element on the side and forming a wiring layer on the other side.

  Also in the semiconductor integrated circuit device and the manufacturing method thereof, it is not necessary to use an SOI substrate, the manufacturing process can be simplified, and the manufacturing cost can be greatly reduced. It has the same action and effect.

  21 .. Semiconductor substrate, 22.. Termination detection part that also serves as element isolation region, 23... Unit pixel region, 24... Source and drain region, 25, 26.・ Multi-layer wiring 31 ・ ・ Multi-layer wiring layer, PD ・ ・ Photodiode 35 ・ ・ Protective insulating film 36 ・ ・ Color filter 37 ・ ・ On-chip lens 38, 64 ・ ・ Back-illuminated CMOS solid Image sensor 62... Element isolation region 63.. Termination detector by columnar layer 63 A.. Sparse region of termination detector 63 B... Dense region of termination detector 71. ··· Termination detector, 73 ·· Semiconductor substrate, Tr21, Tr22 ·· MOS transistor, 75, 81 ·· Gate electrode, 76, 82 ·· Interlayer insulating film, 77, 83 ·· Multilayer wiring, 78, 84 ·・ Multilayer wiring layer , 85 ... Passivation membrane

Claims (18)

On the semiconductor substrate,
An imaging region in which pixels each including a photoelectric conversion element and a plurality of MOS transistors are arranged;
Peripheral circuits,
A columnar end detection unit having a hardness greater than that of the semiconductor substrate in the thickness direction from the surface of the semiconductor substrate and a material film having a higher hardness formed on the bottom surface in the thickness direction;
The semiconductor substrate is thinned to a position where the end detection unit is exposed by chemical mechanical polishing from the back surface,
A solid-state imaging device, wherein the MOS transistor is formed on a surface of the semiconductor substrate, and incident light is captured from a back surface of the semiconductor substrate. The solid-state imaging device according to claim 1, wherein the end detection unit is formed to also serve as an element isolation region. The solid-state imaging device according to claim 1, wherein the end detection unit is formed of a columnar layer different from the element isolation region. The solid-state imaging device according to claim 1, wherein a length in a depth direction of the end detection unit is a length corresponding to a thickness of a photoelectric conversion device that performs photoelectric conversion by light absorption. The solid-state imaging device according to claim 3, wherein an interval between the end detection portions by the columnar layer is set to an interval that does not cause thickness unevenness in chemical mechanical polishing. An imaging region in which pixels comprising a photoelectric conversion element and a plurality of MOS transistors existing on the surface of the semiconductor substrate are arranged on a semiconductor substrate, a peripheral circuit, and a hardness greater than that of the semiconductor substrate in the thickness direction from the surface of the semiconductor substrate And forming a columnar terminal end detection portion having a material film with higher hardness on the bottom surface in the thickness direction;
Bonding a support substrate to the surface side of the semiconductor substrate;
A step of chemically mechanically polishing the semiconductor substrate from a back surface to a position where the termination detection unit is exposed, and thinning the semiconductor substrate.
A method for manufacturing a solid-state imaging device, wherein the back surface of the semiconductor substrate is a surface that captures incident light. The method for manufacturing a solid-state imaging device according to claim 6, wherein the end detection unit is also used as an element isolation region. The method for manufacturing a solid-state imaging element according to claim 6, wherein the end detection unit is formed of a columnar layer different from the element isolation region. The method for manufacturing a solid-state imaging element according to claim 6, wherein the end detection unit is formed to have a length corresponding to a thickness of a photoelectric conversion element that performs photoelectric conversion by light absorption. The method for manufacturing a solid-state imaging device according to claim 8, wherein the end detection portions formed by the plurality of columnar layers are formed with an interval that does not cause thickness unevenness in chemical mechanical polishing. A semiconductor substrate;
A columnar terminal end detection unit in which a hardness is larger than that of the semiconductor substrate in the thickness direction from the surface of the semiconductor substrate and a material film having a higher hardness is formed on the bottom surface in the thickness direction;
A semiconductor device comprising: components of the semiconductor device formed on the front surface and the back surface of the semiconductor substrate that are thinned to a position where the termination detector is exposed by chemical mechanical polishing from the back surface. The semiconductor device according to claim 11, wherein the termination detection unit is formed also as an element isolation region. The semiconductor device according to claim 11, wherein the termination detection unit is formed of a columnar layer different from the element isolation region. The semiconductor device according to claim 13, wherein an interval between the etching stopper layers by the columnar layer is set to an interval that does not cause unevenness in thickness during the chemical mechanical polishing process. A step of forming a columnar terminal end detection unit having a material film having a hardness higher than that of the semiconductor substrate in the thickness direction from the surface and on the bottom surface of the thickness direction on the semiconductor substrate;
Forming a part of the components of the semiconductor device on the surface side of the semiconductor substrate;
Bonding a support substrate to the surface side of the semiconductor substrate;
A step of thinning the semiconductor substrate by chemical mechanical polishing from the back surface of the semiconductor substrate to a position where the termination detector is exposed;
Forming another part of the components of the semiconductor device on the back side of the semiconductor substrate. The method for manufacturing a semiconductor device according to claim 15, wherein the termination detection unit is also used as an element isolation region. The method of manufacturing a semiconductor device according to claim 15, wherein the termination detection unit is formed of a columnar layer different from the element isolation region. The method of manufacturing a semiconductor device according to claim 17, wherein the end detection portions formed by the plurality of columnar layers are formed with an interval that does not cause uneven thickness in chemical mechanical polishing.

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