JP5246304B2 - Method for manufacturing solid-state imaging device - Google Patents

Description

  The present invention relates to a method for manufacturing a backside illumination type solid-state imaging device.

Solid-state imaging devices are roughly classified into CCD (Charge Coupled Device) type solid-state imaging devices and CMOS (Complementary Metal Oxide Semiconductor) type solid-state imaging devices.
In these solid-state imaging devices, a light receiving portion made of a photodiode is formed for each pixel, and in the light receiving portion, signal charges are generated by photoelectric conversion by light incident on the light receiving portion. In the CCD type solid-state imaging device, the signal charge generated in the light receiving unit is transferred through a charge transfer unit having a CCD structure, converted into a pixel signal at the output unit, and output. On the other hand, in the CMOS type solid-state imaging device, the signal charge generated in the light receiving unit is amplified for each pixel, and the amplified signal is output as a pixel signal through a signal line.

  In such a solid-state imaging device, there is a problem that a false signal is generated in the semiconductor substrate due to oblique incident light or incident light diffusely reflected on the upper part of the light receiving unit, and optical noise such as smear and flare is generated.

  In the following Patent Document 1, in a CCD type solid-state imaging device, a light shielding film formed on the charge transfer unit is formed so as to be embedded in a groove formed at the interface between the light receiving unit and the readout gate unit. A configuration for suppressing the occurrence of smear is described. In Patent Document 1, since the light shielding film is formed in the groove portion formed using the LOCOS oxide film, it is difficult to form the light shielding film deep in the substrate, and oblique light that causes smearing is difficult. The incident cannot be completely blocked. In addition, since the pixel area is reduced in proportion to the depth of embedding the light shielding film, it is essentially difficult to embed the light shielding film deeply.

  In recent years, a backside illumination type solid-state imaging device that irradiates light from the side opposite to the side on which the wiring layer on the substrate is formed has been proposed (see Patent Document 2 below). In back-illuminated solid-state imaging devices, the wiring layer and circuit elements are not configured on the light irradiation side, so that the aperture ratio of the light receiving portion formed on the substrate can be increased, and incident light is reflected on the wiring layer, etc. Therefore, the sensitivity is improved.

  In such a back-illuminated solid-state imaging device as well, there is a concern about optical noise due to oblique light. Therefore, it is preferable to form a light-shielding film between the light-receiving portions on the back surface side of the substrate serving as the light irradiation side. In this case, it is conceivable to form one layer having a light-shielding film on the back side of the substrate on the light irradiation side, but the distance between the substrate and the on-chip lens surface is proportional to the height of the light-shielding film. Since it becomes longer, the light condensing characteristic may be deteriorated. When the light collecting characteristic is deteriorated, oblique light transmitted through the color filter of another pixel is incident on a light receiving portion of a pixel different from that pixel, causing problems such as color mixing and sensitivity reduction.

JP 2004-140152 A JP 2004-71931 A

  In view of the above, the present invention provides a method for manufacturing a backside illumination type solid-state imaging device in which light collection characteristics are improved and optical noise such as flare and smear is suppressed.

  In order to solve the above problems and achieve the object of the present invention, a manufacturing method of a solid-state imaging device according to the present invention first forms a plurality of light receiving portions and desired impurity regions in a surface region of a substrate, and etches in a back surface region. A stopper layer is formed, and then a wiring layer composed of a plurality of layers of wiring formed through an interlayer insulating film is formed on the surface side of the substrate. Next, the substrate is etched from the back side to the etching stopper layer. Next, a trench portion reaching a desired depth is formed from the back side of the substrate, a buried film is formed in the trench portion formed in the substrate, and the substrate is thinned using the buried film as a stopper. Next, after removing the buried film, a high dielectric constant material film is buried in the trench portion.

  In the method for manufacturing a solid-state imaging device according to the present invention, a light shielding portion formed by embedding a trench portion formed at a desired depth from the back surface side of the substrate with a light shielding film between a plurality of light receiving portions formed on the substrate. The solid-state imaging device separated by the above is formed. For this reason, when oblique light is incident from the back side of the substrate that is the light irradiation surface, the oblique incident light is blocked by the light shielding portion. Thereby, the incidence of oblique light on the light receiving part formed on the substrate is suppressed.

  According to the present invention, it is possible to obtain a solid-state imaging device in which flare characteristics and smear characteristics are improved and color mixing and blooming are suppressed. Further, by using the solid-state imaging device, an electronic apparatus with improved image quality can be obtained.

1 is a schematic configuration diagram showing an entire CMOS solid-state imaging device according to a first embodiment of the present invention. It is a section lineblock diagram in a pixel part of a solid imaging device concerning a 1st embodiment. A is a manufacturing process diagram of the solid-state imaging device according to the first embodiment. FIG. B is a manufacturing process diagram of the solid-state imaging device according to the first embodiment. FIG. C is a manufacturing process diagram of the solid-state imaging device according to the first embodiment. FIG. D is a manufacturing process diagram of the solid-state imaging device according to the first embodiment. FIG. E is a manufacturing process diagram of the solid-state imaging device according to the first embodiment. FIG. F is a manufacturing process diagram of the solid-state imaging device according to the first embodiment. FIG. G is a manufacturing process diagram of the solid-state imaging device according to the first embodiment. FIG. H is a manufacturing process diagram of the solid-state imaging device according to the first embodiment. FIG. I and J are manufacturing process diagrams of the solid-state imaging device according to the first embodiment. K and L are manufacturing process diagrams of the solid-state imaging device according to the first embodiment. It is a section lineblock diagram in a pixel part of a solid imaging device concerning a 2nd embodiment of the present invention. It is a schematic block diagram of the electronic device which concerns on the 3rd Embodiment of this invention.

Hereinafter, an example of a solid-state imaging device, a manufacturing method thereof, and an electronic apparatus according to an embodiment of the present invention will be described with reference to FIGS. Embodiments of the present invention will be described in the following order. In addition, this invention is not limited to the following examples.
1. First embodiment: Solid-state imaging device
1-1 Configuration of the whole solid-state imaging device 1-2 Configuration of main part 1-3 Manufacturing method of solid-state imaging device 2. Second embodiment: solid-state imaging device Third Embodiment: Electronic Device

<1. First Embodiment: Solid-State Imaging Device>
[1-1 Overall Configuration of Solid-State Imaging Device]
FIG. 1 is a schematic configuration diagram showing the entire CMOS solid-state imaging device according to the first embodiment of the present invention.
A solid-state imaging device 1 according to the present embodiment includes a pixel unit 3 including a plurality of pixels 2 arranged on a substrate 11 made of silicon, a vertical drive circuit 4, a column signal processing circuit 5, and a horizontal drive circuit. 6, an output circuit 7, a control circuit 8, and the like.

  The pixels 2 are composed of a light receiving portion made of a photodiode and a plurality of pixel transistors, and a plurality of pixels 2 are regularly arranged in a two-dimensional array on the substrate 11. The pixel transistor constituting the pixel 2 may be four MOS transistors constituted by a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor, or may be three transistors excluding the selection transistor.

  The pixel unit 3 is composed of pixels 2 regularly arranged in a two-dimensional array. The pixel unit 3 amplifies a signal charge actually received by light and amplifies a signal charge generated by photoelectric conversion and reads it to the column signal processing circuit 5 and a black for outputting an optical black serving as a black level reference. And a reference pixel region (not shown). The black reference pixel region is normally formed on the outer periphery of the effective pixel region.

  The control circuit 8 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock. To do. The clock signal and control signal generated by the control circuit 8 are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, and the like.

  The vertical drive circuit 4 is configured by, for example, a shift register, and selectively scans each pixel 2 of the pixel unit 3 in the vertical direction sequentially in units of rows. Then, the pixel signal based on the signal charge generated according to the amount of light received in the photodiode of each pixel 2 is supplied to the column signal processing circuit 5 through the vertical signal line.

  The column signal processing circuit 5 is arranged, for example, for each column of the pixels 2, and a signal output from the pixels 2 for one row is sent to the black reference pixel region (not shown, but around the effective pixel region) for each pixel column. Signal processing such as noise removal and signal amplification. A horizontal selection switch (not shown) is provided between the output stage of the column signal processing circuit 5 and the horizontal signal line 10.

  The horizontal drive circuit 6 is constituted by, for example, a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 5 in order, and the pixel signal is output from each of the column signal processing circuits 5 to the horizontal signal line. 10 to output.

  The output circuit 7 performs signal processing on signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 10 and outputs the signals.

[1-2 Configuration of main parts]
FIG. 2 is a cross-sectional configuration diagram of the pixel unit 3 of the solid-state imaging device 1 according to the present embodiment. The solid-state imaging device 1 of the present embodiment is an example of a back-illuminated CMOS solid-state imaging device.

  As shown in FIG. 2, the solid-state imaging device 1 according to the present embodiment is formed on the substrate 13, the wiring layer 26 formed on the front surface side of the substrate 13, the support substrate 14, and the back surface side of the substrate 13. The color filter layer 15 and the on-chip lens 16 are included.

  The substrate 13 is composed of a semiconductor substrate made of silicon, and is composed of, for example, a first conductivity type (in this embodiment, n-type) semiconductor substrate. The substrate 13 has a thickness of 3 μm to 5 μm, and the pixel formation region 12 of the substrate 13 includes a plurality of pixels 2 each including a light receiving portion PD and a plurality of pixel transistors Tr constituting the pixel circuit portion. It is formed in a two-dimensional matrix. Although not shown in FIG. 2, a peripheral circuit portion is configured in the peripheral region of the pixel 2 formed on the substrate 13.

The light receiving portion PD is composed of dark current suppression regions 22 and 23 formed in the pixel formation region 12 and a charge storage region 21 formed in a region between the dark current suppression regions 22 and 23. The dark current suppression region 23 is formed on the surface side of the substrate 13 (pixel formation region 12), and is configured by a second conductivity type (p-type in this embodiment) high-concentration impurity region. The dark current suppression region 22 is formed on the back side of the substrate 13 (pixel formation region 12), and is composed of a p-type impurity region. The charge storage region 21 is composed of an n-type impurity region. In the light receiving portion PD, a photodiode is mainly formed by a pn junction formed between a p-type impurity region constituting the dark current suppression regions 22 and 23 and an n-type impurity region constituting the charge storage region 21. It is configured.
In the light receiving unit PD, signal charges corresponding to the amount of incident light are generated and accumulated. In addition, electrons that cause dark current generated at the interface of the substrate are absorbed by holes that are majority carriers in the dark current suppression regions 22 and 23, thereby suppressing dark current.

  The pixel transistor Tr includes a source / drain region (not shown) formed on the surface side of the substrate 13 and a gate electrode 28 formed on the surface of the substrate 13 via a gate insulating film 29. As described above, the pixel transistor Tr may have a configuration including three pixel transistors Tr including a transfer transistor, a reset transistor, and an amplification transistor, or may have a configuration including four pixel transistors Tr including a selection transistor. . Although not shown, the source / drain regions are formed by n-type high-concentration impurity regions formed on the surface side of the substrate 13, and the pixel transistor Tr of this embodiment functions as an n-channel MOS transistor.

Further, an element isolation region 24 composed of a p-type high concentration impurity region is formed between the adjacent pixel 2 and the pixel 2 so as to extend from the front surface to the back surface of the substrate 13. Pixel 2 is electrically isolated. Further, in the element isolation region 24, a light shielding portion 17 formed at a desired depth from the back side of the substrate 13 is formed. The light shielding portion 17 is formed in, for example, a lattice shape so as to surround each pixel 2 in a plan view. The light shielding portion 17 includes a trench portion 19 having a desired depth formed on the back surface side of the substrate 13, a high dielectric constant material film 18 formed on the side wall and the bottom surface of the trench portion 19, and a high dielectric constant material film 18. And a light shielding film 20 embedded in the trench portion 19 via At this time, the outermost surface of the light shielding film 20 embedded in the trench portion 19 is configured to be flush with the back surface of the substrate 13. As a material of the high dielectric constant material film 18, for example, hafnium oxide (HfO ₂ ), tantalum pentoxide (Ta ₂ O ₅ ), or zirconium dioxide (ZrO ₂ ) can be used. Further, as the material of the light shielding film 20, for example, tungsten (W) or aluminum (Al) can be used.

  The wiring layer 26 is formed on the surface side of the substrate 13 and includes a wiring 25 laminated in a plurality of layers (three layers in this embodiment) via an interlayer insulating film 27. The pixel transistor Tr constituting the pixel 2 is driven via the wiring 25 formed in the wiring layer 26.

  The support substrate 14 is formed on the surface of the wiring layer 26 opposite to the side facing the substrate 13. The support substrate 14 is configured to ensure the strength of the substrate 13 at the manufacturing stage, and is configured of, for example, a silicon substrate.

  The color filter layer 15 is formed on the back side of the substrate 13, and for example, R (red), G (green), and B (blue) color filter layers are formed for each pixel. In the color filter layer 15, light having a desired wavelength is transmitted, and the transmitted light is incident on the light receiving part PD in the substrate 13.

  The on-chip lens 16 is formed on the surface of the color filter layer 15 opposite to the side facing the substrate 13. In the on-chip lens 16, the irradiated light is collected, and the collected light efficiently enters each light receiving part PD through the color filter layer 15.

  In the solid-state imaging device 1 having the above configuration, light is irradiated from the back side of the substrate 13, and the light transmitted through the on-chip lens 16 and the color filter layer 15 is photoelectrically converted by the light receiving unit PD, whereby signal charges are generated. Generated. The signal charges generated by the light receiving unit PD are output as pixel signals by the vertical signal line formed by the desired wiring 25 of the wiring layer 26 via the pixel transistor Tr formed on the surface side of the substrate 13. The

In the solid-state imaging device 1 of the present embodiment example, due to the element isolation region 24, electrons are not moved between adjacent pixels 2 due to the barrier formed by the potential of the element isolation region 24. In other words, the pixels are electrically separated by the concentration gradient of the impurity regions formed in the substrate 13.
Further, the light shielding portion 17 formed embedded in the element isolation region 24 prevents light incident obliquely on the light incident surface side from entering the adjacent pixel 2. That is, the pixels are optically separated by the light shielding portion 17.

  In addition, when the trench portion 19 is formed in the element isolation region 24, pinning may be lost in the peripheral portion of the trench portion 19 due to physical damage or impurity activation due to ion irradiation on the side wall and bottom surface of the trench portion 19. . With respect to this problem, in this embodiment, pinning failure is prevented by forming the high dielectric constant material film 18 having a large amount of fixed charges on the side wall and bottom surface of the trench portion 19.

  According to the solid-state imaging device 1 of the present embodiment example, since the light shielding unit 17 embedded in the element isolation region 24 is configured between adjacent pixels, oblique light incident on the light receiving surface is received by the light receiving unit. The incident on the PD can be prevented. As a result, light that is incident on the adjacent pixel 2 without being condensed by the on-chip lens is shielded, and optical color mixing that occurs between adjacent pixels is reduced. In addition, out of diffracted light and reflected light generated between the light receiving surface and the on-chip lens 16, light having a large angle incident on the adjacent pixel 2 is shielded, so that occurrence of flare is reduced.

  Furthermore, according to the solid-state imaging device 1 of the present embodiment example, the light shielding unit 17 is configured to be embedded in the element isolation region 24, so that the light receiving surface on the back surface of the substrate 13 becomes flat and the back surface of the substrate 13. The color filter layer 15 and the on-chip lens 16 formed on the side approach the light receiving surface. As a result, the distance between the surface of the on-chip lens 16 on which the light is incident and the light receiving surface of the substrate 13 are reduced, so that the light collection characteristics are improved and color mixing is reduced.

[1-3 Manufacturing method]
3 to 12 show manufacturing process diagrams of the solid-state imaging device 1 of the present embodiment example, and a manufacturing method of the solid-state imaging device 1 of the present embodiment example will be described.

  First, as shown in FIG. 3A, a plurality of pixels 2 each including a light receiving portion PD and a pixel transistor Tr are formed on a substrate 13, and a plurality of layers formed on the surface side of the substrate 13 via an interlayer insulating film 27. A wiring layer 26 made of the wiring 25 is formed. The pixel 2 and the wiring layer 26 can be formed by the same method as that for the normal solid-state imaging device 1.

In the present embodiment, for example, a substrate 13 having a pixel forming region 12 to be an n-type surface region having a thickness of 3 μm to 5 μm and having a back surface region 30 below the pixel forming region 12 is prepared. A desired impurity is ion-implanted from the surface side of the substrate 13 at a desired concentration to form a light receiving portion PD, an element isolation region 24, and source / drain regions (not shown) in the pixel formation region 12. Then, after forming a gate insulating film 29 made of, for example, a silicon oxide film on the surface of the substrate 13, a gate electrode 28 made of, for example, polysilicon is formed in a desired region above the gate insulating film 29. The formation process of the gate electrode 28 may be performed before the formation process of the light receiving portion PD, the source / drain region, and the like in the pixel formation region 12. In this case, the light receiving portion PD and the source / drain region are connected to the gate electrode. It can be formed by self-alignment using 28 as a mask. In addition, a sidewall made of, for example, a silicon oxide film or a silicon nitride film may be formed on the side surface of the gate electrode 28.
The wiring layer 26 is formed by repeatedly forming the interlayer insulating film 27 made of, for example, a silicon oxide film and the wiring 25 made of aluminum, copper, or the like a desired number of times after the gate electrode 28 is formed. be able to. At this time, although not shown, a contact portion for connecting the wirings is also formed.
The back surface region 30 has a structure in which a non-doped silicon layer 30a, an etching stopper layer 30b made of a p-type high concentration impurity layer, and a non-doped silicon layer 30a are stacked in this order from the pixel forming region 12 side. This etching stopper layer 30b can be formed by ion-implanting boron at a high concentration in a desired region of the non-doped silicon layer 30a. Alternatively, a method may be used in which the non-doped silicon layer 30a is formed by an epitaxial growth method, and a p-type high-concentration impurity layer is formed in a desired region in the formation process. In the back surface region 30 of this embodiment, the silicon layer 30a on the side in contact with the substrate 13 is about 2 μm to 5 μm, the etching stopper layer 30b is about 1 μm, and the silicon layer 30a formed on the etching stopper layer 30b is about 1 μm. It is comprised so that.

  Next, as shown in FIG. 4B, the support substrate 14 is bonded to the upper portion of the wiring layer 26 by physical adhesion using an organic adhesive or plasma irradiation.

  Then, as shown in FIG. 5C, after attaching the support substrate 14, the element is inverted, and the upper surface of the back surface region 30 is polished by a physical polishing method. At this time, polishing is performed to such an extent that it does not reach the etching stopper layer 30b.

  Next, the silicon layer 30a in the back surface region 30 is etched by wet etching using hydrofluoric acid. Then, as shown in FIG. 6D, etching stops at the etching stopper layer 30b due to the difference in doping species between the non-doped silicon layer 30a and the etching stopper layer 30b made of the p-type high concentration impurity layer. That is, only the silicon layer 30a formed on the upper surface side of the back surface region 30 is removed by etching.

  Next, as shown in FIG. 7E, a photoresist layer 31 is formed on the back surface region 30, and exposure and development are performed so that an opening 31a is formed in a region where the light shielding portion 17 of the element isolation region 24 is formed. . In this case, since the back surface region 30 is etched away to the etching stopper layer 30b in the previous step, the surface is flat. For this reason, since the photoresist layer 31 is also formed to have a flat surface, the exposure and development of the photoresist layer 31 are performed with high accuracy, and the desired opening 31a can be patterned more accurately.

  Next, dry etching is performed using the photoresist layer 31 patterned into a desired shape as a mask, thereby penetrating the back surface region 30 to a desired depth from the back surface side of the pixel formation region 12 as shown in FIG. 8F. A trench portion 19 is formed. As described above, the depth of the trench portion 19 may be formed to such a depth that oblique light incident from the back surface side of the substrate 13 can be shielded by the light receiving surface side. The trench portion 19 is formed from the back surface to a depth of, for example, 500 nm to 1000 nm.

Next, as shown in FIG. 9G, a buried film 32 made of a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN) is formed by using, for example, a CVD method so as to fill the trench portion 19.

  Next, as shown in FIG. 10H, the buried film 32 is etched back by etching for a predetermined time by wet etching. At this time, the etch back is completed in a state where the surface of the buried film 32 protrudes from the back surface of the substrate 13 by about 50 to 60 nm.

  Next, using the buried film 32 as a stopper, the back surface region 30 is polished by a CMP method, and the back surface region 30 is thinned. Thereby, as shown in FIG. 11I, the back surface region 30 is removed.

Next, as shown in FIG. 11J, the buried film 32 embedded in the trench portion 19 is removed by wet etching, and the damage layer generated in the polishing process and the trench portion 19 forming process in the previous step is removed. To do. As the chemical solution for removing the buried film 32, boiling acid is preferably used when the buried film 32 is SiO ₂ , and phosphoric acid is preferably used when SiN is used. For removing the damaged layer, it is preferable to use an alkaline chemical solution such as ammonia water.

  Next, as shown in FIG. 12K, a high dielectric constant material film 18 is formed on the back surface of the substrate 13 including the side wall and bottom surface of the trench portion 19 by using a CVD method or a sputtering method. Subsequently, a light shielding film 20 is formed on the entire surface including the trench portion 19 on which the high dielectric constant material film 18 is formed using the CVD method, and the light shielding film 20 is embedded inside the trench portion 19.

  Next, as shown in FIG. 12L, the height of the light shielding film 20 is adjusted by wet etching with an acid chemical solution such as hydrochloric acid or sulfuric acid. At this time, the height of the light shielding film 20 is adjusted so that the surface of the light shielding film 20 and the back surface of the substrate 13 are flush with each other.

  Thereafter, the color filter layer 15 and the on-chip lens 16 are formed on the back surface side of the substrate 13 by using a normal method, and the solid-state imaging device 1 of this embodiment shown in FIG. 2 is completed.

  As described above, the solid-state imaging device 1 according to this embodiment can be formed using a bulk substrate. In a normal back-illuminated solid-state imaging device, an SOI (Silicon On Insulator) substrate is used. However, in this embodiment, since it can be formed by a bulk substrate having a lower cost than an SOI substrate, an expensive SOI substrate is used. Therefore, the cost can be reduced.

  Further, in the solid-state imaging device 1 of the present embodiment example, the substrate 13 having the back surface region 30 in which the etching stopper layer 30b made of a p-type high concentration impurity layer is formed on the non-doped silicon layer 30a is used. However, the present invention is not limited to this, and other substrates having various etching stopper layers can be used. For example, a SiC or SiGe layer may be used as the etching stopper layer 30b.

  Further, in the method for manufacturing the solid-state imaging device 1 according to the present embodiment, the buried film 32 used as a stopper in the process of FIG. 9H can be formed in the trench portion 19, and the back surface region 30 in the process of FIG. Becomes easier. Since the back surface region 30 can be easily thinned, the p-type high concentration impurity layer formed in the back surface region 30 can be formed at a distance from the light receiving portion PD formed on the substrate 13 to some extent. Therefore, it is possible to suppress the modulation of the carrier profile of the light receiving portion PD in the pixel formation region 12 due to heat in the diffusion process of the p-type high concentration impurity layer that is the etching stopper layer 30b.

  In the method for manufacturing the solid-state imaging device 1 according to the present embodiment, the element isolation region 24 formed on the substrate 13 is formed by ion implantation of p-type impurities from the surface side of the substrate 13. For this reason, it is difficult to form a steep potential profile in the pixel formation region 12 located deep from the front surface side (in this case, the back surface side of the substrate 13). Then, on the back surface side of the substrate 13, the generated signal charge may pass through the element isolation region 24 and leak into the adjacent pixels 2, which causes color mixing and blooming. In this embodiment, the light shielding portion 17 is embedded in the element isolation region 24 on the back side of the substrate 13. For this reason, in a region where the element isolation function of the element isolation region 24 is particularly weak, signal charges leaking into adjacent pixels can be physically blocked, and color mixing and blooming due to movement of signal charges in the substrate 13 are suppressed. .

<2. Second Embodiment: Solid-State Imaging Device>
Next, a solid-state imaging device according to the second embodiment of the present invention will be described. The solid-state imaging device according to the present embodiment is a back-illuminated solid-state imaging device like the solid-state imaging device according to the first embodiment, and the overall configuration is the same as in FIG. .

  FIG. 13 is a schematic cross-sectional configuration diagram of a main part of the solid-state imaging device 40 in the present embodiment. In FIG. 13, parts corresponding to those in FIG.

  As shown in FIG. 13, in the solid-state imaging device 40 of the present embodiment example, the light shielding part 47 is an example formed so as to penetrate the pixel formation region 12 in which the light receiving part PD is formed. In the present embodiment example shown in FIG. 13, the light shielding part 47 is formed to a depth reaching the wiring 25 on the lowermost layer (substrate 13 side) of the wiring layer 26, but at a depth reaching the wiring layer 26. If so, various configurations are possible.

  In the manufacturing method of the solid-state imaging device 40 according to the present embodiment, the wiring 25 that penetrates the substrate 13 and is closest to the substrate 13 among the wirings in the wiring layer 26 in the process of FIG. 8F shown in the first embodiment. A trench portion 49 having a depth that can be reached is formed. Thereafter, the light shielding portion 47 can be formed by embedding the high dielectric constant material film 48 and the light shielding film 50 in the trench portion 49 in the same manner as the solid-state imaging device 1 of the first embodiment. As a material constituting the solid-state imaging device 40 of the present embodiment, the same material as that of the first embodiment can be used.

  In the solid-state imaging device 40 of the present embodiment example, the light shielding part 47 is formed to a depth reaching the wiring layer 26, so that each pixel 2 formed on the substrate 13 can be shielded even at a deep position from the light incident surface. 47. Thereby, it becomes possible to further suppress the incidence of oblique light on the adjacent pixels 2, and flare generation and color mixing can be reduced. In addition, since each pixel 2 is separated by the light-shielding portion 47 inside the substrate 13, blooming caused by excessive generated signal charges entering adjacent pixels when irradiated with intense light. Can also be suppressed.

  Furthermore, according to the solid-state imaging device 40 of the present embodiment example, the light shielding portion 47 that penetrates the substrate 13 on which the light receiving portion PD is formed can also be used as a waveguide. That is, the incident light is reflected by the waveguide, so that the incident light can be collected by the light receiving part PD in the substrate 13 and the light collection characteristics are improved.

  In addition, the same effects as those of the first embodiment can be obtained.

  In the first and second embodiments described above, the case where the present invention is applied to a CMOS type solid-state imaging device in which unit pixels that detect signal charges corresponding to the amount of incident light as physical quantities are arranged in a matrix has been described as an example. . However, the present invention is not limited to application to a CMOS type solid-state imaging device. Further, the present invention is not limited to a column type solid-state imaging device in which column circuits are arranged for each pixel column of a pixel portion in which pixels are formed in a two-dimensional matrix.

  For example, the solid-state imaging device of the present invention can also be applied to a CCD type solid-state imaging device. In this case, a charge transfer section having a CCD structure is formed on the surface side of the substrate. When applied to a CCD type solid-state imaging device, the same effects as those of the first and second embodiments described above can be obtained, and the oblique light is incident on the charge transfer unit by the configuration of the light shielding unit. Since it can suppress, generation | occurrence | production of a smear can be suppressed.

  In the first and second embodiments described above, each pixel mainly has an n-channel MOS transistor configuration, but can also have a p-channel MOS transistor configuration. In this case, the conductivity type is reversed in each figure.

  The present invention is not limited to application to a solid-state imaging device that senses the distribution of the amount of incident light of visible light and captures it as an image, but is a solid that captures the distribution of the incident amount of infrared rays, X-rays, or particles as an image. The present invention can also be applied to an imaging device. In a broad sense, the present invention can be applied to all solid-state imaging devices (physical quantity distribution detection devices) such as a fingerprint detection sensor that senses other physical quantity distributions such as pressure and capacitance and captures images as images.

Furthermore, the present invention is not limited to the solid-state imaging device that sequentially scans each unit pixel of the pixel unit in units of rows and reads a pixel signal from each unit pixel. The present invention is also applicable to an XY address type solid-state imaging device that selects an arbitrary pixel in pixel units and reads out signals from the selected pixels in pixel units.
Note that the solid-state imaging device may be formed as a single chip, or may be in a modular form having an imaging function in which a pixel portion and a signal processing portion or an optical system are packaged together. Good.

  In addition, the present invention is not limited to application to a solid-state imaging device, but can also be applied to an imaging device. Here, the imaging apparatus refers to a camera system such as a digital still camera or a video camera, or an electronic device having an imaging function such as a mobile phone. Note that the above-described module form mounted on an electronic device, that is, a camera module may be used as an imaging device.

<3. Third Embodiment: Electronic Device>
Next, an electronic apparatus according to a third embodiment of the present invention will be described. FIG. 14 is a schematic configuration diagram of an electronic device 200 according to the third embodiment of the present invention.
The electronic device 200 according to the present embodiment is an example of the solid-state imaging device 1 according to the first embodiment of the present invention described above as an example of a digital camera capable of taking a still image.

  The electronic apparatus 200 according to the present embodiment includes the solid-state imaging device 1, an optical lens 210, a shutter device 211, a drive circuit 212, and a signal processing circuit 213.

The optical lens 210 forms image light (incident light) from the subject on the imaging surface of the solid-state imaging device 1. As a result, the signal charge is accumulated in the solid-state imaging device 1 for a certain period.
The shutter device 211 controls a light irradiation period and a light shielding period for the solid-state imaging device 1.
The drive circuit 212 supplies drive signals that control the transfer operation of the solid-state imaging device 1 and the shutter operation of the shutter device 211. Signal transfer of the solid-state imaging device 1 is performed by a drive signal (timing signal) supplied from the drive circuit 212. The signal processing circuit 213 performs various signal processing. The video signal subjected to the signal processing is stored in a storage medium such as a memory or output to a monitor.

  In the electronic apparatus 200 according to the present embodiment, the occurrence of flare, color mixing, and blooming is suppressed in the solid-state imaging device 1, so that the image quality can be improved.

  Thus, the electronic device 200 to which the solid-state imaging device 1 can be applied is not limited to a camera, but can be applied to an imaging device such as a digital still camera and a camera module for mobile devices such as a mobile phone.

  In the present embodiment example, the solid-state imaging device 1 is configured to be used in an electronic apparatus, but the solid-state imaging device in the second embodiment described above can also be used.

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device, 2 ... Pixel, 3 ... Pixel part, 4 ... Vertical drive circuit, 5 ... Column signal processing circuit, 6 ... Horizontal drive circuit, 7 ... Output circuit 8... Control times 10... Horizontal signal line 12... Pixel formation region 13... Substrate 14. Support substrate 15. On-chip lens, 17 ... light shielding part, 18 ... high dielectric constant material film, 19 ... trench part, 20 ... light shielding film, 21 ... charge storage region, 22 ... dark current suppression Region 23 ... dark current suppression region 24 ... element isolation region 25 ... wiring 26 ... wiring layer 27 ... interlayer insulating film 28 ... gate electrode 29 ... -Gate insulating film, 30 ... back surface region, 30a ... silicon layer, 30b ... etching stopper layer, 31 ... phosphor Resist layer, 31a ... opening 32 ... filling layer

Claims (7)

Forming a plurality of light receiving portions and desired impurity regions in the front surface region of the substrate, and forming an etching stopper layer in the back surface region;
Forming a wiring layer composed of a plurality of wiring layers formed via an interlayer insulating film on the surface side of the substrate;
Etching the substrate from the back side of the substrate to the etching stopper layer;
Forming a trench portion reaching a desired depth from the back side of the substrate;
Forming a buried film in a trench portion formed in the substrate, and using the buried film as a stopper to thin the substrate;
Removing the buried film and then embedding a light shielding film in the trench portion;
A method for manufacturing a solid-state imaging device. The method for manufacturing a solid-state imaging device according to claim 1, wherein a back surface region of the substrate is configured by a non-doped silicon layer, and the etching stopper layer is configured by a p-type high concentration impurity layer. The method for manufacturing a solid-state imaging device according to claim 1, wherein the embedded film is formed of a silicon oxide film or a silicon nitride film. The method for manufacturing a solid-state imaging device according to claim 1, wherein the trench portion is formed so as to penetrate the substrate. The method for manufacturing a solid-state imaging device according to claim 3, wherein a high dielectric constant material film is formed between the trench part and the light shielding film embedded in the trench part. The method for manufacturing a solid-state imaging device according to claim 3, wherein the light shielding film is made of aluminum or tungsten. The method for manufacturing a solid-state imaging device according to claim 3, wherein the high dielectric constant material film is made of hafnium oxide, tantalum pentoxide, or zirconium dioxide.

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