JP2001053257A - Formation of laminated soi substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a forming method of a laminated SOI substrate, which first suppresses irregularities in the depth directions of recessed parts, which are formed in a first silicon substrate (substrate to be polished) and are used as reference planes for polishing a buried oxide film, to form the laminated SOI substrate, which is formed by a selective polishing method to use the buried oxide film as a polishing stopper and has a SOI layer, which is excellent in the uniformity of its film thickness. SOLUTION: The forming method of a laminated SOI substrate has a process to form recessed parts in the prescribed regions on a first silicon substrate 101, a process to form an insulating film in such a way as to fill at least the recessed parts, a process to laminate together the recessed part formation surfaces of the substrate 101 with a second silicon substrate, a process to grind the surface on the opposite side to the laminated surface of the substrate 101 with the second silicon substrate and a process to selectively polish the ground surface and moreover, the forming method has a process to introduce impurities to change the etching rate of a silicon film in the regions, which are formed with the recessed parts, prior to the formation of the recessed parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bonded SOI
More particularly, the present invention relates to an SOI substrate manufactured by bonding two wafers, followed by grinding of one wafer and selective polishing using a polishing stopper, wherein the SOI film has improved uniformity in SOI film thickness. SO
The present invention relates to a method for manufacturing an I substrate.

[0002]

2. Description of the Related Art In recent semiconductor devices, SO
By using an I (Silicon on Insulator) substrate, complete isolation between elements is facilitated, and a soft error or CMOS (Complete) is used.
nary Metal-Oxide-Semicon
It is becoming possible to suppress latch-up peculiar to a transistor. And from relatively early 5
Using an SOI structure having a silicon active layer (SOI layer) having a thickness of about 00 nm, studies have been made on high speed and high reliability of an LSI having a CMOS transistor.

Recently, the SOI layer on the surface of the SOI substrate is further thinned to about 100 nm, and the impurity concentration of the channel is controlled to be relatively low. Then, it has been found that more excellent performance such as suppression of the short channel effect and improvement of the current driving capability of the MOS transistor can be obtained.

A typical SOI substrate forming method is SIMOX (Separation by Immo).
2. Description of the Related Art Two methods, a planted oxygen method and a wafer bonding method, are known.

However, these methods each have advantages and disadvantages at present. For example, the SIMOX method is excellent in the uniformity of the thickness of the SOI layer, but has poor flatness at the interface with the buried oxide film, and has a problem in transistor reliability and the like.

On the other hand, SOI by wafer bonding method
The substrate has good characteristics of the buried oxide film of the SOI layer, but has a problem in the uniformity of the thickness of the SOI layer as described later.

Conventionally, an SOI substrate manufactured by such a wafer bonding method has been manufactured as follows. Hereinafter, the conventional method will be briefly described with reference to the drawings.

First, as shown in FIG. 10A, a thermal oxide film 302 having a thickness of about 10 nm is formed on an n-type silicon semiconductor substrate 301, for example.

Next, as shown in FIG. 10B, a resist pattern 303 for forming a concave portion of a first silicon substrate 301 such as an n-type silicon semiconductor substrate is formed. Further, using the resist pattern 303 as a mask, the first silicon substrate 301 is etched by a dry etching method, and the resist pattern 303 and the thermal oxide film 302 are removed to obtain a state shown in FIG. .

In the above process, the depth of the concave portion formed in the first silicon substrate 301 (in the direction perpendicular to the substrate surface) becomes the final thickness of the SOI layer. Further, the concave portions are formed by a dry etching method, and the accuracy of the dry etching has an in-plane variation in the vertical direction of the substrate surface of about ± 3%.

Next, the concave portion of the silicon substrate 301 is covered with a buried oxide film 305, and a polysilicon film 306 is further deposited thereon. Then, the surface of the polysilicon film 306 is removed by CMP (Chemical Mechanical).
1 Polishing), and flattened.
The structure shown in FIG. 1 (d) is obtained.

Next, as shown in FIG.
The surface of the polysilicon film 306 of the silicon substrate 301 of FIG.
The second silicon substrate 307 is bonded to the substrate and further subjected to a heat treatment (in an oxygen atmosphere,
(1000 ° C., about 30 minutes).

Further, the back surface (the surface opposite to the bonding surface) of the first silicon substrate 301 is ground, and further, PACE (Plasma Assisted Ch) is performed.
11 (f) by performing a chemical etching process and finally performing a selective polishing process.
An OI substrate can be manufactured.

In both the grinding step and the selective polishing step, processing is performed using the back surface of the wafer as a reference surface. Further, as described above, recently, after grinding, a so-called PACE (P
lasma Assisted Chemical Et
(Ching) processing to make the silicon film thickness before the selective polishing uniform so that the silicon oxide in the field portion can be exposed over the entire surface of the wafer with a smaller amount of over-polishing. According to this method, a bonded SOI substrate having excellent film thickness uniformity can be manufactured by suppressing so-called dishing.

According to the method for manufacturing a bonded SOI substrate described above, not only can the buried oxide film thickness and the like be set relatively freely, but also elements and wirings can be prepared before bonding the substrate to be polished. By doing so, an LSI can be manufactured by embedding them in the SOI substrate, so that an LSI with a higher degree of integration can be manufactured.

[0016]

However, the SOI substrate manufactured by this wafer bonding method has good characteristics of the buried oxide film. There is a problem.

In a bonded SOI substrate by selective polishing using a polishing stopper film, factors that deteriorate the thickness uniformity (in-plane uniformity) in the depth direction of the SOI film are roughly classified into (1) There are two in-plane uniformity of a silicon step (recess) formed first on one silicon substrate (substrate to be polished), and (2) precision and in-plane uniformity of selective polishing.

The factor (2) relates to how to stop polishing at the reference surface of silicon oxide serving as a polishing stopper.
It is necessary to improve the uniformity of polishing including ing.

In the conventional laminating method, the factor of the above factor (2) is large as the cause of the in-plane variation of the SOI film thickness, and the in-plane uniformity of the selective polishing is improved and the selective polishing is not performed. Consideration has been mainly focused on improving the ratio (that is, polishing silicon in the field portion faster than silicon in the concave portion in the active portion).

However, since it is possible to make the silicon film uniform and thin before the selective polishing by using the PACE processing, the influence of the finished (2) on the variation in the SOI film thickness is relatively small. On the contrary, the influence of the in-plane variation in the depth direction of the silicon step (recess) of (1) is increasing.

For example, at the time of grinding, in order to make the influence of crystal defects formed in the silicon active layer (SOI layer) negligible, the substrate to be polished is thinned by grinding from the back side thereof. Requires that the grinding be performed so that at least about 4 μm or more of silicon remains over the entire area of the wafer. Since this grinding is performed with mechanical precision based on the back surface of the second silicon substrate (support substrate), the in-plane variation of the silicon film thickness after grinding is the variation in the thickness of the support substrate (TTV: Total). Thickness Vari
It is not possible to make it less than the degree.

In the current 200 mmφ wafer, TTV
Even when a double-side polished wafer with a small
Is about 1.0 μm, and the variation in the thickness of the remaining silicon after grinding must be at least about 1.0 μm. Assuming that the uniformity of the selective polishing is about 10% and considering the worst case, at least about 10% of overpolishing must be performed on a portion (about 5 μm) where silicon is thickest before selective polishing. Therefore, in the portion where the silicon is thickest before the selective polishing, the polishing is just Polish even if the polishing progresses the slowest in the plane. Over-polishing (5.5
μm polishing × distribution in polished surface 10% -4 μm).

Assuming that the selective ratio of the selective polishing is about 50, the resulting SOI film thickness distribution is 2 μm.
/ 50 to 40 nm. This 40nm (± 20nm)
In the case of a fully depleted SOI transistor, the SOI film thickness distribution of S
This corresponds to the OI film thickness distribution.

That is, in the conventional device of the 0.35 μm rule, the depth of the recess formed in the first silicon substrate (this is the SOI film thickness after selective polishing) is 0.1 μm, When this step was formed, the in-plane variation (6 nm) of about 6% (± 3%) could be achieved, so that the influence of the silicon step distribution was relatively small.

However, in the recent device of the 0.18 μm rule, the silicon step has a depth of about 50 nm, which is half the depth, and the absolute value of the in-plane distribution (variation) even when the dry etching uniformity is about the same (6%) Was 3 nm.

On the other hand, by making uniform the variation of the silicon film thickness after grinding by PACE processing, the silicon film thickness distribution before selective polishing can be made about 200 ± 50 nm. Even when 100% overpolishing is performed with respect to the average value of the silicon film thickness, the variation in the SOI film thickness obtained by the selective polishing is about 4 nm, which is about the same as the in-plane uniformity of the silicon step (recess). Will be.

That is, as shown in FIG.
When the concave portion is formed in the silicon substrate 301, the concave portion having the depth (D, E) variation is formed due to the in-plane variation of the dry etching (variation of the etching in the depth direction). Is directly reflected in the variation of the film thickness (F, G) of the finally formed SOI layer (308 in FIG. 11F).

Therefore, in the present and future semiconductor devices having a rule of 0.18 μm or less, the SOI film thickness uniformity is further improved by improving the in-plane uniformity of PACE processing and selective polishing and the selective ratio of selective polishing. At the same time, it is important to improve the in-plane uniformity of the concave portion formed first on the first silicon substrate.

In a future LSI with further miniaturization, the SOI film thickness of an SOI substrate to be used is becoming increasingly thinner, and the demand for uniformity of the film thickness is becoming more severe. Therefore, even in an SOI substrate manufactured by the bonding method, S
In order to manufacture an OI substrate, there is a need to develop a technique for forming a concave portion with improved in-plane uniformity.

The present invention has been made in view of such a situation. In a bonded SOI substrate manufactured by selective polishing using a buried oxide film as a polishing stopper, the bonded SOI substrate is first formed on a first silicon substrate (substrate to be polished). It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer having excellent film thickness uniformity by suppressing variation in the depth direction of a concave portion serving as a polishing reference surface.

[0031]

In general, it is known that the etching rate (particularly, wet etching) of silicon varies depending on the type and concentration of impurities contained in silicon or the difference in crystal defect density in silicon crystals. ing. Then, when etching silicon, by appropriately selecting an etching solution or an etching method that causes such a difference in the etching rate,
It is possible to selectively and accurately etch a predetermined region of silicon.

In the case where silicon is simply chemically etched, in-plane uniformity of etching (here, “in-plane uniformity of etching” refers to uniformity of a step shape obtained by etching (particularly in a depth direction). ))
Is more difficult to improve than when dry etching is used.

However, it is impossible to form an impurity introduction layer having excellent in-plane uniformity in a predetermined region of a silicon substrate by accurately introducing a predetermined impurity into a predetermined region of the silicon substrate at a predetermined concentration. Relatively easy.

The present inventor has formed an impurity-introduced layer having excellent in-plane uniformity in a predetermined region of a silicon substrate, and based on the type of impurity, impurity concentration, crystal defect density, etc. It has been found that by appropriately selecting an etching condition that causes a difference, a concave portion (silicon step) having excellent in-plane uniformity can be formed as compared with the case where the conventional dry etching is performed, and the present invention is completed. Reached.

That is, the present invention provides a step of forming a concave portion in a predetermined region of a first silicon substrate, a step of forming an insulating film so as to fill at least the concave portion, and a step of forming the concave portion of the first silicon substrate. A bonded SOI substrate having a step of bonding a surface to a second silicon substrate, a step of grinding a surface of the first silicon substrate opposite to the bonded surface, and a step of selectively polishing the ground surface Prior to the formation of the recess, a step of introducing an impurity that changes the etching rate of silicon into a region where the recess is formed.
A method for manufacturing a substrate is provided.

In the present invention, the “surface on which the concave portion is formed on the first silicon substrate” means a surface on the side where the concave portion is formed on the first silicon substrate. That is, the present invention provides an insulating film surface having a flat surface formed on the concave portion of the first silicon substrate, or a planarized film surface having a flat surface formed on the insulating film; This is a method of manufacturing an SOI substrate by bonding one surface of the SOI substrate.

In the present invention, the step of introducing an impurity that changes the etching rate of silicon into the region where the concave portion is formed is performed by implanting the impurity that changes the etching speed of silicon into the region where the concave portion is formed by ion implantation. It is preferable to have a step of introducing.

Further, the step of introducing an impurity that changes the etching rate of silicon into the region where the concave portion is formed includes a step of introducing an impurity that changes the crystal defect density of silicon into the region where the concave portion is formed. Is preferred.

Further, the step of introducing an impurity which changes the etching rate of silicon into the region where the concave portion is to be formed is performed by adding phosphorus, boron, arsenic,
More preferably, the method includes a step of introducing silicon or a compound thereof, and more preferably, a step of introducing these substances by ion implantation.

In the step of forming a concave portion in a predetermined region of the first silicon substrate, the step of forming the concave portion may be performed under a condition that an etching rate changes according to a type of impurity contained in the silicon substrate or a concentration of the impurity. Preferably, the method includes a step of etching a predetermined region of the one silicon substrate.

The step of forming a concave portion in a predetermined region of the first silicon substrate is performed under the condition that the etching rate changes according to the type of impurity contained in the silicon substrate or the concentration of the impurity. The method preferably includes a step of etching a predetermined area of the silicon substrate by a wet etching method, and more preferably includes a step of HF anodic etching of the predetermined area of the first silicon substrate.

The step of forming a concave portion in a predetermined region of the first silicon substrate is particularly preferably performed according to the type of impurity contained in the silicon substrate or the concentration of the impurity.
A step of etching a predetermined region of the first silicon substrate using an etching solution containing acetic acid, potassium hydroxide, ethylenediamine or hydrazine.

Preferably, the step of selectively polishing the ground surface includes the step of selectively polishing the ground surface using the insulating film as a polishing stopper.

Further, in the present invention, a flat surface is formed on the insulating film between the step of forming the insulating film and the step of bonding the concave portion forming surface of the first silicon substrate to a second silicon substrate. It is preferable that the method further includes a step of forming an oxide film. In this case, it is more preferable that the step of forming the planarizing film on the insulating film includes the step of forming a polysilicon film having a flat surface on the insulating film.

Further, in the present invention, between the step of grinding the surface of the first silicon substrate opposite to the surface to be bonded and the step of selectively polishing the ground surface, the ground surface may be PACE (Plasma). Assisted C
More preferably, the method further includes a step of performing a chemical etching process.

According to the present invention, an impurity introduction layer having excellent in-plane uniformity (sometimes referred to as a “crystal defect introduction layer”) is first formed in a region of the first silicon substrate where a concave portion is to be formed. Then, by selectively etching the impurity-introduced layer (crystal defect-introduced layer) with high selectivity, it is possible to form a concave portion having better in-plane uniformity than in the case of the conventional dry etching method. It is possible to manufacture an SOI substrate having an SOI layer with further improved performance.

In the present invention, when impurities are introduced by ion implantation, the implantation energy and implantation dose of the impurities can be precisely controlled, so that the impurity-introduced layer with extremely excellent in-plane uniformity can be obtained. (A crystal defect introduction layer) can be formed.

Further, in the present invention, when impurities are introduced by the ion implantation method, the in-plane uniformity of the impurity-introduced layer is determined by the accuracy of the ion implantation. It can be particularly preferably applied in this case.

[0049]

Next, embodiments of the present invention will be described with reference to the drawings. The following is merely an embodiment of the present invention, and the types of the first and second substrates, heat treatment conditions after bonding, selective polishing conditions, and the like are appropriately set without departing from the spirit of the present invention. Can be selected and changed. In the following description of the present embodiment, the “active portion” refers to a surface portion region of the first silicon substrate on which an SOI layer is finally formed, and the “field portion”
It refers to the surface region of the first silicon substrate other than the active region.

First Embodiment In a first embodiment , an impurity is implanted only into a region of a first silicon substrate where a concave portion is to be formed, the impurity is activated, and then the impurity is activated in accordance with the type and concentration of the impurity. This is a method for manufacturing an SOI substrate in which a step having excellent in-plane uniformity is formed by selectively etching only an impurity-implanted region using a method in which the etching rate of silicon is increased.

First, as shown in FIG. 1A, a thermal oxide film 102 having a thickness of about 10 nm is formed on a first silicon substrate 101 by, for example, a thermal oxidation method. The thermal oxide film 102 prevents contaminants such as metal from entering from a resist mask or the like into a region that will ultimately become an SOI layer in the next step, and is used to implant ions into a field portion. It also has the function of suppressing channeling. Although a thermal oxide film is formed in the present embodiment, any film other than the thermal oxide film can be formed as long as the film has such a function.

As the first silicon substrate, for example, n
Or a p-type substrate having a low impurity concentration can be used. In this embodiment, the silicon substrate 101 containing boron as a p-type impurity having a concentration of about 1 × 10 ¹⁵ / cm ³ is used.
(The resistivity is about 20 Ω · cm.).

Next, as shown in FIG. 1B, a resist pattern 103 for element isolation is formed.

Next, as shown in FIG. 1C, P ⁺ ions are selectively implanted into the field portion using the resist pattern 103 as a mask. The ion implantation at this time is performed, for example, at an acceleration voltage of 20 keV (Rp = ｐ25 nm) and a dose of 1 × 10 ¹⁴ atoms / cm ² (surface concentration = 〜2
× 10 ¹⁹ atoms / cm ³ ). At this time, the ion implantation is performed using the thermal oxide film 1 having a thickness of about 10 nm.
02, the impurity can be introduced such that the impurity (phosphorus) concentration has a peak at a portion that is about 15 nm from the surface of the silicon substrate 102.

Next, as shown in FIG. 2D, the resist pattern is removed by, for example, an ashing process, and the silicon substrate 101 is subjected to a heat treatment. This heat treatment is performed to activate the impurities and increase the selectivity of the next etching. The heat treatment at this time is performed, for example, at 950 ° C. for 10 seconds (“RT
A (Rapid Thermal Annealin)
g) processing. ), Heat treatment of the silicon substrate 101 can be performed.

After this heat treatment, a portion having a high phosphorus (P) concentration (n ⁺ carrier concentration) is formed from the surface of the silicon substrate 101 to a portion which enters into the inside of about 50 nm.

After that, as shown in FIG. 2E, after the thermal oxide film 102 is removed by etching with, for example, a dilute hydrofluoric acid aqueous solution, the region of the silicon substrate 101 into which the impurity (phosphorus) is introduced is removed. For example, by etching under the following etching conditions, the silicon substrate 101 is etched.
A concave portion A is formed in the substrate.

(Silicon Etching Conditions) Etching solution: HF / HNO ₃ / CH ₃ COOH = 1
/ 3/12 Processing temperature: 20 ° C Processing time: 10 seconds

Under the above etching conditions, a region of the silicon substrate 101 having an impurity (phosphorus) concentration exceeding 5 × 10 ¹⁸ atoms / cm ³ can be selectively etched. Etching selectivity at this time is about 20, in the region of the silicon substrate 101 to which phosphorus is introduced, 50 nm approximately in the depth direction, but is etched while maintaining in-plane uniformity, the active region p ^- Layer (region of silicon substrate 101 into which phosphorus has not been introduced)
Is etched only about 2.5 nm.

Therefore, by performing the processing under the above-described etching conditions, the in-plane uniformity of the etching amount can be reduced by ± 5.
%. That is, the in-plane variation of the etching amount of silicon in the active portion is 0.1 to 0.1.
It can be suppressed within 2 nm, and in the field portion, the in-plane variation of the etching amount determined by the depth of introduction of phosphorus is taken into consideration, and the in-plane variation of the etching amount in the active portion and the field portion is considered in total. Also, the in-plane variation of the etching amount can be controlled within 1 nm.

Although the etching time is 10 seconds in this embodiment, in order to further improve the controllability of the etching (ie, to increase the in-plane uniformity of the etching amount), for example, a single wafer type Spin Processor (Spi
n Processer or the like.

Furthermore, in this embodiment, CH ₃ COOH is used as a buffer component in the etching solution. However, the composition ratio of this CH ₃ COOH is increased,
The controllability can be further improved by setting the temperature to a temperature lower than ° C. (the processing time needs to be lengthened).

As described above, the silicon substrate 101
In addition, the concave portions A having excellent in-plane uniformity can be formed. Since the depth of the concave portion A determines the thickness of the SOI layer, an SOI layer having a uniform thickness can be formed as a result.

Next, a buried oxide film 105 having a thickness of about 600 nm is formed as an insulating film so as to fill the recess A. The buried oxide film 105 is made of, for example, SiH ₄ −
CVD using O ₂ (Chemical Vapor)
(Deposition) method.

Further, a polysilicon film 10 is formed on the buried oxide film 105 as a flattening film for bonding.
6 is deposited. The polysilicon film 106 is made of, for example, S
It can be formed by a CVD method using iH ₄ .
As described above, the structure shown in FIG. In this embodiment, the polysilicon film is formed as the flattening film. However, any other material may be used as long as it is a film made of a material which can be easily flattened and can be firmly bonded to the second silicon substrate. Can also be formed.

Next, as shown in FIG.
MP (Chemical Mechanical Po)
The surface of the polysilicon film 106 is flattened by a lishing method.

Thereafter, as shown in FIG. 3H, the surface of the polysilicon film 106 on the first silicon substrate 101 and the second silicon substrate 107 are bonded. After the bonding, in order to increase the bonding strength of the bonding, for example, heat treatment is performed in an oxygen atmosphere at about 1000 ° C. for about 30 minutes. Before the bonding, it is preferable that the bonding surface is subjected to, for example, RCA cleaning or the like, so as to be in a hydrophilic surface state.

Next, as shown in FIG. 4I, the surface of the first silicon substrate 101 opposite to the bonding surface is ground to reduce the film thickness to about 5 μm.

In this grinding, for example, as described in the next second embodiment, hydrogen is ion-implanted into a position of a predetermined depth of the first silicon substrate 101 before bonding, so that the separation layer is formed. Is formed, the substrate is bonded to the second silicon substrate 107, and the bonded substrate is heated, whereby the first silicon substrate is separated by the separation layer, whereby the grinding time can be significantly reduced.

Further, the ground surface of the first silicon substrate 101 is further thinned by PACE processing and selective polishing.

The PACE processing is a technique for processing a thin film with a uniform thickness to a thickness required for an SOI layer by grinding and polishing. B. (See, for example, PB Mumola et al., 2).
nd Intern. Symp. on Semicon
ductor Wafer Bonding Scie
nce, Technology and Applic
ations (TheElectrochemical
Society, Pennington, NJ, 19
See 1994. ).

In the PACE process, first, the film thickness of a wafer to be etched is measured before etching by, for example, reflection spectroscopy, and plasma is generated under a PACE electrode which scans the wafer surface based on the measured data. ,
SF ₆ activated by the energy of this plasma
The etching is performed by controlling the etching time to etch the wafer surface. By performing the PACE processing, the ground surface of the first silicon substrate 101 can be further flattened and thinned.

In this embodiment, the first silicon substrate 10
After performing PACE processing on the ground surface of No. 1, selective polishing is further performed.

The conditions for the selective polishing at this time can be performed, for example, as follows. (Selective Polishing Conditions for First Silicon Substrate 101) Polishing Pad: Wet foamed nonwoven fabric type cloth (Suba
800) Polishing pressure: 300 g / cm ² Number of rotations: 60 rpm Abrasive: 0.0005% ethylenediamine aqueous solution Abrasive flow: 60 cc / min

In this selective polishing, the buried oxide film 105 is used as a polishing stopper. When the silicon oxide 105 in the field portion is completely exposed, the selective polishing is completed, and an SOI substrate as shown in FIG.

In the present embodiment, an example has been described in which a p-type silicon semiconductor substrate 101 is used as the first silicon substrate and phosphorus (P ⁺ ) ions are selectively introduced as impurities into the field portion of the substrate 101. The present invention is not limited to this. For example, n other than P such as As or Sb may be used.
Type impurities may be introduced.

Further, by introducing a p-type impurity such as boron, even if impurities of the same conductivity type are contained, the impurity concentration difference (for example, the impurity concentration of the first silicon substrate is 5 × 10 Less than ¹⁸ atoms / cm ³ ,
5 × 10 ¹⁸ atoms in a predetermined region of the first silicon substrate
By changing the etching rate based on the formation of an impurity-introduced layer of s / cm ³ or more, the concave portion can be formed by selectively etching with high in-plane uniformity.

In this embodiment, as the etching solution,
An etching solution consisting of HF / HNO ₃ / CH ₃ COOH = 1/3/12 is used.
An alkaline aqueous solution such as an aqueous solution containing KOH, hydrazine (NH ₂ NH ₂ ), and ethylene diamine (NH ₂ (CH ₂ ) ₂ NH ₂ ) can be used.

Further, an HF anodic etching method using an HF aqueous solution (for example, IEEE Electron Dev
ice Letters. , 11 (12) 588 (19
90) can also be used. According to this HF anodic etching method, a fine pattern can be formed with high accuracy. In this case, it is preferable that an n-type low-concentration impurity-containing substrate is used for the first silicon substrate, and that the impurity to be introduced into the field portion is a p-type impurity such as boron.

As described above, according to the present embodiment, first, the impurity introduction layer 104 having excellent in-plane uniformity is formed by ion implantation in the region where the concave portion A of the first silicon substrate 101 is formed. By forming and etching the impurity-doped layer 104 with high selectivity, a concave portion having better in-plane uniformity can be formed as compared with the conventional dry etching method, and the SOI layer with further improved film thickness uniformity can be formed. 1
08 can be manufactured.

Second Embodiment In a second embodiment , a silicon crystal defect is introduced into a first silicon substrate 201 by implanting silicon into a field portion by an ion implantation method, and the density of the crystal defect is reduced. Etching is performed under such etching conditions that the etching rate of silicon increases accordingly.
This is an example in which a recess B having high in-plane uniformity is formed in a predetermined region of the silicon substrate 201 of FIG.

First, as shown in FIG. 5A, a thermal oxide film 202 is formed on a first silicon substrate 201 on which an SOI layer is to be finally formed, for example, by a thermal oxidation method. This thermal oxide film 202 prevents contaminants such as metal from entering from a resist mask or the like into a region that will eventually become an SOI layer in the next step, and also prevents ions from being ion-implanted into a field portion. It also has the function of suppressing channeling. At this time, the thickness of the thermal oxide film 202 is 10 n.
m is sufficient.

Here, the first silicon substrate 201 has n
And a p-type low impurity concentration substrate, a single crystal silicon substrate, or the like can be used. In this embodiment, the density is 1 × 1
A silicon substrate 201 containing boron as a p-type impurity of about 0 ¹⁵ atoms / cm ³ (resistivity is about 20 Ω · cm) is used.

Next, as shown in FIG. 5B, a resist pattern 203 for element isolation is formed.

Next, using the resist pattern 203 as a mask, silicon (Si) ions for introducing crystal defects into the silicon substrate 201 are introduced by ion implantation.
Conditions for the ion implantation at this time are, for example, as follows.

(Si ⁺ ion implantation conditions) Acceleration voltage: 40 keV (Rp = about 50 nm) Dose: 5 × 10 ¹⁵ / cm ²

Since the Si ⁺ ions are implanted through the thermal oxide film 202, the Si ⁺ ions are introduced so as to have a concentration distribution peak at a portion of about 40 nm from the surface of the silicon substrate 201. At this time, ΔRp (variation in the range of ions) is about 10 nm. As described above, as shown in FIG. 5C, the silicon crystal defect introducing layer 204 is formed in a predetermined region of the silicon substrate 201. The silicon crystal defect introduction layer 204 is uniform in the depth direction because Si ⁺ ions are formed by ion implantation.

Thereafter, as shown in FIG. 6D, the resist pattern 203 is removed by ashing or the like.
As shown in (e), the thermal oxide film 202 is etched away with a solution such as dilute hydrofluoric acid, and the silicon crystal defect introduction layer 204 in the field portion is selectively etched away.

The etching conditions at this time can be performed, for example, under the same etching conditions as those used in the first embodiment. That is, HF /
Using a mixed solution of HNO ₃ / CH ₃ COOH = 1/3/12, processing is performed at an etching temperature of 20 ° C. for 10 seconds.

In the etching at this time, the silicon in the crystal defect introduction layer 204 of silicon in the field portion is instantaneously etched, but the silicon in the active portion is etched only by about 2.5 nm. In this case, the distribution (variation) of the etching amount of silicon in the active portion can be suppressed to within 0.1 to 0.2 nm.

Further, the distribution (variation) of the etching amount in the field portion is determined by the uniformity of the silicon crystal defect introduction layer in the depth direction. However, the distribution (variation) of the total etching amount can be controlled within 1 nm. In this way, FIG.
As shown in the figure, the concave portion B in which the in-plane uniformity is suppressed to within ± 5%.
Can be formed.

Next, as shown in FIG. 6F, similarly to the first embodiment, a buried oxide film 205 as an insulating film and a polysilicon film 206 as a planarizing film.
Are sequentially formed in the same manner as in the first embodiment, and as shown in FIG. 7G, the surface of the polysilicon film 206 is planarized by using, for example, a CMP method.

Next, as shown in FIG. 7H, hydrogen ions are ion-implanted into the first silicon substrate 201 at a predetermined depth to form the release layer 201 ′ in the first silicon substrate 201. Form.

Thereafter, as shown in FIG. 8I, the surface of the polysilicon layer 206 on the first silicon substrate 201 is
Lamination with the second silicon substrate 207 is performed. At this time, it is preferable that the bonded surface be subjected to, for example, standard RCA cleaning to make the surface hydrophilic. After bonding, for example, at 1000 ° C. in an oxygen atmosphere for 3 hours.
By performing the heat treatment for 0 minutes, the bonding strength of the bonding surfaces is strengthened.

Next, as shown in FIG. 8 (j), the separation (separation) of the back surface side portion C of the first silicon substrate 201 is performed at the boundary portion on the bonding surface side of the separation layer 201 '. A crack is generated in the separation layer 201 ′ by heat treatment after bonding or additional heat treatment thereafter, and the first silicon substrate 201 is easily separated by the separation layer 201 ′. Relatively easy. Thus, the grinding time on the back surface side of the first silicon substrate 201 can be significantly reduced. In addition, the peeled portion C of the first silicon substrate 201 can be reused by performing a regeneration process.

Thereafter, as in the first embodiment, the back surface of the first silicon substrate 201 is ground,
By performing the processing and the selective polishing, an SOI substrate as illustrated in FIG. 9K can be manufactured.

In this embodiment, the peeling layer 201 'is formed on the first silicon substrate 201 before the lamination, but it is needless to say that the peeling layer is not formed as in the first embodiment. The back surface of the first silicon substrate 201 can be ground by bonding with the second silicon substrate 207.

According to the present embodiment, first, a crystal defect introducing layer 204 having excellent in-plane uniformity is formed by ion implantation in a region where the concave portion B of the first silicon substrate 201 is formed. By etching the crystal defect introducing layer 204 with high selectivity, it is possible to form a concave portion having in-plane uniformity superior to that by the conventional dry etching method. Therefore, an SOI substrate having the SOI layer 208 with further improved film thickness uniformity can be manufactured.

In particular, in this embodiment, since the same silicon as the material of the first silicon substrate is introduced as an impurity, the total impurity concentration in the first silicon substrate 201 is the same as the initial concentration. Therefore, various semiconductor devices can be freely designed by using the SOI substrate manufactured in this embodiment.

[0100]

As described above, according to the present invention,
In a bonded SOI substrate manufactured by selective polishing using a buried oxide film as a polishing stopper, variation in the depth direction of a concave portion serving as a polishing reference surface formed first on a first silicon substrate (substrate to be polished) is suppressed. Thus, an SOI substrate having an SOI layer with excellent film thickness uniformity can be manufactured.

When the same silicon as the first silicon substrate material is introduced as an impurity, the total impurity concentration in the first silicon substrate is the same as the initial concentration. Therefore, various semiconductor devices can be freely designed and manufactured by using such an SOI substrate.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing main steps of a method for manufacturing an SOI substrate of the present invention.

FIG. 2 is a sectional view showing main steps of a method for manufacturing an SOI substrate of the present invention.

FIG. 3 is a cross-sectional view showing main steps of a method for manufacturing an SOI substrate of the present invention.

FIG. 4 is a cross-sectional view showing main steps in a method for manufacturing an SOI substrate of the present invention.

FIG. 5 is a cross-sectional view showing main steps in a method for manufacturing an SOI substrate of the present invention.

FIG. 6 is a cross-sectional view showing main steps in a method for manufacturing an SOI substrate of the present invention.

FIG. 7 is a cross-sectional view showing main steps of a method for manufacturing an SOI substrate of the present invention.

FIG. 8 is a cross-sectional view showing main steps in a method for manufacturing an SOI substrate of the present invention.

FIG. 9 is a cross-sectional view of an SOI substrate manufactured by an SOI substrate manufacturing method of the present invention.

FIG. 10 is a cross-sectional view of main steps in a conventional method for manufacturing an SOI substrate.

FIG. 11 is a cross-sectional view of main steps in a conventional method for manufacturing an SOI substrate.

[Explanation of symbols]

101, 201, 301 ... first silicon substrate, 10
2, 202, 302: thermal oxide film, 103, 203, 30
3 ... resist pattern, 104 ... impurity introduction layer, 204
... crystal defect introduction layer, 105, 205, 305 ... insulating film (buried oxide film), 106, 206, 306 ... flattening film (polysilicon film), 107, 207, 307 ... second
Silicon substrate, 108, 208, 308... SOI layer

Claims (13)

[Claims] A step of forming a recess in a predetermined region of the first silicon substrate; a step of forming an insulating film so as to fill the recess; a step of forming the recess in the first silicon substrate; Bonding a silicon substrate, a step of grinding a surface opposite to a bonding surface of the first silicon substrate, and a step of selectively polishing the ground surface. A method for manufacturing a bonded SOI substrate, comprising a step of introducing an impurity that changes the etching rate of silicon into a region where the concave portion is to be formed before the formation of the concave portion. 2. The step of introducing an impurity which changes the etching rate of silicon into a region where the concave portion is formed is a step of introducing an impurity which changes the etching speed of silicon into the region where the concave portion is formed by ion implantation. The method for manufacturing a bonded SOI substrate according to claim 1, comprising: 3. The step of introducing an impurity which changes the etching rate of silicon into the region where the concave portion is formed includes the step of introducing an impurity which changes the crystal defect density of silicon into the region where the concave portion is formed. A method for manufacturing a bonded SOI substrate according to claim 1. 4. The step of introducing an impurity which changes the etching rate of silicon into the region where the recess is formed, the step of introducing phosphorus, boron, arsenic, silicon or a compound thereof into the region where the recess is formed. The method for manufacturing a bonded SOI substrate according to claim 1, comprising: 5. The step of introducing an impurity which changes the etching rate of silicon into the region where the concave portion is to be formed, the method comprises the step of implanting phosphorus, boron, arsenic, silicon or a compound thereof into the region where the concave portion is to be formed. 2. The method for manufacturing a bonded SOI substrate according to claim 1, further comprising: 6. A step of forming a concave portion in a predetermined region of the first silicon substrate, the step of forming the concave portion in a predetermined region of the first silicon substrate under the condition that an etching rate changes according to a type of impurity contained in the silicon substrate or a concentration of the impurity. 2. The method for manufacturing a bonded SOI substrate according to claim 1, further comprising a step of etching a predetermined region of the one silicon substrate. 7. The step of forming a concave portion in a predetermined region of the first silicon substrate, wherein the step of forming the concave portion in the predetermined region of the first silicon substrate is performed under a condition that an etching rate changes according to a type of impurity contained in the silicon substrate or a concentration of the impurity. 2. The method for manufacturing a bonded SOI substrate according to claim 1, further comprising a step of etching a predetermined region of the one silicon substrate by a wet etching method. 8. A step of forming a concave portion in a predetermined region of the first silicon substrate, the step of forming the concave portion in a predetermined region of the first silicon substrate under the condition that an etching rate changes according to a type of impurity contained in the silicon substrate or a concentration of the impurity. The method for manufacturing a bonded SOI substrate according to claim 1, further comprising a step of etching a predetermined region of the one silicon substrate by HF anodic etching. 9. The step of forming a concave portion in a predetermined region of the first silicon substrate includes the step of forming a concave portion in the predetermined region of the first silicon substrate according to the type of impurity contained in the silicon substrate or the concentration of the impurity. The method for manufacturing a bonded SOI substrate according to claim 1, further comprising a step of etching the region using an etching solution containing acetic acid, potassium hydroxide, ethylenediamine, or hydrazine. 10. The method for manufacturing a bonded SOI substrate according to claim 1, wherein the step of selectively polishing the ground surface includes the step of selectively polishing the ground surface using the insulating film as a polishing stopper. 11. The step of forming the insulating film, the step of forming
2. The production of a bonded SOI substrate according to claim 1, further comprising a step of forming a flattening film on the insulating film between the step of bonding the concave portion forming surface of the silicon substrate and the second silicon substrate. Method. 12. The method for manufacturing a bonded SOI substrate according to claim 11, wherein the step of forming a planarizing film on the insulating film includes a step of forming a polysilicon film having a flat surface on the insulating film. 13. A method of polishing a ground surface of a PACE (Plasm) between a step of grinding a surface of the first silicon substrate opposite to a bonding surface and a step of selectively polishing the ground surface.
a Assisted Chemical Etchi
2. The method for manufacturing a bonded SOI substrate according to claim 1, further comprising a step of performing ng) processing.