JP3948035B2 - Method for creating bonded SOI substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  This invention is a laminateMethod for manufacturing SOI substrateIn particular, even if the buried oxide film is formed by a method other than the thermal oxidation method, the thickness of the SOI layer can be made uniform, and high integration can be realized by embedding various elements in the SOI substrate. Bonding that can suppress the short channel effect of MOS transistorsMethod for manufacturing SOI substrateAbout.
[0002]
[Prior art]
  A MOS transistor formed on a single crystal silicon (Silicon on Insulator: SOI) layer on an insulating film such as an oxide film has excellent radiation resistance and latch-up characteristics compared to a normal MOS transistor, and a short channel. Excellent suppression of effects. In particular, a method for manufacturing an SOI substrate to which a wafer bonding technique is applied has become one of the most noticeable techniques in recent years because an SOI layer with very few defects is generally obtained.
[0003]
  As one of the methods for manufacturing SOI substrates using the above wafer bonding technique, recently, Smart Cut(Registered trademark) Technology (Smart Cut (Registered trademark) Process) is commercialized at SOITEC, France.
[0004]
  Smart Cut(Registered trademark) Explain Process.FIG.(A) ~FIG.(D) shows a conventional method for manufacturing a bonded SOI substrate (Smart Cut(Registered trademark) FIG. First,FIG.As shown in (a), an oxide film layer 1102 having a thickness of, for example, 400 nm is formed on the first Si wafer 1101 by a thermal oxidation method.
[0005]
  next,FIG.As shown in FIG. 6B, for example, 2 × 10 hydrogen ions 1109 are passed through the oxide film layer 602 on the first Si wafer 1101.¹⁶/ Cm² ~ 5x10¹⁶/ Cm² Ion implantation is performed with a moderate dose. The ion implantation energy at this time is set so that the peak range (Rp) 1103 of the ion implantation is present in the first Si wafer 1101. Specifically, Rp is the oxide film layer 1102 and the first Si wafer 1101. Is set to a depth of about 250 nm from the boundary surface.
[0006]
  Next, after the surface of the oxide film layer 1102 is cleaned,FIG.As shown in (c), the surface of the oxide film layer 1102 and the surface of the second Si wafer 1104 are bonded together. This lamination is performed at room temperature.
[0007]
  Thereafter, the bonded first and second wafers 1101 and 1104 are put in a diffusion furnace (not shown) and annealed at a low temperature of about 400 ° C. to 500 ° C. in this diffusion furnace. At this time, the first wafer 1101 is cut at the peak range (Rp) 1103 of the ion implantation. ThisFIG.As shown in FIG. 4D, an SOI layer (single crystal silicon layer) 1105 having a thickness of about 250 nm is formed on the second wafer 1104 with an oxide film layer (insulating film) 1102 interposed therebetween. As a result, a bonded SOI substrate 1110 is formed.
[0008]
  Next, by polishing the surface of the SOI layer 1105 by about 50 nm, damage due to cutting on the surface of the SOI layer 1105 is removed. Thereafter, the bonded SOI substrate 1110 is annealed at a high temperature of 1100.degree. This is a process for enhancing the bonding strength of the bonded SOI substrate 1110 and reducing crystal defects in the vicinity of the surface of the SOI layer 1105. In this way, a conventional bonded SOI substrate is manufactured. According to this method, it is possible to form an SOI layer 1105 with extremely high uniformity with a thickness variation of ± 5 nm on the entire surface of the wafer.
[0009]
  Thereafter, a MOS transistor (not shown) is formed in the SOI layer 1105 in the bonded SOI substrate.
[0010]
[Problems to be solved by the invention]
  By the way, the conventional bonded SOI substrate and its manufacturing method (Smart Cut(Registered trademark) Process) has the following problems. As described above, the MOS transistor formed in the SOI layer is excellent in suppressing the short channel effect. However, as the transistor is further miniaturized, even the MOS transistor formed in the SOI layer has a short channel effect. Occurs. That is, as the gate length of the MOS transistor is shortened, the lines of electric force from the drain reach the source through the SOI layer where the channel is formed, and as a result, there is a problem that leakage current increases. .
[0011]
  The uniformity of the thickness of the SOI layer in the bonded SOI substrate manufactured by the above method is within the plane of the buried oxide film thickness where ions pass during ion implantation and the peak range (Rp) of the ion implantation itself. Determined by uniformity. For this reason, it is necessary to use a process with excellent film thickness uniformity as a method for forming a buried oxide film. Specifically, as used in the conventional method for manufacturing a bonded SOI substrate, a thermal oxidation method is used. It will be limited to. However, in a method for manufacturing a bonded SOI substrate having an embedded element such as a backside gate electrode, most of the embedded oxide film must be formed by a CVD (Chemical Vapor Deposition) method which is a method other than the thermal oxidation method. First, when the CVD method is used, the thickness of the buried oxide film becomes non-uniform. Furthermore, since the buried oxide film formed by the CVD method may need to be subjected to a polishing process for planarization, the thickness uniformity of the buried oxide film is five times worse than that of the thermal oxide film. Become. In addition, when a structure in which various elements for realizing high integration are embedded in an SOI substrate is used, the range of implanted ions may be different depending on the material in which this element is formed. In-plane uniformity of the peak range (Rp) of ion implantation itself deteriorates. Therefore, in the conventional method for manufacturing a bonded SOI substrate, when the various elements are embedded in the SOI substrate, or when the buried oxide film is formed by the CVD method, the film thickness is uniform as in the case of the thermal oxidation method. An excellent SOI layer cannot be formed.
[0012]
  The present invention has been made in view of the above circumstances, and an object thereof is a bonded SOI substrate capable of suppressing the short channel effect of a MOS transistor.How to makeIs to provide.
[0013]
  Another object of the present invention is to provide a method for manufacturing a bonded SOI substrate that can make the thickness of the SOI layer uniform even if the buried oxide film is formed by a method other than the thermal oxidation method.
[0014]
  Another object of the present invention is to achieve high integration by embedding various elements in an SOI substrate without impairing the uniformity of the SOI layer thickness.Method for manufacturing SOI substrateIs to provide.
[0015]
[Means for Solving the Problems]
  In order to solve the above problems, a method for manufacturing a bonded SOI substrate according to the present invention includes a step of forming a first insulating film on the surface of a Si wafer and a step of forming an element on the first insulating film. A step of forming a second insulating film on the element and the first insulating film, a step of planarizing the second insulating film, and the first and second insulating layers on the Si wafer. Smart Cut through membrane and above element(Registered trademark)Forming a peak range of ion implantation at a certain depth in the Si wafer by performing ion implantation in the method, attaching a semiconductor wafer to the surface of the second insulating film, and the Si wafer. And a step of cutting at a peak range portion of the ion implantation.
[0016]
  Further, the second insulating film in the step of forming the second insulating film is formed by a CVD method.
[0017]
  A step of providing a step on the surface of the Si wafer by forming a polishing stopper layer made of a material other than Si on the surface of the Si wafer; and a step of providing an element between the polishing stopper layers; A step of providing an insulating film on the element and the polishing stopper layer; a step of planarizing the insulating film; and a Smart Cut through the insulating film and the polishing stopper layer on the Si wafer.(Registered trademark)Forming a peak range of the ion implantation in the Si wafer by performing ion implantation in the method, attaching the semiconductor wafer to the surface of the insulating film, and a peak range of the ion implantation of the Si wafer. And a step of chemically polishing the cut surface of the Si wafer with an alkaline polishing liquid containing no abrasive grains using the polishing stopper layer as a stopper. And
[0018]
  Further, a step of providing a step on the surface of the Si wafer by etching and removing a part of the surface of the Si wafer by a dry etching method, and a polishing stopper layer made of a material other than Si on the step portion Forming an element between the polishing stopper layer, providing an insulating film on the element and the polishing stopper layer, flattening the insulating film, and the Si wafer Smart Cut through the insulating film and the polishing stopper layer(Registered trademark)Forming a peak range of the ion implantation in the Si wafer by performing ion implantation in the method, attaching the semiconductor wafer to the surface of the insulating film, and a peak range of the ion implantation of the Si wafer. And a step of chemically polishing the cut surface of the Si wafer with an alkaline polishing liquid containing no abrasive grains using the polishing stopper layer as a stopper. And
[0019]
  Further, a CMP method is used as a planarization means in the planarization step.
[0020]
  In addition, the element is a backside gate electrode, a wiring, a resistor, or a capacitor.
[0021]
  In addition, the SOI layer is selectively formed only in the active region of the MOS transistor by the chemical polishing step.
[0022]
  Further, the polishing selectivity in the above-described chemical polishing step (where the polishing selectivity is Rsi / Rsoi, and Rsi is the film reduction of the silicon substrate in chemical polishing when the entire polishing surface is a silicon substrate) Rsoi is a film reduction rate of the SOI layer remaining between the polishing stopper layers when polishing reaches the polishing stopper layer.
[0023]
  Above bondingIt was formed on the SOI substrate by the SOI substrate manufacturing method.In the MOS transistor, a back surface gate electrode is provided below the gate electrode, and a channel formation region is sandwiched between the back surface gate electrode and the gate electrode. Therefore, when the MOS transistor is driven, the electric lines of force from the drain are terminated at the back gate electrode, so that the electric lines of force from the drain are prevented from reaching the source through the channel as in the conventional MOS transistor. it can. As a result, leakage current can be suppressed. In this way, the short channel effect of the MOS transistor can be suppressed, and the variation in characteristics of the MOS transistor can be suppressed.
[0024]
  In the method for manufacturing the bonded SOI substrate, the surface of the Si wafer after being cut is chemically polished with an alkaline polishing liquid containing no abrasive grains using the polishing stopper layer as a stopper. For this reason, variation in the thickness of the SOI layer after polishing can be reduced. That is, when a planarized insulating film is formed on the polishing stopper layer and the Si wafer, strictly speaking, this insulating film has a variation in film thickness, and the range of various ions in the oxide film Although the thickness of the SOI layer after cutting the Si wafer becomes non-uniform due to a slight difference in the range in Si, if the above chemical polishing is performed, the thickness of the SOI layer after the cutting is reduced. Variation can be reduced. Further, by setting the polishing selection ratio in the above-described chemical polishing step to 37, the variation in the thickness of the SOI layer after polishing can be reduced to 1/37.
[0025]
  Also, the bonded SOI substrateHow to makeThen, by embedding an element such as a capacitor in the insulating film, high integration can be realized when a semiconductor device using a bonded SOI substrate is manufactured, and even in this case, the uniformity of the thickness of the SOI layer is impaired. There is no.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
  Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are sectional views showing a method for manufacturing a bonded SOI substrate according to a first embodiment of the present invention. FIG. 7A is a plan view showing a MOS transistor, and this MOS transistor is formed on a bonded SOI substrate manufactured by the above-described manufacturing method. FIG. 7B is a plan view of FIG. 7) is a cross-sectional view taken along line 7a-7a.
[0027]
  First, as shown in FIG. 1, a first silicon oxide film 102 having a thickness of, for example, 50 nm is formed on the surface of the first Si wafer 101 by a thermal oxidation method.
[0028]
  Next, as shown in FIG. 2, on the first silicon oxide film 102, a back surface gate electrode 103 located above a channel region of a MOS transistor described later is formed. The back gate electrode 103 is formed by a series of processes such as deposition of a structure material by a CVD (Chemical Vapor Deposition) method, patterning by a lithography technique and a dry etching technique, for example.
[0029]
  Specifically, for example, a polycrystalline silicon film is deposited on the first silicon oxide film 102 by a CVD method, and a resist film (not shown) located above the channel region is deposited on the polycrystalline silicon film. It is formed. By etching the polycrystalline silicon film using the resist film as a mask, a back electrode 103 made of polycrystalline silicon is formed on the first silicon oxide film 102. Then, the resist film is removed.
[0030]
  Thereafter, as shown in FIG. 3, a second silicon oxide film 106 is deposited on the back gate electrode 103 and the first silicon oxide film 102 by a CVD method. Thereafter, the surface of the silicon oxide film 106 is planarized by means such as CMP (Chemical Mechanical Polishing). Since this CMP flattening method is a technique using a multilayer stopper, when CMP is used, a second silicon oxide film 106, a BPSG film, etc. are laminated on the back gate electrode 103 and the first silicon oxide film 102. However, if this is used, the variation in film thickness of the silicon oxide film 106 after planarization can be suppressed to about ± 30 nm. Therefore, the silicon oxide film 106 with high film thickness uniformity can be formed.
[0031]
  Next, as shown in FIG. 4, the first Si wafer 101 is subjected to Smart Cut through the first and second silicon oxide films 102 and 106 and the back gate electrode 103.(Registered trademark)Ion implantation in the method is performed. In this case, for example, hydrogen ions 109 are 2 × 10 6.¹⁶/ Cm² ~ 5x10¹⁶/ Cm² This is performed at a moderate dose (about 10 times the dose at the time of source / drain region formation in a semiconductor process). Further, the ion implantation energy is set so that the peak range of the ion implantation exists in the first Si wafer 101. Specifically, the peak range includes the first silicon oxide film 102, the first Si wafer 101, and the first Si wafer 101. For example, the depth is set to about 250 nm from the boundary surface. Since the ranges of various ion implantations in the oxide film and Si are almost equal, the peak range (Rp2) 105 is substantially constant from the surface in the Si wafer 101 regardless of the location.
[0032]
  Thereafter, as shown in FIG. 5, the roughness of the surface of the second Si oxide film 106 and the dust adhering to the surface are removed by applying means such as CMP. Next, a second Si wafer 107 is prepared, and the surface of the second silicon oxide film 106 and the surface of the second Si wafer 107 are bonded together. This lamination is performed at room temperature.
[0033]
  Thereafter, the bonded first and second Si wafers 101 and 107 are put in a diffusion furnace (not shown) and annealed at a low temperature of about 400 ° C. to 500 ° C. in this diffusion furnace. At this time, the first Si wafer 101 is cut at the peak range (Rp2) 105 of the ion implantation. As a result, an SOI layer (single crystal silicon layer) 108 is formed on the second Si wafer 107 via the first and second silicon oxide films 102 and 106 as shown in FIG. In this way, the SOI substrate 120 in which the back gate electrode 103 is buried below the region including the channel of the MOS transistor is obtained.
[0034]
  Next, by polishing the surface of the SOI layer 108 by about 50 nm, damage caused by cutting on the surface of the SOI layer 108 is removed. Thereafter, the bonded SOI substrate 120 is annealed at a high temperature of 1100.degree. This is a process for enhancing the bonding strength of the bonded SOI substrate 120 and reducing crystal defects in the vicinity of the surface of the SOI layer 108.
[0035]
  Thereafter, as shown in FIG. 7A, an element isolation region (element isolation oxide film) 702 is provided in a portion other than the MOSFET active region 701 on the surface of the SOI layer 108.
[0036]
  Next, in the MOSFET active region 701, as shown in FIG. 7B, a gate electrode 703 is formed on the SOI layer 108 located above the back gate electrode 103 via a gate insulating film (not shown). Is done. Thereafter, diffusion layers of source / drain regions (not shown) are formed in the SOI layer 108 located on both sides of the gate electrode 702.
[0037]
  The back gate electrode 103 is electrically connected to a wiring layer (not shown). This wiring layer is for controlling the potential of the back gate electrode 103, and is usually connected to the ground (ground potential) for the nMOS transistor and connected to the power source for the pMOS transistor.
[0038]
  According to the first embodiment, as shown in FIG. 7B, the back gate electrode 103 is provided below the gate electrode 703, and the channel formation region is sandwiched between the back gate electrode 103 and the gate electrode 703. The back gate electrode 103 is electrically connected to a wiring layer (not shown) and fixed to the ground potential or the power supply potential. Therefore, when the MOS transistor is driven, the electric lines of force from the drain are terminated by the back gate electrode 103 having a fixed potential, so that the electric lines of force from the drain pass through the channel as in the conventional MOS transistor. Can be prevented from reaching the source. As a result, leakage current can be suppressed. In this way, the short channel effect of the MOS transistor can be suppressed, and the variation in characteristics of the MOS transistor can be suppressed. The effect of suppressing the leakage current is that the channel of the MOS transistor is formed as the oxide film (first silicon oxide film 102) between the back gate electrode 103 and the SOI layer 108 is thinner. The thinner the SOI layer 108 in the region, the larger the region.
[0039]
  In the first embodiment, the back gate electrode 103 is embedded in the lower part of the MOS transistor. However, in addition to the back gate electrode 103 or in addition to the back gate electrode 103, a wiring, a resistor, a capacitor, etc. It is also possible to embed an element. Thus, high integration can be realized when a semiconductor device using a bonded SOI substrate is manufactured.
[0040]
  8 to 13 are sectional views showing a method for manufacturing a bonded SOI substrate according to the second embodiment of the present invention. FIGS. 13A and 13B are cross-sectional views showing a planarization process by chemical polishing of the SOI layer in the above manufacturing method, and FIG. 13A is a manufacturing process of the bonded SOI substrate shown in FIG. This is a more accurate representation of the thickness of the SOI layer.
[0041]
  First, as shown in FIG. 8, in the MOSFET active region 803 on the surface of the first Si wafer (Si substrate) 801, a thermal oxidation mask layer (not shown) including, for example, a Si nitride film is selected using a lithography technique or the like. Formed. Thereafter, an oxide film is selectively grown using the thermal oxidation mask layer as a mask, so that, for example, a LOCOS as a polishing stopper layer made of a material other than Si is formed in the element isolation region on the surface of the first Si wafer 801. An oxide film 802 is formed. At this time, about 45% of the LOCOS oxide film 802 is formed in the internal direction of the Si substrate 801, so that a step 804 is formed between the lower portion of the LOCOS oxide film 802 and the surface of the MOSFET active region 803. Thereafter, the thermal oxidation mask layer is removed using various etching techniques including wet etching.
[0042]
  Although not shown in the drawing, the polishing stopper layer (LOCOS oxide film) 802 can also be formed by an etching method (for example, a dry etching method). In the case of the etching method, first, a resist film is coated on the MOS transistor active region 803 on the surface of the first Si wafer 801 by a lithography technique. Thereafter, for example, Cl is used as a mask.₂ / O₂ By performing RIE (Reactive Ion Etching) with a system gas for a predetermined time, the surface of the wafer 801 in the element isolation region is removed by etching. As a result, a step 804 is formed on the surface of the wafer 801. The predetermined time may be calculated backward from the etching rate to obtain a desired level difference. A silicon oxide film, for example, is formed on the step 804 as a polishing stopper layer made of a material other than Si.
[0043]
  Next, as shown in FIG. 9, an oxide film (not shown) having a thickness of about 100 nm is formed on the first Si wafer 801 and the LOCOS oxide film 802 by thermal oxidation, and is located above the MOSFET active region 803. A backside gate electrode 805 made of, for example, a polycrystalline silicon layer is formed on the oxide film by using a lithography technique or the like.
[0044]
  Thereafter, a silicon oxide film 806 having a thickness of about 400 nm is formed on the back gate electrode 805 and the LOCOS oxide film 802 by a CVD method.
[0045]
  Thereafter, the surface of the silicon oxide film 806 is planarized. This planarization is performed by an arbitrary method, but a special CMP (Chemical Mechanical Polishing) planarization method can also be used. If this is used, silicon oxide after planarization on the MOSFET active region 803 is used. The film thickness variation of the film 806 can be suppressed to about ± 30 nm.
[0046]
  Next, as shown in FIG. 10, the first Si wafer 801 is subjected to Smart Cut from the planarized surface of the silicon oxide film 806.(Registered trademark)In this method, ion implantation 809 is performed. The ion implantation energy at this time is set so that the peak range (Rp) 807 of the ion implantation exists in the first Si wafer 801. Specifically, Rp is the silicon oxide film 806 and the first Si wafer. The depth is set to about 250 nm from the boundary surface 801. Since the ranges of various ions in the oxide film and Si are almost equal, the peak range (Rp) 206 is almost constant from the surface in the Si wafer 801 regardless of the location. Since the film thickness of the formed silicon oxide film 806 becomes more non-uniform than that by the conventional thermal oxidation method, a larger variation in Rp occurs than in the conventional method for manufacturing a bonded SOI substrate.
[0047]
  Thereafter, after the surface of the silicon oxide film 806 is cleaned, a second Si wafer 808 is prepared. As shown in FIG. 11, the surface of the silicon oxide film 806 and the surface of the second Si wafer 808 are separated. It is pasted together. This lamination is performed at room temperature.
[0048]
  Next, the bonded first and second Si wafers 801 and 808 are annealed at a low temperature of about 400 ° C. to 500 ° C. At this time, the first Si wafer 801 is cut at the peak range (Rp) 807 of the ion implantation. Thus, as shown in FIG. 12, an SOI layer (single crystal silicon layer) 811 is formed on the second Si wafer 808 via the back gate electrode 805, the silicon oxide film 806, and the LOCOS oxide film 802. . As a result, an SOI substrate 820 is obtained.
[0049]
  FIG. 13A shows the state of the thickness of the SOI layer 811 in the SOI substrate 820 obtained as described above in more detail. As can be seen from FIG. 13A, the cut surface (Rp surface) of the first Si wafer 801 is not constant, and there is a certain variation (ΔRp) 1304 in the thickness of the SOI layer 811. In the above-described process, the largest cause of ΔRp is the film thickness variation (non-uniform film thickness) of the silicon oxide film 806, and strictly speaking, the range of various ions in the oxide film and Si. A slight difference in the range of ΔRp also causes ΔRp. As a result, ΔRp is about ± 50 nm depending on the location.
[0050]
  Thereafter, as shown in FIG. 13B, the surface of the SOI layer 811 after the cutting is subjected to chemical polishing (hereinafter also referred to as “selective polishing”) with an alkaline polishing liquid that does not contain polishing abrasive grains. Polishing is performed using a polishing stopper layer (LOCOS oxide film) 802 as a stopper under a polishing selection ratio of 37. As a result, the surface of the polishing stopper layer 802 is exposed over the entire polishing surface, and the SOI layer 811 remains only between the polishing stopper layers 802.
[0051]
  The selective polishing will be described in detail below. The surface of the SOI layer 811 after the cutting is chemically polished using a polishing liquid made of an alkaline solution such as an ethylenediamine aqueous solution or an ammonia aqueous solution. In this chemical polishing, it is important to set the polishing pressure and the rotation speed of the polishing constant. Here, the polishing pressure is the pressure applied to the polishing surface, and the rotational speed of the polishing constant is the rotational speed of the polishing constant disposed in a state of facing the holding constant supporting the bonded SOI substrate 820.
[0052]
  Note that a 0.0005% ethylenediamine solution was used as the polishing liquid, and the flow rate of the polishing liquid was 60 cm.^Three / Min and polishing is performed in a room temperature atmosphere of 20 ° C. The rotation speed of the holding constant is set equal to the rotation speed of the polishing constant.
[0053]
  FIG. 14 shows a case where the cut surface of the first Si wafer (silicon substrate) 801 is polished under the above-described conditions. The horizontal axis represents the product of the polishing pressure w and the rotation speed rot of the polishing constant. A graph F5 in which the ratio of the film reduction rate Rsi of silicon to the film reduction rate Rsoi of the SOI layer is plotted on the vertical axis is shown. However, the film reduction rate Rsi of the silicon substrate is the film reduction rate of the silicon substrate in chemical polishing when the entire polishing surface is a silicon substrate. The SOI layer film reduction rate Rsoi is the film reduction rate of the SOI layer 811 remaining between the polishing stopper layers 802 when the polishing reaches the polishing stopper layer 802.
[0054]
  Here, the value at which the differential coefficient of the film reduction rate Rsi of the silicon substrate and the differential coefficient of the film reduction rate Rsoi of the SOI layer are approximately equal to the product of the polishing pressure w and the rotational speed rot of the polishing constant is selective polishing. Is the optimum value. Therefore, the optimum value is a value indicating the maximum value in the graph F5, and specifically, it is around w × rot = 13000 and Rsi / Rsoi = 37. This corresponds to the above-described polishing selection ratio (Rsi / Rsoi) 37 and is an optimum condition when the SOI layer 811 is planarized by selective polishing.
[0055]
  Thereafter, polycrystalline silicon is formed on the SOI layer 811 (MOSFET active region 803) left only between the element isolation regions (LOCOS oxide film as a polishing stopper layer) 802 via a gate oxide film (not shown). A gate electrode (not shown) is formed, and this gate electrode is located above the back gate electrode 805. A diffusion layer of source / drain regions (not shown) is formed in the SOI layer 811 located below both side surfaces of the gate electrode. As a result, a MOS transistor (not shown) is formed in the MOSFET active region 803.
[0056]
  According to the second embodiment, the layer (LOCOS oxide film) made of a material other than Si in the element isolation region is used as the polishing stopper layer 802 and selective polishing is performed under the condition of the polishing selection ratio 37, so that FIG. The variation ΔRp in the thickness of the SOI layer 811 shown in (a) can be reduced to 1/37. That is, in the case where the thickness variation ΔRp of the SOI layer 811 shown in FIG. 13A is about ± 50 nm, if the SOI layer 811 is polished under the condition of the polishing selection ratio 37, as shown in FIG. In addition, the thickness variation ΔTsoi (difference between Tsoi.1 and Tsoi.2) of the SOI layer 811 after selective polishing can be suppressed to about ± 2 nm.
[0057]
  That is, in the step shown in FIG. 9, even if a silicon oxide film 806 is formed on the LOCOS oxide film 802 and the back gate electrode 805 by a method other than the thermal oxidation method, for example, a CVD method, and the silicon oxide film 806 is planarized. Strictly speaking, the film thickness varies, and the SOI layer 811 after cutting the first Si wafer 801 has a slight difference between the range of various ions in the oxide film and the range in Si. Although the thickness is also uneven, if selective polishing is performed under the condition of the polishing selection ratio 37, the thickness variation ΔRp of the SOI layer 811 after cutting can be reduced to 1/37.
[0058]
  In the second embodiment, the polishing stopper layer (LOCOS oxide film) 202 is formed on the surface of the first Si wafer 201 by the LOCOS method. However, the method of forming this polishing stopper layer is limited to the LOCOS method. However, the polishing stopper layer can be formed by other methods.
[0059]
  Further, as shown in FIG. 9, the back surface gate electrode 805 is formed in the MOSFET active region 803, but the present invention can be applied to other things, and the MOSFET active region 803 is combined with the back surface gate electrode 805. Alternatively, in addition to the back surface gate electrode 805, an element such as a wiring, a resistor, or a capacitor can be embedded. Accordingly, high integration can be realized when a semiconductor device using a bonded SOI substrate is manufactured, and even in this case, the uniformity of the thickness of the SOI layer 811 is not impaired.
[0060]
【The invention's effect】
  As described above, according to the present invention, the back gate electrode is provided below the gate electrode, and the channel forming region is sandwiched between the back gate electrode and the gate electrode. Further, the surface of the Si wafer after being cut is chemically polished with an alkaline polishing liquid containing no abrasive grains using the polishing stopper layer as a stopper. Therefore, it is possible to suppress the short channel effect of MOS transistors.Method for manufacturing SOI substrateCan be provided. In addition, even when the buried oxide film is formed by a method other than the thermal oxidation method, a method for manufacturing a bonded SOI substrate that can make the thickness of the SOI layer uniform can be provided. In addition, bonding that realizes high integration by embedding various elements in the SOI substrate without impairing the uniformity of the thickness of the SOI layerMethod for manufacturing SOI substrateCan be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a method for manufacturing a bonded SOI substrate according to a first embodiment of the invention.
FIG. 2 is a cross-sectional view illustrating a method for manufacturing a bonded SOI substrate according to the first embodiment of the present invention and illustrating the next step of FIG. 1;
FIG. 3 is a cross-sectional view illustrating a method for manufacturing a bonded SOI substrate according to the first embodiment of the present invention and illustrating the next step of FIG. 2;
FIG. 4 is a cross-sectional view showing a method for manufacturing a bonded SOI substrate according to the first embodiment of the present invention and showing the next step of FIG. 3;
FIG. 5 is a sectional view showing a method for manufacturing a bonded SOI substrate according to the first embodiment of the present invention and showing a step subsequent to FIG. 4;
6 is a cross-sectional view showing a method for manufacturing a bonded SOI substrate according to the first embodiment of the present invention and showing a step subsequent to FIG. 5. FIG.
7 (a) is a plan view showing a MOS transistor formed on a bonded SOI substrate according to the first embodiment of the present invention, and FIG. 7 (b) is a plan view of FIG. 7 (a). Sectional drawing along line 7a.
FIG. 8 is a cross-sectional view showing a method for manufacturing a bonded SOI substrate according to a second embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a method for manufacturing a bonded SOI substrate according to the second embodiment of the present invention and showing a step subsequent to that in FIG. 8;
FIG. 10 is a cross-sectional view showing a method for manufacturing a bonded SOI substrate according to the second embodiment of the present invention and showing a step subsequent to FIG. 9;
FIG. 11 is a cross-sectional view showing a method for manufacturing a bonded SOI substrate according to the second embodiment of the present invention and showing the next step of FIG. 10;
FIG. 12 is a cross-sectional view showing a method for manufacturing a bonded SOI substrate according to the second embodiment of the present invention and showing the next step of FIG. 11;
FIG. 13A shows a method for manufacturing a bonded SOI substrate according to the second embodiment of the present invention, and shows the thickness of the SOI layer in the manufacturing process of the bonded SOI substrate shown in FIG. FIG. 13B is a cross-sectional view showing the state more accurately, and FIG. 13B shows a planarization step by chemical polishing of the SOI layer in the above manufacturing method, and the next step of FIG. FIG.
FIG. 14 is a graph showing a film reduction rate ratio between the silicon substrate and the SOI layer with respect to the product of the number of rotations of the polishing constant and the polishing pressure.
FIGS. 15A to 15D are cross-sectional views illustrating a conventional method for manufacturing a bonded SOI substrate. FIGS.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... 1st Si wafer, 102 ... 1st silicon oxide film, 103 ... Back surface gate electrode, 105 ... Peak range (Rp2) of ion implantation, 106 ... 2nd silicon oxide film, 106a ... Flattened oxidation Surface of film 107 107 Second silicon wafer 108 SOI layer 109 Hydrogen ion 120 SOI substrate 701 MOSFET active region 702 Element isolation region 703 Gate electrode 801 First Si wafer (Si substrate), 802 ... polishing stopper layer (LOCOS oxide film, element isolation region), 803 ... MOS transistor active region, 804 ... step, 805 ... back gate electrode, 806 ... silicon oxide film, 807 ... peak range of ion implantation (Rp), 808 ... second Si wafer, 809 ... Smart Cut(Registered trademark) Ion implantation in the method, 811 ... SOI layer (single crystal silicon layer), 1304 ... variation in thickness of the SOI layer (ΔRp), 820 ... SOI substrate, 1101 ... first Si wafer, 1102 ... oxide film layer, 1103 ... Peak range (Rp) of ion implantation, 1104... Second Si wafer, 1105... SOI layer (single crystal silicon layer), 1109.

Claims (10)

Forming a first insulating film on the surface of the Si wafer;
Forming an element on the first insulating film;
Forming a second insulating film on the element and the first insulating film;
Planarizing the second insulating film;
The Si the first to the wafer, by ion implantation definitive in Smart Cut (registered trademark) method through the second insulating film and the element, to form a peak range of the ion implantation to a certain depth in the Si wafer Process,
Attaching a semiconductor wafer to the surface of the second insulating film;
Cutting the Si wafer at a portion of the peak range of the ion implantation;
A method for manufacturing a bonded SOI substrate, comprising:   2. The method for manufacturing a bonded SOI substrate according to claim 1, wherein the second insulating film in the step of forming the second insulating film is formed by a CVD method. Providing a step on the surface of the Si wafer by forming a polishing stopper layer made of a material other than Si on the surface of the Si wafer;
Providing an element between the polishing stopper layers; providing an insulating film on the element and the polishing stopper layer;
Planarizing the insulating film;
Forming a peak range of the ion implantation in the Si wafer by performing ion implantation in the Smart Cut (registered trademark) method through the insulating film and the polishing stopper layer to the Si wafer;
Attaching a semiconductor wafer to the surface of the insulating film;
Cutting the Si wafer at a portion of the peak range of the ion implantation;
Chemically polishing the surface of the Si wafer after cutting with an alkaline polishing liquid containing no abrasive grains using the polishing stopper layer as a stopper;
A method for manufacturing a bonded SOI substrate, comprising:   4. The method for manufacturing a bonded SOI substrate according to claim 3, wherein in the step of providing the step, the polishing stopper layer is formed by a LOCOS method. Providing a step on the surface of the Si wafer by etching away a part of the surface of the Si wafer by dry etching;
A step of forming a polishing stopper layer made of a material other than Si on the stepped portion, a step of providing an element between the polishing stopper layers,
Providing an insulating film on the element and the polishing stopper layer;
Planarizing the insulating film;
Forming a peak range of the ion implantation in the Si wafer by performing ion implantation in the Smart Cut (registered trademark) method through the insulating film and the polishing stopper layer to the Si wafer;
Attaching a semiconductor wafer to the surface of the insulating film;
Cutting the Si wafer at a portion of the peak range of the ion implantation;
Chemically polishing the surface of the Si wafer after cutting with an alkaline polishing liquid containing no abrasive grains using the polishing stopper layer as a stopper;
A method for manufacturing a bonded SOI substrate, comprising:   6. The method for manufacturing a bonded SOI substrate according to claim 1, wherein a CMP method is used as a flattening means in the flattening step.   6. The method for manufacturing a bonded SOI substrate according to claim 3, wherein the insulating film in the step of providing the insulating film is formed by a CVD method.   6. The method for manufacturing a bonded SOI substrate according to claim 1, wherein the element is a back gate electrode, a wiring, a resistor, or a capacitor.   6. The method for manufacturing a bonded SOI substrate according to claim 3, wherein an SOI layer is selectively formed only in an active region of the MOS transistor by the chemical polishing step.   Polishing selection ratio in the above-described chemical polishing step (where the polishing selection ratio is Rsi / Rsoi, and Rsi is the film reduction rate of the silicon substrate in chemical polishing when the entire polishing surface is a silicon substrate) 6. The bonded SOI substrate according to claim 3, wherein Rsoi is a film reduction rate of the SOI layer remaining between the polishing stopper layers when polishing reaches the polishing stopper layer. Manufacturing method.

Images