JP4476390B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP4476390B2
JP4476390B2 JP23496399A JP23496399A JP4476390B2 JP 4476390 B2 JP4476390 B2 JP 4476390B2 JP 23496399 A JP23496399 A JP 23496399A JP 23496399 A JP23496399 A JP 23496399A JP 4476390 B2 JP4476390 B2 JP 4476390B2
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layer
substrate
crystal
silicon
crystal semiconductor
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JP2000150905A (en
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久 大谷
舜平 山崎
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株式会社半導体エネルギー研究所
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/1262Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • H01L29/66772Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/973Substrate orientation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate

Description

【0001】
【発明が属する技術分野】
本願発明はSOI(Silicon on Insulator)基板を用いて作製した半導体装置及びその作製方法に関する。具体的にはSOI基板上に形成された薄膜トランジスタ(以下、TFTと呼ぶ)を含む半導体装置に関する。
【0002】
なお、本明細書中において半導体装置とは半導体特性を利用することで機能しうる装置全般を指す。従って、TFTのみならず、液晶表示装置や光電変換装置に代表される電気光学装置、TFTを集積化した半導体回路、またその様な電気光学装置や半導体回路を部品として用いた電子機器も半導体装置に含む。
【0003】
【従来の技術】
近年、VLSI技術が飛躍的な進歩を遂げる中で低消費電力を実現するSOI(Silicon on Insulator)構造が注目されている。この技術は従来バルク単結晶シリコンで形成されていたFETの活性領域(チャネル形成領域)を、薄膜単結晶シリコンとする技術である。
【0004】
SOI基板では単結晶シリコン上に酸化シリコンでなる埋め込み酸化膜が存在し、その上に単結晶シリコン薄膜が形成される。この様なSOI基板の作製方法は様々な方法が知られている。代表的なものとしてはSIMOX基板が知られている。SIMOXとは、「Separation-by-Implanted Oxygen」の略であり、単結晶シリコン基板中に酸素をイオン注入して埋め込み酸化層を形成する。SIMOX基板に関する詳細は、「K.Izumi,M.Doken and H.Ariyoshi:“C.M.O.S. devices fabrication on buried SiO2 layers formed by oxygen implantation into silicon”,Electron.Lett.,14,593-594 (1978)」に詳しい。
【0005】
また、最近では貼り合わせSOI基板も注目されている。貼り合わせSOI基板とは、その名の通り2枚のシリコン基板を貼り合わせることでSOI構造を実現するものである。この技術を用いればセラミックス基板などの上にも単結晶シリコン薄膜を形成できる。
【0006】
その貼り合わせSOI基板の中でも最近特に注目されているものの一つにELTRAN(キャノン株式会社の登録商標)と呼ばれる技術がある。この技術は多孔質シリコン層の選択性エッチングを利用したSOI基板の作製方法である。ELTRAN法の詳細な技術に関しては、「K.Sakaguchi et al.,"Current Progress in Epitaxial Layer Transfer (ELTRAN)",IEICE TRANS.ELECTRON,VOL.E80 C,NO.3,pp378-387,March 1997」に詳しい。
【0007】
また、他に注目されているSOI技術にSmart-Cut(SOITEC社の登録商標)がある。Smart-Cut法は1996年にフランスのSOITEC社で開発された技術であり、水素脆化を利用した貼り合わせSOI基板の作製方法である。Smart-Cut法の詳細な技術に関しては、「工業調査会,電子材料8月号,pp.83〜87 (1997)」に詳しい。
【0008】
【発明が解決しようとする課題】
前述のSOI基板を作製する際には、いずれも主表面(素子が形成される面)の結晶面が{100}面(結晶方位が〈100〉配向)である単結晶シリコン基板が用いられている。これは{100}面が最も界面準位密度(Qss)が小さく、界面特性に敏感な電界効果トランジスタに適しているからである。
【0009】
しかしながら、TFTに用いるためのSOI基板は絶縁層上に単結晶シリコン薄膜を形成する必要があるため、界面準位密度よりも絶縁層との密着性を第一に優先させる必要がある。即ち、いくら界面準位密度が小さいからといって単結晶シリコン薄膜が剥がれてしまっては意味がないのである。
【0010】
本願発明はこのような問題点を鑑みてなされたものであり、TFTに適したSOI基板を作製し、その上に形成されたTFTでもって信頼性の高い半導体装置を実現することを課題としている。
【0011】
【課題を解決するための手段】
本明細書で開示する発明の構成は、
主表面が{110}面である単結晶半導体基板中に水素含有層を形成する工程と、
前記単結晶半導体基板と支持基板とを貼り合わせる工程と、
第1熱処理により前記単結晶半導体基板を前記水素含有層に沿って分断する工程と、
900〜1200℃の温度で第2熱処理を行う工程と、
前記支持基板の上の主表面が{110}面である単結晶半導体層を研削する工程と、
前記単結晶半導体層を活性層とする複数のTFTを形成する工程と、
を含むことを特徴とする。
【0012】
また、他の発明の構成は、
主表面が{110}面である単結晶半導体基板を陽極化成して多孔質半導体層を形成する工程と、
前記多孔質半導体層に対して還元雰囲気中で第1熱処理を行う工程と、
前記多孔質半導体層上に主表面が{110}面である単結晶半導体層をエピタキシャル成長させる工程と、
前記単結晶半導体基板と支持基板とを貼り合わせる工程と、
900〜1200℃の温度で第2熱処理を行う工程と、
前記多孔質半導体層を露呈させる工程と、
前記多孔質半導体層を除去し、前記単結晶半導体層を露呈させる工程と、
前記支持基板の上に、前記単結晶半導体層を活性層とする複数のTFTを形成する工程と、
を含むことを特徴とする。
【0013】
また、他の発明の構成は、
主表面が{110}面である単結晶半導体基板中に酸素含有層を形成する工程と、
前記酸素含有層を形成した単結晶半導体基板に対して800〜1200℃で熱処理を施す工程と、
前記酸素含有層の上に形成された主表面が{110}面である単結晶半導体層を活性層とする複数のTFTを形成する工程と、
を含むことを特徴とする。
【0014】
本願発明の趣旨は、SIMOX、ELTRAN、Smart-CutといったSOI技術を用いてSOI基板を作製するにあたって、最終的に支持基板上に形成される単結晶半導体層の形成材料として、主表面が{110}面である(結晶面が{110}面である)単結晶半導体基板を用いることにある。
【0015】
なお、ここでいう半導体とは代表的にはシリコンを指すが、シリコンゲルマニウムなどの他の半導体も含む。
【0016】
本願発明において、単結晶半導体層の形成材料として主表面が{110}面である単結晶半導体基板を用いる理由を以下に説明する。なお、この説明は単結晶シリコンを例にして行う。
【0017】
なお、単結晶シリコンとしてはFZ法で形成されたものとCZ法で形成されたものとがあるが、本願発明ではFZ法で形成された単結晶シリコンを用いた方が好ましい。現在主流となっているCZ法は応力緩和を目的として2×1018atoms/cm3程度の酸素を含むため、電子や正孔の移動度が低下する恐れがある。特に微細なTFTを形成する場合にはこのことが顕著に現れる様になる。
【0018】
しかしながら、本願発明の様なSOI基板に用いる場合、TFTの活性層として必要とする単結晶シリコン層の膜厚は10〜50nmと極めて薄い場合が多いので応力をあまり考慮する必要がなく、安価なCZ法よりも安価に単結晶シリコンを作製できるFZ法(含有酸素濃度は1×1017atoms/cm3以下)を用いても十分な効果を得ることができる。
【0019】
また、一般的なSOI基板は酸化シリコン層の上に単結晶シリコン層が形成されている。従って、酸化シリコン層と単結晶シリコン層との密着性や整合性が重要となる。そういう観点から見ると、SOI基板においては酸化シリコン層と接する時に最も安定な面で単結晶シリコン層が接しているのが理想的である。
【0020】
酸化シリコン層と最も安定に接する面は{110}面である。なぜならば、{110}面の場合には酸化シリコン層に対して3つのシリコン原子で接するからである。この状態を図8に示す写真を用いて説明する。
【0021】
図8(A)に示した写真は、単結晶シリコンの単位格子が二つ並んだ状態を示している結晶構造モデルである。ここで注目すべきは図中の矢印で示す部分である。矢印で示した部分には3つのシリコン原子が並んでいる。この3つのシリコン原子はどれも{110}面の面内に含まれている。
【0022】
即ち、結晶面が{110}面である単結晶シリコン層を絶縁層上に形成すると、絶縁層と接合するシリコン原子は3つとなることが判る。
【0023】
また、図8(A)を、角度を変えて見た写真を図8(B)に示す。図8(B)において矢印で示す部分に3つのシリコン原子が存在するが、これらは図8(A)にて矢印で示した3つのシリコン原子と同一のものである。
【0024】
この様に、3つのシリコン原子は{110}面に含まれ、且つ、概略三角形状に隣接して配置されていることが判る。即ち、この様な配置状態で下地となる絶縁層に接合し、「面」で接した安定な接合を形成している。この事は、単結晶シリコン層と下地となる絶縁層とが非常に高い密着性をもって接合されていることを示している。
【0025】
一方で、例えば{100}面や{111}面といった他の面で酸化シリコン層に接した場合、酸化シリコン層に接するのは最大で2つのシリコン原子であり、「線」で接した不安定な接合を形成する。
【0026】
さらに、主表面が{110}面である単結晶シリコン層を用いる大きなメリットとしては、シリコン表面が非常に平坦であることが挙げられる。主表面が{110}面である場合、劈開面は層状に現れる様になっており、非常に凹凸の少ない表面を形成することが可能である。
【0027】
この様に、本願発明ではSOI基板において単結晶シリコン層の下地(酸化シリコン層)への密着性を第一に考え、従来用いられなかった{110}面を結晶面とする単結晶シリコン基板を用いる点に特徴がある。即ち、主表面(結晶面)が{110}面である単結晶半導体基板を材料としてSIMOX、ELTRAN、Smart-CutといったSOI技術を駆使し、信頼性の高いSOI基板を形成することに特徴がある。なお、主表面が{110}面である単結晶半導体基板のオリエンタルフラットは{111}面とすれば良い。
【0028】
そして、その様なSOI基板を用いて単結晶半導体薄膜を活性層とする複数のTFTを同一基板上に形成し、信頼性の高い半導体装置を実現する。
【0029】
【発明の実施の形態】
本願発明の実施の形態について、以下に記載する実施例でもって詳細な説明を行うこととする。
【0030】
【実施例】
(実施例1)
本実施例ではSmart-Cut法でSOI基板を作製するにあたって主表面が{110}面である単結晶シリコン基板を用い、そのSOI基板を用いて半導体装置を作製する場合について図1を用いて説明する。
【0031】
まず、単結晶シリコン層の形成材料となる単結晶シリコン基板101を用意する。ここでは主表面の結晶面が{110}面であるP型基板を用いるが、N型であっても良い。勿論、単結晶シリコンゲルマニウム基板を用いることもできる。
【0032】
次いで熱酸化処理を行い、その主表面(素子形成面に相当する)に酸化シリコン膜102を形成する。膜厚は実施者が適宜決定すれば良いが、10〜500nm(代表的には20〜50nm)とすれば良い。この酸化シリコン膜102は後にSOI基板の埋め込み絶縁層の一部として機能する。(図1(A))
【0033】
この時、単結晶シリコン基板101と酸化シリコン膜102の界面の密着性は非常に高いものとなる。これは本願発明では{110}面上に酸化シリコン膜102を形成するため、非常に整合性の高い界面が実現されるからである。この界面は最終的にTFTとなった時、活性層と下地膜との界面であるため、密着性(整合性)が高いことは非常に有利である。
【0034】
また、酸化シリコン膜102の膜厚を20〜50nmと薄くすることが可能であるのは、単結晶シリコン基板101の結晶面が{110}面であるため、薄くても密着性の高い酸化シリコン膜が形成できるからである。
【0035】
なお、{110}面は酸化反応が進行すると次第にシリコン表面のうねり(凹凸)が大きくなるという問題があるが、本実施例の様に薄い酸化シリコン膜を設ける場合、酸化量が小さいのでその様なうねりの問題を極力排除できる。このことは、本明細書に記載された全ての実施例に共通する利点である。
【0036】
従って、本願発明を用いて作製された単結晶シリコン層は極めて平坦な表面を有する。例えば、うねりの頂点から頂点までの距離は、前述した{110}面に含まれる3つの原子の隣接原子間距離の10倍以下(好ましくは20倍以下)である。即ち、約5nm以下(好ましくは10nm以下)である。
【0037】
次に、単結晶シリコン基板101の主表面側から酸化シリコン膜102を通して水素を添加する。この場合、水素イオンの形でイオンインプランテーション法を用いて水素添加を行えば良い。勿論、水素の添加工程を他の手段で行うことも可能である。こうして水素含有層103が形成される。本実施例では水素イオンを1×1016〜1×1017atoms/cm2のドーズ量で添加する。(図1(B))
【0038】
なお、水素含有層103が形成される深さは後に単結晶シリコン層の膜厚を決定するため、精密な制御が必要である。本実施例では単結晶シリコン基板101の主表面と水素含有層103との間に50nm厚の単結晶シリコン層が残る様に水素添加プロファイルの深さ方向の制御を行っている。
【0039】
また、{110}面は原子密度が最も小さな面であるため、水素イオンを添加してもシリコン原子との衝突確率が最も小さい。即ち、イオン添加する際のダメージを最小限に抑えることが可能である。
【0040】
次に、単結晶シリコン基板101と支持基板とを貼り合わせる。本実施例では支持基板としてシリコン基板104を用い、その表面には貼り合わせ用の酸化シリコン膜105を設けておく。なお、シリコン基板104としてはFZ法で形成された安価なシリコン基板を用意すれば十分である。勿論、多結晶シリコン基板であっても構わない。また、平坦性さえ確保できれば石英基板、セラミックス基板、結晶化ガラス基板などの高耐熱性基板を用いても良い。(図1(C))
【0041】
この時、貼り合わせ界面は親水性の高い酸化シリコン膜同士となるので、両表面に含まれた水分の反応により水素結合で接着される。
【0042】
次に、400〜600℃(典型的には500℃)の熱処理(第1熱処理)を行う。この熱処理により水素含有層103では微小空乏の体積変化が起こり、水素含有層103に沿って破断面が発生する。これにより単結晶シリコン基板101は分断され、支持基板の上には酸化シリコン膜102と単結晶シリコン層106が残される。(図1(D))
【0043】
次に、第2熱処理工程として1050〜1150℃の温度範囲でファーネスアニール工程を行う。この工程では貼り合わせ界面において、Si-O-Si結合の応力緩和が起こり、貼り合わせ界面が安定化する。即ち、単結晶シリコン層106を支持基板上に完全に接着させるための工程となる。本実施例ではこの工程を1100℃、2時間で行う。
【0044】
こうして貼り合わせ界面が安定化することで埋め込み絶縁層107が画定する。なお、図1(E)において埋め込み絶縁層107中の点線は、貼り合わせ界面を示しており、界面が強固に接着されたことを意味している。
【0045】
次に、単結晶シリコン層106の表面を平坦化する。平坦化にはCMP(ケミカルメカニカルポリッシング)と呼ばれる研磨工程や還元雰囲気中で高温(900〜1200℃程度)のファーネスアニール処理を行えば良い。
【0046】
最終的な単結晶シリコン層106の膜厚は10〜200nm(好ましくは20〜100nm)とすれば良い。
【0047】
次に、単結晶シリコン層106をパターニングして、後にTFTの活性層となる島状シリコン層108を形成する。なお、本実施例では一つの島状シリコン層しか記載していないが、同一基板上に複数個が形成される。(図1(F))
【0048】
以上の様にして、主表面が{110}面である島状シリコン層108が得られる。本願発明はこうして得られた島状シリコン層をTFTの活性層として用い、同一基板上に複数のTFTを形成することに特徴がある。
【0049】
次に、TFTの形成方法について図2を用いて説明する。まず、図1(F)の状態までを完成させる。なお、図2(A)において、支持基板201は実際には図1のシリコン基板104と埋め込み絶縁層107とに区別されるが、簡易的に一体化した状態で示す。また、図2(A)の島状シリコン層202が図1(F)の島状シリコン層108に相当する。
【0050】
次に、熱酸化工程を行って島状シリコン層202の表面に10nm厚の酸化シリコン膜203を形成する。この酸化シリコン膜203はゲート絶縁膜として機能する。ゲート絶縁膜203を形成したら、その上に導電性を有するポリシリコン膜を形成し、パターニングによりゲート配線204を形成する。(図2(A))
【0051】
なお、本実施例ではゲート配線としてN型導電性を持たせたポリシリコン膜を利用するが、材料はこれに限定されるものではない。特に、ゲート配線の抵抗を下げるにはタンタル、タンタル合金又はタンタルと窒化タンタルとの積層膜等の金属膜を用いることも有効である。さらに低抵抗なゲート配線を狙うならば銅や銅合金を用いても有効である。
【0052】
図2(A)の状態が得られたら、N型導電性又はP型導電性を付与する不純物を添加して不純物領域205を形成する。この時の不純物濃度で後にLDD領域の不純物濃度が決定する。本実施例では1×1018atoms/cm3の濃度で砒素を添加するが、不純物も濃度も本実施例に限定される必要はない。
【0053】
次に、ゲート配線の表面に5〜10nm程度の薄い酸化シリコン膜206を形成する。これは熱酸化法やプラズマ酸化法を用いて形成すれば良い。この酸化シリコン膜206の形成には、次のサイドウォール形成工程でエッチングストッパーとして機能させる目的がある。
【0054】
エッチングストッパーとなる酸化シリコン膜206を形成したら、窒化シリコン膜を形成してエッチバックを行い、サイドウォール207を形成する。こうして図2(B)の状態を得る。
【0055】
なお、本実施例ではサイドウォール207として窒化シリコン膜を用いたが、ポリシリコン膜やアモルファスシリコン膜を用いることもできる。勿論、ゲート配線の材料が変われば、それに応じてサイドウォールとして用いることのできる材料の選択幅も広がることは言うまでもない。
【0056】
次に、再び先程と同一導電型の不純物を添加する。この時に添加する不純物濃度は先程の工程よりも高い濃度とする。本実施例では不純物として砒素を用い、濃度は1×1021atoms/cm3とするがこれに限定する必要はない。この不純物の添加工程によりソース領域208、ドレイン領域209、LDD領域210及びチャネル形成領域211が画定する。(図2(C))
【0057】
こうして各不純物領域が形成されたらファーネスアニール、レーザーアニール又はランプアニール等の手段により不純物の活性化を行う。
【0058】
次に、ゲート配線204、ソース領域208及びドレイン領域209の表面に形成された酸化シリコン膜を除去し、それらの表面を露呈させる。そして、5nm程度のコバルト膜212を形成して熱処理工程を行う。この熱処理によりコバルトとシリコンとの反応が起こり、シリサイド層(コバルトシリサイド層)213が形成される。(図2(D))
【0059】
この技術は公知のサリサイド技術である。従って、コバルトの代わりにチタンやタングステンを用いても構わないし、熱処理条件等は公知技術を参考にすれば良い。本実施例ではランプアニールを用いて熱処理工程を行う。
【0060】
こうしてシリサイド層213を形成したら、コバルト膜212を除去する。その後、1μm厚の層間絶縁膜214を形成する。層間絶縁膜214としては、酸化シリコン膜、窒化シリコン膜もしくは酸化窒化シリコン膜などの無機絶縁膜又はポリイミド、アクリル、ポリアミド、ポリイミドアミド、BCB(ベンゾシクロブテン)などの有機樹脂絶縁膜を用いれば良い。また、これらの無機絶縁膜または有機樹脂絶縁膜を積層しても良い。
【0061】
次に、層間絶縁膜214にコンタクトホールを形成してアルミニウムを主成分とする材料でなるソース配線215及びドレイン配線216を形成する。最後に素子全体に対して水素雰囲気中で300℃2時間のファーネスアニールを行い、水素化を完了する。
【0062】
こうして、図2(E)に示す様なTFTが得られる。なお、本実施例で説明した構造は一例であって本願発明を適用しうるTFT構造はこれに限定されない。従って、公知のあらゆる構造のTFTに対して適用可能である。また、本実施例の工程条件は一例であり、本願発明の本質部分以外は実施者が適宜最適な条件を設定すれば良い。
【0063】
また、本実施例ではNチャネル型TFTを例にとって説明したが、Pチャネル型TFTを作製することも容易である。さらに同一基板上にNチャネル型TFTとPチャネル型TFTとを形成して相補的に組み合わせ、CMOS回路を形成することも可能である。
【0064】
さらに、図2(E)の構造においてドレイン配線216と電気的に接続する画素電極(図示せず)を公知の手段で形成すればアクティブマトリクス型表示装置の画素スイッチング素子を形成することも容易である。
【0065】
即ち、本願発明は液晶表示装置、EL(エレクトロルミネッセンス)表示装置、EC(エレクトロクロミクス)表示装置又は光電変換装置(光センサ)等に代表される電気光学装置の作製方法としても非常に有効な技術である。
【0066】
(実施例2)
本願発明では、主表面が{110}面である単結晶シリコン基板を用いて実施例1とは異なるSOI基板を作製し、それを用いて半導体装置を作製した場合例について説明する。具体的にはELTRANと呼ばれる技術を用いる場合を説明する。
【0067】
まず、主表面(結晶面)が{110}面である単結晶シリコン基板301を用意する。次に、その主表面を陽極化成することにより多孔質シリコン層302を形成する。陽極化成工程はフッ酸とエタノールの混合溶液中で行えば良い。多孔質シリコン層302は柱状の表面孔が表面密度にして1011個/cm3程度設けられた単結晶シリコン層と考えられ、単結晶シリコン基板301の結晶状態(配向性等)をそのまま受け継ぐ。なお、ELTRAN法自体が公知であるので詳細な説明はここでは省略する。
【0068】
そして、その多孔質シリコン層302を形成したら、還元雰囲気中で900〜1200℃(好ましくは1000〜1150℃)の温度範囲の熱処理工程を行ことが好ましい。本実施例では水素雰囲気中で1050℃、2時間の加熱処理を行う。
【0069】
還元雰囲気としては水素雰囲気、アンモニア雰囲気、水素又はアンモニアを含む不活性雰囲気(水素と窒素又は水素とアルゴンの混合雰囲気など)が望ましいが、不活性雰囲気でも結晶性珪素膜の表面の平坦化は可能である。しかし、還元作用を利用して自然酸化膜の還元を行うとエネルギーの高いシリコン原子が多く発生し、結果的に平坦化効果が高まるので好ましい。
【0070】
ただし、特に注意が必要なのは雰囲気中に含まれる酸素又は酸素化合物(例えばOH基)の濃度を10ppm以下(好ましくは1ppm以下)にしておくことである。さもないと水素による還元反応が起こらなくなってしまう。
【0071】
この時、多孔質シリコン層302の表面近傍では表面孔がシリコン原子の移動によって閉塞され、非常に平坦なシリコン表面が得られる。
【0072】
次に、多孔質シリコン層302上に単結晶シリコン層303をエピタキシャル成長させる。この時、エピタキシャル成長させた単結晶シリコン層303は単結晶シリコン基板301の結晶構造をそのまま反映するので、主表面が{110}面となる。また、膜厚は10〜200nm(好ましくは20〜100nm)とすれば良い。(図3(A))
【0073】
次に、単結晶シリコン層303を酸化して酸化シリコン層304を形成する。形成方法としては、熱酸化、プラズマ酸化、レーザー酸化などを用いることが可能である。このとき、単結晶シリコン層305が残存する。(図3(B))
【0074】
次に、支持基板として表面に酸化シリコン層を設けた多結晶シリコン基板306を用意する。勿論、表面に絶縁膜を設けたセラミックス基板、石英基板、ガラスセラミックス基板を用いても良い。
【0075】
こうして単結晶シリコン基板301と支持基板(多結晶シリコン基板306)の準備が完了したら、互いの主表面を向かい合わせる形で両基板を貼り合わせる。この場合、互いの基板に設けられた酸化シリコン層が接着剤の役目を果たす。(図3(C))
【0076】
貼り合わせが終了したら、次に1050〜1150℃の温度で熱処理工程を行い、酸化シリコン同士でなる貼り合わせ界面の安定化を行う。本実施例ではこの熱処理工程を1100℃、2時間で行う。なお、図3(C)において点線で示されているのは完全に接着された貼り合わせ界面である。また、両基板に設けられた酸化シリコン層は熱処理により一体化して埋め込み絶縁層307となる。
【0077】
次に、CMP等の機械的な研磨により単結晶シリコン基板301を裏面側から研削し、多孔質シリコン層302が露呈したところで研削工程を終了する。こうして図3(D)の状態を得る。
【0078】
次に、多孔質シリコン層302をウェットエッチングして選択的に除去する。用いるエッチャントはフッ酸水溶液と過酸化水素水溶液との混合溶液が良い。49%HFと30%H22を1:5で混合した溶液は、単結晶シリコン層と多孔質シリコン層との間で10万倍以上の選択比を持つことが報告されている。
【0079】
こうして図3(E)の状態が得られる。この状態では多結晶シリコン基板306上に埋め込み絶縁層307が設けられ、その上に単結晶シリコン層308が形成されている。
【0080】
この時点でSOI基板は完成しているのだが、単結晶シリコン層308の表面には微小な凹凸が存在するので、水素雰囲気中で熱処理工程を行い、平坦化を施すことが望ましい。この平坦化現象は前述した様に自然酸化膜を還元することによるシリコン原子の増速表面拡散によるものである。
【0081】
なおこの時、水素原子によって単結晶シリコン層308中に含まれるボロン(P型シリコン基板に含まれていたもの)が気相中へと離脱する効果もあるので不純物の低減にも有効である。
【0082】
次に、得られた単結晶シリコン層308をパターニングして島状シリコン層309を形成する。なお、図面上では一つしか記載していないが、複数個を形成しても良いことは言うまでもない。
【0083】
この後は、実施例1において図2を用いて説明したのと同様の工程によってTFTを作製することができる。また、他の公知の手段を用いてTFTを形成しても良い。本実施例では詳細な説明を省略する。
【0084】
(実施例3)
本願発明では、主表面が{110}面である単結晶シリコン基板を用いて実施例1、実施例2とは異なるSOI基板を作製し、それを用いて半導体装置を作製した場合例について説明する。具体的にはSIMOXと呼ばれるSOI基板を作製する場合を説明する。
【0085】
図4(A)において、401は単結晶シリコン基板である。本実施例では、まず単結晶シリコン基板401に対して酸素イオンを添加し、所定の深さに酸素含有層402を形成する。酸素イオンは1×1018atoms/cm2程度のドーズ量で添加すれば良い。
【0086】
また、この時、{110}面は原子密度が小さいため、酸素イオンとシリコン原子との衝突確率は小さいものとなる。即ち、酸素を添加することによるシリコン表面のダメージを最小限に抑えることができる。勿論、イオン添加中に基板温度を400〜600℃にすることでさらにダメージを低減することができる。
【0087】
次に、800〜1200℃の温度で熱処理を行い、酸素含有層402を埋め込み絶縁層403に変化させる。酸素含有層402の深さ方向の幅はイオン添加時の酸素イオンの分布で決まっており、裾をひくような分布を持っているが、この熱処理工程により単結晶シリコン基板401と埋め込み絶縁層403との界面は非常に急峻なものとなる。(図4(B))
【0088】
この埋め込み絶縁層403の膜厚は10〜500nm(代表的には20〜50nm)とする。20〜50nmといった薄い埋め込み絶縁層を実現できるのは単結晶シリコン基板401と埋め込み絶縁層403の界面が安定に接合されているからであり、それは主表面が{110}面である単結晶シリコン基板を単結晶シリコン層の形成材料として用いるからに他ならない。
【0089】
こうして埋め込み絶縁層403が形成されると、埋め込み絶縁層403の上には単結晶シリコン層404が残存する。即ち、本実施例では主表面が{110}面である単結晶シリコン基板を用いるため、埋め込み絶縁層を形成した後に得られる単結晶シリコン層404も主表面(結晶面)が{110}面となる。なお、単結晶シリコン層404の膜厚は10〜200nm(好ましくは20〜100nm)となる様に調節すれば良い。
【0090】
こうして単結晶シリコン層404が得られたら、パターニングして島状シリコン層405を得る。島状シリコン層は複数形成しても構わない。
【0091】
この後は、実施例1において図2で説明した工程に従って複数のTFTを完成すれば良い。また、他の公知の手段を用いてTFTを形成しても良い。本実施例では詳細な説明を省略する。
【0092】
(実施例4)
本実施例では、本願発明の半導体装置として反射型液晶表示装置の例を図5に示す。画素TFT(画素スイッチング素子)の作製方法やセル組工程は公知の手段を用いれば良いので詳細な説明は省略する。
【0093】
図5(A)において11は絶縁表面を有する基板、12は画素マトリクス回路、13はソースドライバー回路、14はゲイトドライバー回路、15は対向基板、16はFPC(フレキシブルプリントサーキット)、17は信号処理回路である。信号処理回路17としては、D/Aコンバータ、γ補正回路、信号分割回路などの従来ICで代用していた様な処理を行う回路を形成することができる。勿論、ガラス基板上にICチップを設けて、ICチップ上で信号処理を行うことも可能である。
【0094】
さらに、本実施例では液晶表示装置を例に挙げて説明しているが、アクティブマトリクス型の表示装置であればEL(エレクトロルミネッセンス)表示装置やEC(エレクトロクロミックス)表示装置などの他の電気光学装置に本願発明を用いることも可能である。
【0095】
ここで図5(A)のドライバー回路13、14を構成する回路の一例を図5(B)に示す。なお、TFT部分については既に実施例1で説明しているので、ここでは必要箇所のみの説明を行うこととする。
【0096】
図5(B)において、501、502はNチャネル型TFT、503はPチャネル型TFTであり、501と503のTFTでCMOS回路を構成している。504は窒化シリコン膜/酸化シリコン膜/樹脂膜の積層膜でなる絶縁層、その上にはチタン配線505が設けられ、前述のCMOS回路とTFT502とが電気的に接続されている。チタン配線はさらに樹脂膜でなる絶縁層506で覆われている。二つの絶縁層504、506は平坦化膜としての機能も有している。
【0097】
また、図5(A)の画素マトリクス回路12を構成する回路の一部を図5(C)に示す。図5(C)において、507はダブルゲート構造のNチャネル型TFTでなる画素TFTであり、画素領域内に大きく広がる様にしてドレイン配線508が形成されている。
【0098】
その上には絶縁層504が設けられ、その上にチタン配線505が設けられている。この時、絶縁層504の一部には凹部が落とし込み部が形成され、最下層の窒化シリコン及び酸化シリコンのみが残される。これによりドレイン配線508とチタン配線505との間で補助容量が形成される。
【0099】
また、画素マトリクス回路内に設けられたチタン配線505はソース・ドレイン配線と後の画素電極との間において電界遮蔽効果をもたらす。さらに、複数設けられた画素電極間の隙間ではブラックマスクとしても機能する。
【0100】
そして、チタン配線505を覆って絶縁層506が設けられ、その上に反射性導電膜でなる画素電極509が形成される。勿論、画素電極509の表面に反射率を上げるための工夫をなしても構わない。
【0101】
また、実際には画素電極509の上に配向膜や液晶層が設けられるが、ここでの説明は省略する。
【0102】
本願発明を用いて以上の様な構成でなる反射型液晶表示装置を作製することができる。勿論、公知の技術と組み合わせれば容易に透過型液晶表示装置(但し、支持基板として透光性基板を用いた場合に限る)を作製することもできる。さらに、公知の技術と組み合わせればアクティブマトリクス型のEL表示装置も容易に作製することができる。
【0103】
なお、本実施例の電気光学装置を作製するにあたって、実施例1〜実施例3のいずれのSOI基板を用いても構わない。
【0104】
(実施例5)
本願発明は従来のIC技術全般に適用することが可能である。即ち、現在市場に流通している全ての半導体回路に適用できる。例えば、ワンチップ上に集積化されたRISCプロセッサ、ASICプロセッサ等のマイクロプロセッサに適用しても良いし、D/Aコンバータ等の信号処理回路から携帯機器(携帯電話、PHS、モバイルコンピュータ)用の高周波回路に適用しても良い。
【0105】
図6に示すのは、マイクロプロセッサの一例である。マイクロプロセッサは典型的にはCPUコア21、RAM22、クロックコントローラ23、キャッシュメモリー24、キャッシュコントローラ25、シリアルインターフェース26、I/Oポート27等から構成される。
【0106】
勿論、図6に示すマイクロプロセッサは簡略化した一例であり、実際のマイクロプロセッサはその用途によって多種多様な回路設計が行われる。
【0107】
しかし、どの様な機能を有するマイクロプロセッサであっても中枢として機能するのはIC(Integrated Circuit)28である。IC28は半導体チップ29上に形成された集積化回路をセラミック等で保護した機能回路である。
【0108】
そして、その半導体チップ29上に形成された集積化回路(半導体回路)を構成するのが本願発明の構造を有するNチャネル型TFT30、Pチャネル型TFT31である。なお、基本的な回路はCMOS回路を最小単位として構成することで消費電力を抑えることができる。
【0109】
また、本実施例に示したマイクロプロセッサは様々な電子機器に搭載されて中枢回路として機能する。代表的な電子機器としてはパーソナルコンピュータ、携帯型情報端末機器、その他あらゆる家電製品が挙げられる。また、車両(自動車や電車等)の制御用コンピュータなども挙げられる。
【0110】
なお、本実施例の半導体回路を作製するにあたって、実施例1〜実施例3のいずれのSOI基板を用いても構わない。
【0111】
(実施例6)
実施例4に示した電気光学装置や実施例5に示した半導体回路は、様々な電子機器に用いることができる。その様な電子機器としては、ビデオカメラ、デジタルカメラ、プロジェクター、プロジェクションTV、TV用ディスプレイ、パーソナルコンピュータ用ディスプレイ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、カーナビゲーション、パーソナルコンピュータ、画像再生装置(DVDプレイヤー、CDプレイヤー、MDプレイヤー等)、携帯情報端末(モバイルコンピュータ、携帯電話、電子書籍等)などが挙げられる。それらの一例を図7に示す。
【0112】
図7(A)は携帯電話であり、本体2001、音声出力部2002、音声入力部2003、表示装置2004、操作スイッチ2005、アンテナ2006で構成される。本願発明を音声出力部2002、音声入力部2003、表示装置2004やその他の信号制御回路に適用することができる。
【0113】
図7(B)はビデオカメラであり、本体2101、表示装置2102、音声入力部2103、操作スイッチ2104、バッテリー2105、受像部2106で構成される。本願発明を表示装置2102、音声入力部2103やその他の信号制御回路に適用することができる。
【0114】
図7(C)はモバイルコンピュータ(モービルコンピュータ)であり、本体2201、カメラ部2202、受像部2203、操作スイッチ2204、表示装置2205で構成される。本願発明は表示装置2205やその他の信号制御回路に適用できる。
【0115】
図7(D)はパーソナルコンピュータであり、本体2301、受像部2302、表示装置2303、キーボード2304等で構成される。本願発明は表示装置2304やその他の信号制御回路に用いることができる。
【0116】
図7(E)はリア型プロジェクターであり、本体2401、光源2402、表示装置2403、偏光ビームスプリッタ2404、リフレクター2405、2406、スクリーン2407で構成される。本発明は表示装置2403やその他の信号制御回路に適用することができる。
【0117】
図7(F)は電子書籍であり、本体2501、表示装置2502、2503、記憶媒体2504、操作スイッチ2505、アンテナ2506で構成される。本発明は表示装置2502、2503やその他の信号制御回路に適用することができる。
【0118】
以上の様に、本願発明の適用範囲は極めて広く、あらゆる分野の電子機器に用いることが可能である。
【0119】
(実施例7)
本実施例は、実施例2の変形例であり、図3のELTRAN法を用いる際に、多孔質シリコン層302の形成方法を改良した例を示す。
【0120】
図3(A)の工程ではフッ酸とエタノールの混合溶液中で陽極化成処理を行って多孔質シリコン層302を形成している。このとき、陽極化成処理は一定の電流密度で行っているが、本実施例では電流密度を陽極化成処理の途中で切り換えることを特徴とする。
【0121】
具体的には、陽極化成処理の途中で与える電流密度を上げ、それまでに形成された多孔質シリコン層(第1多孔質シリコン層)よりも個々の孔の径が大きい第2の多孔質シリコン層を形成する。
【0122】
本実施例の場合、図3(C)の状態の多孔質シリコン層(第1多孔質シリコン層と第2多孔質シリコン層との積層体)に衝撃を与えると、多孔質シリコン層302は第1多孔質シリコン層と第2多孔質シリコン層との界面に沿って分断される。即ち、図3(D)に示したような研磨工程(研削工程)を行う必要がない。
【0123】
従って、本実施例に従えば、一つのSOI基板を作製するのに二枚の半導体基板を必要としないため、大幅に製造コストを低減することができる。
【0124】
なお、本実施例に従ってSOI基板を作製したら、実施例1の工程に従って、主表面が{110}面の単結晶シリコン層でなる活性層を有するTFTを形成すれば良い。また、本実施例を用いて作製されたTFTは実施例4の電気光学装置または実施例5の半導体回路に用いることができる。また、そうして作製された電気光学装置や半導体回路は、実施例6の電子機器に用いることができる。
【0125】
【発明の効果】
本願発明を実施することで、SOI基板の埋め込み絶縁層と単結晶シリコン層との密着性を高めることができ、SOI基板を用いて作製されたTFTの信頼性を高めることができる。
【0126】
そして、そのTFTを用いて非常に高い信頼性を有する半導体回路を構成することが可能となり、延いては液晶表示装置やそれを搭載したノートパソコンなどの半導体装置の信頼性を高くすることができる。
【図面の簡単な説明】
【図1】 SOI基板の作製工程を示す図。
【図2】 TFTの作製工程を示す図。
【図3】 SOI基板の作製工程を示す図。
【図4】 SOI基板の作製工程を示す図。
【図5】 半導体装置(電気光学装置)の構成を示す図。
【図6】 半導体装置(半導体回路)の構成を示す図。
【図7】 半導体装置(電子機器)の構成を示す図。
【図8】 単結晶シリコンの結晶構造を示す写真。
[0001]
[Technical field to which the invention belongs]
The present invention relates to a semiconductor device manufactured using an SOI (Silicon on Insulator) substrate and a manufacturing method thereof. Specifically, the present invention relates to a semiconductor device including a thin film transistor (hereinafter referred to as a TFT) formed over an SOI substrate.
[0002]
Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Accordingly, not only TFTs but also electro-optical devices typified by liquid crystal display devices and photoelectric conversion devices, semiconductor circuits in which TFTs are integrated, and electronic devices using such electro-optical devices and semiconductor circuits as components are also semiconductor devices. Included.
[0003]
[Prior art]
In recent years, an SOI (Silicon on Insulator) structure that realizes low power consumption has attracted attention as VLSI technology has made great progress. This technique is a technique in which the active region (channel formation region) of an FET that has been conventionally formed of bulk single crystal silicon is thin film single crystal silicon.
[0004]
In an SOI substrate, a buried oxide film made of silicon oxide exists on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods for manufacturing such an SOI substrate are known. A typical example is a SIMOX substrate. SIMOX is an abbreviation for “Separation-by-Implanted Oxygen”, in which oxygen is ion-implanted into a single crystal silicon substrate to form a buried oxide layer. Details regarding the SIMOX substrate are detailed in “K. Izumi, M. Doken and H. Ariyoshi:“ CMOS devices fabrication on buried SiO 2 layers formed by oxygen implantation into silicon ”, Electron. Lett., 14, 593-594 (1978)”.
[0005]
Recently, a bonded SOI substrate has also attracted attention. A bonded SOI substrate, as its name suggests, realizes an SOI structure by bonding two silicon substrates. By using this technique, a single crystal silicon thin film can be formed on a ceramic substrate or the like.
[0006]
One of the bonded SOI substrates that has recently attracted particular attention is a technique called ELTRAN (registered trademark of Canon Inc.). This technique is a method for manufacturing an SOI substrate using selective etching of a porous silicon layer. For the detailed technology of the ELTRAN method, see “K. Sakaguchi et al.,“ Current Progress in Epitaxial Layer Transfer (ELTRAN) ”, IEICE TRANS. ELECTRON, VOL. E80 C, NO. 3, pp 378-387, March 1997”. Be familiar with.
[0007]
Another SOI technology attracting attention is Smart-Cut (registered trademark of SOITEC). The Smart-Cut method was developed in 1996 by SOITEC, France, and is a method for manufacturing a bonded SOI substrate using hydrogen embrittlement. The detailed technology of the Smart-Cut method is detailed in “Industrial Research Committee, August issue of electronic materials, pp. 83-87 (1997)”.
[0008]
[Problems to be solved by the invention]
When manufacturing the aforementioned SOI substrate, a single crystal silicon substrate in which the crystal surface of the main surface (surface on which an element is formed) is a {100} plane (crystal orientation is <100> orientation) is used. Yes. This is because the {100} plane has the smallest interface state density (Qss) and is suitable for a field effect transistor sensitive to interface characteristics.
[0009]
However, since an SOI substrate for use in a TFT needs to form a single crystal silicon thin film on an insulating layer, it is necessary to give first priority to adhesion with the insulating layer over the interface state density. That is, no matter how small the interface state density is, it does not make sense to peel off the single crystal silicon thin film.
[0010]
The present invention has been made in view of such problems, and it is an object of the present invention to produce an SOI substrate suitable for a TFT and to realize a highly reliable semiconductor device with the TFT formed thereon. .
[0011]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
Forming a hydrogen-containing layer in a single crystal semiconductor substrate whose main surface is a {110} plane;
Bonding the single crystal semiconductor substrate and the support substrate;
Dividing the single crystal semiconductor substrate along the hydrogen-containing layer by a first heat treatment;
Performing a second heat treatment at a temperature of 900 to 1200 ° C .;
Grinding a single crystal semiconductor layer whose main surface on the support substrate is a {110} plane;
Forming a plurality of TFTs having the single crystal semiconductor layer as an active layer;
It is characterized by including.
[0012]
In addition, the configuration of other inventions is as follows:
Forming a porous semiconductor layer by anodizing a single crystal semiconductor substrate whose main surface is a {110} plane;
Performing a first heat treatment on the porous semiconductor layer in a reducing atmosphere;
Epitaxially growing a single crystal semiconductor layer whose main surface is a {110} plane on the porous semiconductor layer;
Bonding the single crystal semiconductor substrate and the support substrate;
Performing a second heat treatment at a temperature of 900 to 1200 ° C .;
Exposing the porous semiconductor layer; and
Removing the porous semiconductor layer and exposing the single crystal semiconductor layer;
Forming a plurality of TFTs having the single crystal semiconductor layer as an active layer on the support substrate;
It is characterized by including.
[0013]
In addition, the configuration of other inventions is as follows:
Forming an oxygen-containing layer in a single crystal semiconductor substrate whose main surface is a {110} plane;
Performing a heat treatment at 800 to 1200 ° C. on the single crystal semiconductor substrate on which the oxygen-containing layer is formed;
Forming a plurality of TFTs having a single crystal semiconductor layer whose main surface formed on the oxygen-containing layer is a {110} plane as an active layer;
It is characterized by including.
[0014]
The gist of the present invention is that when a SOI substrate is manufactured using SOI technology such as SIMOX, ELTRAN, and Smart-Cut, the main surface is {110 as a material for forming a single crystal semiconductor layer finally formed on a support substrate. } Plane (where the crystal plane is the {110} plane).
[0015]
Note that the semiconductor here is typically silicon but includes other semiconductors such as silicon germanium.
[0016]
The reason why a single crystal semiconductor substrate whose main surface is a {110} plane is used as a material for forming a single crystal semiconductor layer in the present invention will be described below. Note that this description is made using single crystal silicon as an example.
[0017]
Single crystal silicon includes those formed by the FZ method and those formed by the CZ method. In the present invention, it is preferable to use single crystal silicon formed by the FZ method. The current mainstream CZ method contains about 2 × 10 18 atoms / cm 3 of oxygen for the purpose of stress relaxation, so that the mobility of electrons and holes may be lowered. This is especially noticeable when a fine TFT is formed.
[0018]
However, when used for an SOI substrate as in the present invention, the film thickness of the single crystal silicon layer required as the active layer of the TFT is often as thin as 10 to 50 nm. A sufficient effect can be obtained even by using the FZ method (containing oxygen concentration is 1 × 10 17 atoms / cm 3 or less) which can produce single crystal silicon at a lower cost than the CZ method.
[0019]
Further, in a general SOI substrate, a single crystal silicon layer is formed on a silicon oxide layer. Therefore, adhesion and consistency between the silicon oxide layer and the single crystal silicon layer are important. From this point of view, it is ideal that the single crystal silicon layer is in contact with the most stable surface in contact with the silicon oxide layer in the SOI substrate.
[0020]
The surface that is in most stable contact with the silicon oxide layer is the {110} surface. This is because in the case of the {110} plane, the silicon oxide layer is in contact with three silicon atoms. This state will be described with reference to the photograph shown in FIG.
[0021]
The photograph shown in FIG. 8A is a crystal structure model showing a state in which two unit crystals of single crystal silicon are arranged. What should be noted here is a portion indicated by an arrow in the figure. Three silicon atoms are lined up in the portion indicated by the arrow. These three silicon atoms are all included in the {110} plane.
[0022]
That is, it is found that when a single crystal silicon layer having a {110} plane is formed on an insulating layer, there are three silicon atoms bonded to the insulating layer.
[0023]
FIG. 8B shows a photograph of FIG. 8A viewed from different angles. In FIG. 8B, there are three silicon atoms in the portion indicated by the arrow, which are the same as the three silicon atoms indicated by the arrow in FIG.
[0024]
Thus, it can be seen that the three silicon atoms are included in the {110} plane and are arranged adjacent to each other in a substantially triangular shape. That is, in such an arrangement state, it is bonded to the underlying insulating layer, and a stable bonding is formed in which the “surface” is in contact. This indicates that the single crystal silicon layer and the underlying insulating layer are bonded with very high adhesion.
[0025]
On the other hand, for example, when the silicon oxide layer is in contact with another surface such as the {100} plane or the {111} plane, the silicon oxide layer is in contact with a maximum of two silicon atoms. A good bond.
[0026]
Furthermore, a great advantage of using a single crystal silicon layer whose main surface is a {110} plane is that the silicon surface is very flat. When the main surface is a {110} plane, the cleavage plane appears to be layered, and a surface with very little unevenness can be formed.
[0027]
As described above, in the present invention, firstly considering the adhesion of the single crystal silicon layer to the base (silicon oxide layer) in the SOI substrate, a single crystal silicon substrate having a {110} plane which is not conventionally used as a crystal plane is used. It is characterized in that it is used. That is, it is characterized in that a highly reliable SOI substrate is formed by making full use of SOI technology such as SIMOX, ELTRAN, and Smart-Cut by using a single crystal semiconductor substrate whose main surface (crystal plane) is {110} plane as a material. . Note that the oriental flat of the single crystal semiconductor substrate whose main surface is the {110} plane may be the {111} plane.
[0028]
Then, using such an SOI substrate, a plurality of TFTs having a single crystal semiconductor thin film as an active layer are formed over the same substrate, thereby realizing a highly reliable semiconductor device.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
The embodiment of the present invention will be described in detail with the examples described below.
[0030]
【Example】
Example 1
In this embodiment, a case where a single crystal silicon substrate whose main surface is a {110} plane is used for manufacturing an SOI substrate by the Smart-Cut method and a semiconductor device is manufactured using the SOI substrate will be described with reference to FIGS. To do.
[0031]
First, a single crystal silicon substrate 101 which is a material for forming a single crystal silicon layer is prepared. Here, a P-type substrate having a {110} plane on the main surface is used, but an N-type substrate may be used. Of course, a single crystal silicon germanium substrate can also be used.
[0032]
Next, thermal oxidation is performed to form a silicon oxide film 102 on the main surface (corresponding to an element formation surface). The film thickness may be appropriately determined by the practitioner, but may be 10 to 500 nm (typically 20 to 50 nm). This silicon oxide film 102 functions later as part of the buried insulating layer of the SOI substrate. (Fig. 1 (A))
[0033]
At this time, the adhesion at the interface between the single crystal silicon substrate 101 and the silicon oxide film 102 is very high. This is because in the present invention, since the silicon oxide film 102 is formed on the {110} plane, a highly consistent interface is realized. Since this interface is the interface between the active layer and the base film when it finally becomes a TFT, it is very advantageous to have high adhesion (coherence).
[0034]
In addition, the silicon oxide film 102 can be thinned to a thickness of 20 to 50 nm because the crystal plane of the single crystal silicon substrate 101 is the {110} plane. This is because a film can be formed.
[0035]
The {110} plane has a problem that the undulation (unevenness) of the silicon surface gradually increases as the oxidation reaction proceeds. However, when a thin silicon oxide film is provided as in this embodiment, the amount of oxidation is small, and so on. The problem of swell can be eliminated as much as possible. This is an advantage common to all the embodiments described herein.
[0036]
Therefore, the single crystal silicon layer manufactured using the present invention has a very flat surface. For example, the distance from the apex of the undulation to the apex is 10 times or less (preferably 20 times or less) the distance between adjacent atoms of three atoms included in the {110} plane described above. That is, it is about 5 nm or less (preferably 10 nm or less).
[0037]
Next, hydrogen is added from the main surface side of the single crystal silicon substrate 101 through the silicon oxide film 102. In this case, hydrogen may be added using an ion implantation method in the form of hydrogen ions. Of course, the hydrogen addition step can be performed by other means. Thus, the hydrogen-containing layer 103 is formed. In this embodiment, hydrogen ions are added at a dose of 1 × 10 16 to 1 × 10 17 atoms / cm 2 . (Fig. 1 (B))
[0038]
Note that the depth at which the hydrogen-containing layer 103 is formed needs to be precisely controlled because it determines the thickness of the single crystal silicon layer later. In this embodiment, the depth direction of the hydrogenation profile is controlled so that a 50 nm thick single crystal silicon layer remains between the main surface of the single crystal silicon substrate 101 and the hydrogen-containing layer 103.
[0039]
Moreover, since the {110} plane has the lowest atomic density, the collision probability with the silicon atom is the lowest even when hydrogen ions are added. That is, it is possible to minimize damage when adding ions.
[0040]
Next, the single crystal silicon substrate 101 and the supporting substrate are attached to each other. In this embodiment, a silicon substrate 104 is used as a support substrate, and a silicon oxide film 105 for bonding is provided on the surface thereof. Note that it is sufficient to prepare an inexpensive silicon substrate formed by the FZ method as the silicon substrate 104. Of course, it may be a polycrystalline silicon substrate. Further, a high heat resistant substrate such as a quartz substrate, a ceramic substrate, or a crystallized glass substrate may be used as long as flatness can be ensured. (Figure 1 (C))
[0041]
At this time, since the bonding interface is made of silicon oxide films having high hydrophilicity, they are bonded by hydrogen bonds by the reaction of moisture contained on both surfaces.
[0042]
Next, a heat treatment (first heat treatment) at 400 to 600 ° C. (typically 500 ° C.) is performed. By this heat treatment, a volume change of microdepletion occurs in the hydrogen-containing layer 103, and a fracture surface is generated along the hydrogen-containing layer 103. Thus, the single crystal silicon substrate 101 is divided, and the silicon oxide film 102 and the single crystal silicon layer 106 are left on the support substrate. (Figure 1 (D))
[0043]
Next, a furnace annealing step is performed in a temperature range of 1050 to 1150 ° C. as a second heat treatment step. In this step, stress relaxation of the Si—O—Si bond occurs at the bonding interface, and the bonding interface is stabilized. That is, this is a process for completely bonding the single crystal silicon layer 106 on the supporting substrate. In this embodiment, this step is performed at 1100 ° C. for 2 hours.
[0044]
Thus, the embedded insulating layer 107 is defined by stabilizing the bonding interface. Note that in FIG. 1E, a dotted line in the buried insulating layer 107 indicates a bonding interface, which means that the interface is firmly bonded.
[0045]
Next, the surface of the single crystal silicon layer 106 is planarized. For planarization, a high temperature (about 900 to 1200 ° C.) furnace annealing treatment may be performed in a polishing process called CMP (Chemical Mechanical Polishing) or in a reducing atmosphere.
[0046]
The final thickness of the single crystal silicon layer 106 may be 10 to 200 nm (preferably 20 to 100 nm).
[0047]
Next, the single crystal silicon layer 106 is patterned to form an island-like silicon layer 108 that will later become an active layer of the TFT. Although only one island-like silicon layer is shown in this embodiment, a plurality of silicon layers are formed on the same substrate. (Fig. 1 (F))
[0048]
As described above, the island-like silicon layer 108 whose main surface is the {110} plane is obtained. The present invention is characterized in that the island-like silicon layer thus obtained is used as an active layer of a TFT and a plurality of TFTs are formed on the same substrate.
[0049]
Next, a method for forming a TFT will be described with reference to FIGS. First, the state up to the state of FIG. In FIG. 2A, the support substrate 201 is actually divided into the silicon substrate 104 and the embedded insulating layer 107 in FIG. Further, the island-shaped silicon layer 202 in FIG. 2A corresponds to the island-shaped silicon layer 108 in FIG.
[0050]
Next, a silicon oxide film 203 having a thickness of 10 nm is formed on the surface of the island-like silicon layer 202 by performing a thermal oxidation process. This silicon oxide film 203 functions as a gate insulating film. After the gate insulating film 203 is formed, a conductive polysilicon film is formed thereon, and a gate wiring 204 is formed by patterning. (Fig. 2 (A))
[0051]
In this embodiment, a polysilicon film having N-type conductivity is used as the gate wiring, but the material is not limited to this. In particular, it is effective to use a metal film such as tantalum, a tantalum alloy, or a laminated film of tantalum and tantalum nitride in order to reduce the resistance of the gate wiring. Furthermore, if a low resistance gate wiring is aimed, it is effective to use copper or a copper alloy.
[0052]
When the state of FIG. 2A is obtained, an impurity region 205 is formed by adding an impurity imparting N-type conductivity or P-type conductivity. The impurity concentration in the LDD region is determined later by the impurity concentration at this time. In this embodiment, arsenic is added at a concentration of 1 × 10 18 atoms / cm 3 , but neither the impurity nor the concentration need be limited to this embodiment.
[0053]
Next, a thin silicon oxide film 206 of about 5 to 10 nm is formed on the surface of the gate wiring. This may be formed using a thermal oxidation method or a plasma oxidation method. The formation of the silicon oxide film 206 has the purpose of functioning as an etching stopper in the next side wall formation step.
[0054]
After the silicon oxide film 206 serving as an etching stopper is formed, a silicon nitride film is formed and etched back to form sidewalls 207. In this way, the state of FIG.
[0055]
In this embodiment, a silicon nitride film is used as the sidewall 207, but a polysilicon film or an amorphous silicon film can also be used. Of course, if the material of the gate wiring changes, it goes without saying that the range of selection of materials that can be used as sidewalls also increases accordingly.
[0056]
Next, an impurity having the same conductivity type as before is added again. The impurity concentration added at this time is higher than that in the previous step. In this embodiment, arsenic is used as an impurity and the concentration is 1 × 10 21 atoms / cm 3 , but it is not necessary to be limited to this. The source region 208, the drain region 209, the LDD region 210, and the channel formation region 211 are defined by this impurity addition step. (Fig. 2 (C))
[0057]
When each impurity region is thus formed, the impurity is activated by means such as furnace annealing, laser annealing or lamp annealing.
[0058]
Next, the silicon oxide film formed on the surfaces of the gate wiring 204, the source region 208, and the drain region 209 is removed to expose the surfaces. Then, a cobalt film 212 of about 5 nm is formed and a heat treatment process is performed. By this heat treatment, a reaction between cobalt and silicon occurs, and a silicide layer (cobalt silicide layer) 213 is formed. (Fig. 2 (D))
[0059]
This technique is a known salicide technique. Therefore, titanium or tungsten may be used instead of cobalt, and heat treatment conditions may be referred to known techniques. In this embodiment, the heat treatment process is performed using lamp annealing.
[0060]
When the silicide layer 213 is thus formed, the cobalt film 212 is removed. Thereafter, an interlayer insulating film 214 having a thickness of 1 μm is formed. As the interlayer insulating film 214, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, or an organic resin insulating film such as polyimide, acrylic, polyamide, polyimide amide, or BCB (benzocyclobutene) may be used. . Further, these inorganic insulating films or organic resin insulating films may be stacked.
[0061]
Next, contact holes are formed in the interlayer insulating film 214 to form source wirings 215 and drain wirings 216 made of a material containing aluminum as a main component. Finally, furnace annealing is performed on the entire device in a hydrogen atmosphere at 300 ° C. for 2 hours to complete the hydrogenation.
[0062]
In this way, a TFT as shown in FIG. 2E is obtained. Note that the structure described in this embodiment is merely an example, and the TFT structure to which the present invention can be applied is not limited thereto. Therefore, it can be applied to TFTs having any known structure. Moreover, the process conditions of a present Example are an example, A practitioner should just set optimal conditions suitably except the essential part of this invention.
[0063]
In this embodiment, an N-channel TFT is described as an example, but a P-channel TFT can be easily manufactured. Further, an N-channel TFT and a P-channel TFT can be formed on the same substrate and complementarily combined to form a CMOS circuit.
[0064]
Further, if a pixel electrode (not shown) electrically connected to the drain wiring 216 in the structure of FIG. 2E is formed by a known means, it is easy to form a pixel switching element of an active matrix display device. is there.
[0065]
That is, the present invention is very effective as a method for manufacturing an electro-optical device represented by a liquid crystal display device, an EL (electroluminescence) display device, an EC (electrochromics) display device, a photoelectric conversion device (photosensor), or the like. Technology.
[0066]
(Example 2)
In the present invention, an example will be described in which an SOI substrate different from that in Example 1 is manufactured using a single crystal silicon substrate having a {110} plane as a main surface, and a semiconductor device is manufactured using the SOI substrate. Specifically, a case where a technique called ELTRAN is used will be described.
[0067]
First, a single crystal silicon substrate 301 whose main surface (crystal plane) is a {110} plane is prepared. Next, the porous silicon layer 302 is formed by anodizing the main surface. The anodizing step may be performed in a mixed solution of hydrofluoric acid and ethanol. The porous silicon layer 302 is considered to be a single crystal silicon layer in which columnar surface holes are provided with a surface density of about 10 11 pieces / cm 3 , and inherits the crystal state (orientation, etc.) of the single crystal silicon substrate 301 as it is. Since the ELTRAN method itself is known, a detailed description is omitted here.
[0068]
When the porous silicon layer 302 is formed, it is preferable to perform a heat treatment step in a temperature range of 900 to 1200 ° C. (preferably 1000 to 1150 ° C.) in a reducing atmosphere. In this embodiment, heat treatment is performed at 1050 ° C. for 2 hours in a hydrogen atmosphere.
[0069]
The reducing atmosphere is preferably a hydrogen atmosphere, an ammonia atmosphere, or an inert atmosphere containing hydrogen or ammonia (such as a mixed atmosphere of hydrogen and nitrogen or hydrogen and argon), but the surface of the crystalline silicon film can be planarized even in an inert atmosphere. It is. However, it is preferable to reduce the natural oxide film by using the reducing action because many silicon atoms with high energy are generated and as a result, the planarization effect is enhanced.
[0070]
However, it is particularly necessary to keep the concentration of oxygen or oxygen compounds (for example, OH groups) in the atmosphere at 10 ppm or less (preferably 1 ppm or less). Otherwise, the hydrogen reduction reaction will not occur.
[0071]
At this time, in the vicinity of the surface of the porous silicon layer 302, the surface holes are blocked by the movement of silicon atoms, and a very flat silicon surface is obtained.
[0072]
Next, the single crystal silicon layer 303 is epitaxially grown on the porous silicon layer 302. At this time, the epitaxially grown single crystal silicon layer 303 reflects the crystal structure of the single crystal silicon substrate 301 as it is, so that the main surface is a {110} plane. The film thickness may be 10 to 200 nm (preferably 20 to 100 nm). (Fig. 3 (A))
[0073]
Next, the single crystal silicon layer 303 is oxidized to form a silicon oxide layer 304. As a formation method, thermal oxidation, plasma oxidation, laser oxidation, or the like can be used. At this time, the single crystal silicon layer 305 remains. (Fig. 3 (B))
[0074]
Next, a polycrystalline silicon substrate 306 having a silicon oxide layer on the surface is prepared as a support substrate. Of course, a ceramic substrate, a quartz substrate, or a glass ceramic substrate provided with an insulating film on the surface may be used.
[0075]
When the preparation of the single crystal silicon substrate 301 and the support substrate (polycrystalline silicon substrate 306) is thus completed, the two substrates are bonded together so that their main surfaces face each other. In this case, the silicon oxide layers provided on the substrates serve as an adhesive. (Figure 3 (C))
[0076]
When the bonding is completed, a heat treatment step is then performed at a temperature of 1050 to 1150 ° C. to stabilize the bonding interface made of silicon oxides. In this embodiment, this heat treatment step is performed at 1100 ° C. for 2 hours. Note that in FIG. 3C, a dotted line indicates a completely bonded bonding interface. Further, the silicon oxide layers provided on both the substrates are integrated by heat treatment to form a buried insulating layer 307.
[0077]
Next, the single crystal silicon substrate 301 is ground from the back side by mechanical polishing such as CMP, and the grinding process is terminated when the porous silicon layer 302 is exposed. In this way, the state of FIG.
[0078]
Next, the porous silicon layer 302 is selectively removed by wet etching. The etchant used is preferably a mixed solution of a hydrofluoric acid aqueous solution and a hydrogen peroxide aqueous solution. It has been reported that a solution in which 49% HF and 30% H 2 O 2 are mixed at a ratio of 1: 5 has a selectivity ratio of 100,000 times or more between the single crystal silicon layer and the porous silicon layer.
[0079]
In this way, the state of FIG. In this state, a buried insulating layer 307 is provided on the polycrystalline silicon substrate 306, and a single crystal silicon layer 308 is formed thereon.
[0080]
Although the SOI substrate is completed at this point, since there are minute irregularities on the surface of the single crystal silicon layer 308, it is desirable to perform planarization by performing a heat treatment step in a hydrogen atmosphere. As described above, this flattening phenomenon is due to accelerated surface diffusion of silicon atoms by reducing the natural oxide film.
[0081]
Note that at this time, boron atoms contained in the single crystal silicon layer 308 by hydrogen atoms (what was contained in the P-type silicon substrate) are also released into the gas phase, which is effective in reducing impurities.
[0082]
Next, the obtained single crystal silicon layer 308 is patterned to form an island-shaped silicon layer 309. Although only one is shown in the drawing, it goes without saying that a plurality may be formed.
[0083]
Thereafter, a TFT can be manufactured by the same process as that described in Embodiment 1 with reference to FIG. Moreover, you may form TFT using another well-known means. Detailed description is omitted in this embodiment.
[0084]
(Example 3)
In the present invention, an example will be described in which an SOI substrate different from those in Embodiments 1 and 2 is manufactured using a single crystal silicon substrate whose main surface is a {110} plane, and a semiconductor device is manufactured using the SOI substrate. . Specifically, a case where an SOI substrate called SIMOX is manufactured will be described.
[0085]
In FIG. 4A, reference numeral 401 denotes a single crystal silicon substrate. In this embodiment, first, oxygen ions are added to the single crystal silicon substrate 401 to form an oxygen-containing layer 402 at a predetermined depth. Oxygen ions may be added at a dose of about 1 × 10 18 atoms / cm 2 .
[0086]
At this time, since the {110} plane has a low atomic density, the collision probability between oxygen ions and silicon atoms is low. That is, damage to the silicon surface due to the addition of oxygen can be minimized. Of course, damage can be further reduced by setting the substrate temperature to 400 to 600 ° C. during ion addition.
[0087]
Next, heat treatment is performed at a temperature of 800 to 1200 ° C. to change the oxygen-containing layer 402 into the buried insulating layer 403. The width in the depth direction of the oxygen-containing layer 402 is determined by the distribution of oxygen ions at the time of ion addition, and has a distribution that has a skirt, but by this heat treatment process, the single crystal silicon substrate 401 and the buried insulating layer 403 The interface with is very steep. (Fig. 4 (B))
[0088]
The buried insulating layer 403 has a thickness of 10 to 500 nm (typically 20 to 50 nm). The thin buried insulating layer of 20 to 50 nm can be realized because the interface between the single crystal silicon substrate 401 and the buried insulating layer 403 is stably bonded, and the single crystal silicon substrate whose main surface is the {110} plane. Is used as a material for forming a single crystal silicon layer.
[0089]
When the buried insulating layer 403 is formed in this way, the single crystal silicon layer 404 remains on the buried insulating layer 403. That is, in this embodiment, since a single crystal silicon substrate having a {110} plane as the main surface is used, the single crystal silicon layer 404 obtained after forming the buried insulating layer has a main surface (crystal plane) of {110} plane. Become. Note that the thickness of the single crystal silicon layer 404 may be adjusted to be 10 to 200 nm (preferably 20 to 100 nm).
[0090]
When the single crystal silicon layer 404 is obtained in this way, patterning is performed to obtain the island-shaped silicon layer 405. A plurality of island-like silicon layers may be formed.
[0091]
Thereafter, a plurality of TFTs may be completed according to the process described in Embodiment 1 with reference to FIG. Moreover, you may form TFT using another well-known means. Detailed description is omitted in this embodiment.
[0092]
Example 4
In this embodiment, an example of a reflective liquid crystal display device is shown in FIG. 5 as a semiconductor device of the present invention. Since a known method may be used for a manufacturing method of a pixel TFT (pixel switching element) and a cell assembly process, detailed description thereof is omitted.
[0093]
5A, 11 is a substrate having an insulating surface, 12 is a pixel matrix circuit, 13 is a source driver circuit, 14 is a gate driver circuit, 15 is a counter substrate, 16 is an FPC (flexible printed circuit), and 17 is signal processing. Circuit. As the signal processing circuit 17, it is possible to form a circuit that performs processing such as a D / A converter, a γ correction circuit, a signal division circuit, or the like that has been substituted for a conventional IC. Of course, it is also possible to provide an IC chip on a glass substrate and perform signal processing on the IC chip.
[0094]
Further, in this embodiment, the liquid crystal display device is described as an example. However, if the display device is an active matrix type, other electric devices such as an EL (electroluminescence) display device and an EC (electrochromic) display device are used. The present invention can also be used for an optical device.
[0095]
Here, FIG. 5B shows an example of a circuit constituting the driver circuits 13 and 14 in FIG. Since the TFT portion has already been described in Embodiment 1, only the necessary portions will be described here.
[0096]
In FIG. 5B, reference numerals 501 and 502 denote N-channel TFTs, and 503 denotes a P-channel TFT. The TFTs 501 and 503 constitute a CMOS circuit. Reference numeral 504 denotes an insulating layer formed of a laminated film of silicon nitride film / silicon oxide film / resin film, and a titanium wiring 505 is provided on the insulating layer, and the above-described CMOS circuit and the TFT 502 are electrically connected. The titanium wiring is further covered with an insulating layer 506 made of a resin film. The two insulating layers 504 and 506 also have a function as a planarizing film.
[0097]
FIG. 5C illustrates part of a circuit included in the pixel matrix circuit 12 in FIG. In FIG. 5C, reference numeral 507 denotes a pixel TFT formed of an N-channel TFT having a double gate structure, and a drain wiring 508 is formed so as to spread widely in the pixel region.
[0098]
An insulating layer 504 is provided thereon, and a titanium wiring 505 is provided thereon. At this time, a recess is dropped into a part of the insulating layer 504, and only the lowermost silicon nitride and silicon oxide are left. As a result, an auxiliary capacitance is formed between the drain wiring 508 and the titanium wiring 505.
[0099]
The titanium wiring 505 provided in the pixel matrix circuit provides an electric field shielding effect between the source / drain wiring and the subsequent pixel electrode. Further, it functions as a black mask in the gaps between a plurality of pixel electrodes.
[0100]
An insulating layer 506 is provided to cover the titanium wiring 505, and a pixel electrode 509 made of a reflective conductive film is formed thereon. Of course, the surface of the pixel electrode 509 may be devised to increase the reflectance.
[0101]
In addition, an alignment film and a liquid crystal layer are actually provided on the pixel electrode 509, but description thereof is omitted here.
[0102]
A reflection type liquid crystal display device having the above-described configuration can be manufactured using the present invention. Needless to say, a transmissive liquid crystal display device (however, only when a light-transmitting substrate is used as a supporting substrate) can be easily manufactured by combining with a known technique. Further, an active matrix EL display device can be easily manufactured by combining with a known technique.
[0103]
In manufacturing the electro-optical device of this example, any of the SOI substrates of Examples 1 to 3 may be used.
[0104]
(Example 5)
The present invention can be applied to all conventional IC technologies. That is, it can be applied to all semiconductor circuits currently on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor or an ASIC processor integrated on a single chip, or from a signal processing circuit such as a D / A converter to a portable device (cell phone, PHS, mobile computer). You may apply to a high frequency circuit.
[0105]
FIG. 6 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.
[0106]
Needless to say, the microprocessor illustrated in FIG. 6 is a simplified example, and various circuit designs are performed on an actual microprocessor depending on its application.
[0107]
However, it is an IC (Integrated Circuit) 28 that functions as the center of a microprocessor having any function. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected with ceramic or the like.
[0108]
The N-channel TFT 30 and the P-channel TFT 31 having the structure of the present invention constitute an integrated circuit (semiconductor circuit) formed on the semiconductor chip 29. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.
[0109]
The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Typical electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (such as an automobile or a train) may be used.
[0110]
In manufacturing the semiconductor circuit of this embodiment, any of the SOI substrates of Embodiments 1 to 3 may be used.
[0111]
(Example 6)
The electro-optical device shown in Embodiment 4 and the semiconductor circuit shown in Embodiment 5 can be used for various electronic devices. Such electronic devices include video cameras, digital cameras, projectors, projection TVs, TV displays, personal computer displays, goggle-type displays (head-mounted displays), car navigation systems, personal computers, and image playback devices (DVD players, CD players, MD players, etc.) and portable information terminals (mobile computers, mobile phones, electronic books, etc.). An example of them is shown in FIG.
[0112]
FIG. 7A illustrates a mobile phone, which includes a main body 2001, an audio output unit 2002, an audio input unit 2003, a display device 2004, an operation switch 2005, and an antenna 2006. The present invention can be applied to the audio output unit 2002, the audio input unit 2003, the display device 2004, and other signal control circuits.
[0113]
FIG. 7B illustrates a video camera, which includes a main body 2101, a display device 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The present invention can be applied to the display device 2102, the voice input unit 2103, and other signal control circuits.
[0114]
FIG. 7C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.
[0115]
FIG. 7D illustrates a personal computer, which includes a main body 2301, an image receiving portion 2302, a display device 2303, a keyboard 2304, and the like. The present invention can be used for the display device 2304 and other signal control circuits.
[0116]
FIG. 7E illustrates a rear projector, which includes a main body 2401, a light source 2402, a display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be applied to the display device 2403 and other signal control circuits.
[0117]
FIG. 7F illustrates an electronic book which includes a main body 2501, display devices 2502 and 2503, a storage medium 2504, operation switches 2505, and an antenna 2506. The present invention can be applied to the display devices 2502 and 2503 and other signal control circuits.
[0118]
As described above, the application range of the present invention is extremely wide and can be used for electronic devices in various fields.
[0119]
(Example 7)
The present embodiment is a modification of the second embodiment, and shows an example in which the method for forming the porous silicon layer 302 is improved when the ELTRAN method of FIG. 3 is used.
[0120]
In the step of FIG. 3A, the anodizing treatment is performed in a mixed solution of hydrofluoric acid and ethanol to form the porous silicon layer 302. At this time, the anodizing treatment is performed at a constant current density, but the present embodiment is characterized in that the current density is switched during the anodizing treatment.
[0121]
Specifically, the current density applied during the anodizing treatment is increased, and the second porous silicon having larger individual pore diameters than the porous silicon layer (first porous silicon layer) formed so far. Form a layer.
[0122]
In the case of this embodiment, when an impact is applied to the porous silicon layer (laminated body of the first porous silicon layer and the second porous silicon layer) in the state of FIG. It is divided along the interface between the first porous silicon layer and the second porous silicon layer. That is, it is not necessary to perform a polishing process (grinding process) as shown in FIG.
[0123]
Therefore, according to the present embodiment, two semiconductor substrates are not required for manufacturing one SOI substrate, so that the manufacturing cost can be greatly reduced.
[0124]
When an SOI substrate is manufactured according to this embodiment, a TFT having an active layer made of a single crystal silicon layer whose main surface is a {110} plane may be formed according to the steps of Embodiment 1. The TFT manufactured using this embodiment can be used for the electro-optical device of Embodiment 4 or the semiconductor circuit of Embodiment 5. In addition, the electro-optical device and the semiconductor circuit thus manufactured can be used for the electronic apparatus of Example 6.
[0125]
【The invention's effect】
By implementing the present invention, the adhesion between the buried insulating layer of the SOI substrate and the single crystal silicon layer can be improved, and the reliability of a TFT manufactured using the SOI substrate can be improved.
[0126]
Then, it becomes possible to constitute a semiconductor circuit having very high reliability by using the TFT, and as a result, the reliability of a semiconductor device such as a liquid crystal display device or a notebook personal computer equipped with the liquid crystal display device can be increased. .
[Brief description of the drawings]
FIGS. 1A to 1C illustrate a manufacturing process of an SOI substrate. FIGS.
FIGS. 2A and 2B are diagrams illustrating a manufacturing process of a TFT. FIGS.
FIGS. 3A to 3D are diagrams illustrating a manufacturing process of an SOI substrate. FIGS.
FIGS. 4A to 4D are diagrams illustrating a manufacturing process of an SOI substrate. FIGS.
FIG. 5 is a diagram showing a configuration of a semiconductor device (electro-optical device).
FIG. 6 illustrates a structure of a semiconductor device (semiconductor circuit).
FIG. 7 illustrates a structure of a semiconductor device (electronic device).
FIG. 8 is a photograph showing a crystal structure of single crystal silicon.

Claims (9)

  1. 主表面が{110}面である単結晶半導体基板に熱酸化処理を行い、膜厚が20nm〜50nmである酸化シリコン膜を形成し、
    前記酸化シリコン膜を通して前記単結晶半導体基板中に水素を添加して水素含有層を形成し、
    前記単結晶半導体基板と支持基板とを貼り合わせ、
    第1熱処理により前記単結晶半導体基板を前記水素含有層に沿って分断し、
    1050℃〜1150℃の温度で第2熱処理を行い、
    前記支持基板の上の主表面が{110}面である単結晶半導体層を研削し、
    前記単結晶半導体層を活性層とする複数のTFTを形成することを特徴とする半導体装置の作製方法。
    A thermal oxidation treatment is performed on the single crystal semiconductor substrate whose main surface is the {110} plane, and a silicon oxide film having a thickness of 20 nm to 50 nm is formed.
    Hydrogen is added to the single crystal semiconductor substrate through the silicon oxide film to form a hydrogen-containing layer,
    Bonding the single crystal semiconductor substrate and the support substrate,
    Dividing the single crystal semiconductor substrate along the hydrogen-containing layer by a first heat treatment;
    The second heat treatment is performed at a temperature of 1050 ° C. to 1150 ° C. ,
    Grinding a single crystal semiconductor layer whose main surface on the support substrate is a {110} plane;
    A method for manufacturing a semiconductor device, comprising forming a plurality of TFTs using the single crystal semiconductor layer as an active layer.
  2. 主表面が{110}面である単結晶半導体基板に熱酸化処理を行い、膜厚が20nm〜50nmである酸化シリコン膜を形成し、Thermal oxidation treatment is performed on the single crystal semiconductor substrate whose main surface is the {110} plane, and a silicon oxide film having a thickness of 20 nm to 50 nm is formed.
    前記酸化シリコン膜を通して前記単結晶半導体基板中に水素を添加して水素含有層を形成し、Hydrogen is added to the single crystal semiconductor substrate through the silicon oxide film to form a hydrogen-containing layer,
    前記単結晶半導体基板と支持基板とを貼り合わせ、Bonding the single crystal semiconductor substrate and the support substrate,
    第1熱処理により前記単結晶半導体基板を前記水素含有層に沿って分断し、Dividing the single crystal semiconductor substrate along the hydrogen-containing layer by a first heat treatment;
    1050℃〜1150℃の温度で第2熱処理を行い、The second heat treatment is performed at a temperature of 1050 ° C. to 1150 ° C.,
    前記支持基板の上の主表面が{110}面である単結晶半導体層の表面を平坦化し、Planarizing the surface of the single crystal semiconductor layer whose main surface on the support substrate is a {110} plane;
    前記単結晶半導体層を活性層とする複数のTFTを形成することを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, comprising forming a plurality of TFTs using the single crystal semiconductor layer as an active layer.
  3. 請求項2において、前記単結晶半導体層の表面の平坦化処理として、ケミカルメカニカルポリッシング処理または900℃〜1200℃の還元雰囲気中での熱処理を行うことを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device according to claim 2, wherein the planarization treatment of the surface of the single crystal semiconductor layer is performed by chemical mechanical polishing treatment or heat treatment in a reducing atmosphere at 900 ° C. to 1200 ° C.
  4. 主表面が{110}面である単結晶半導体基板に熱酸化処理を行い、膜厚が20nm〜50nmである酸化シリコン膜を形成し、Thermal oxidation treatment is performed on the single crystal semiconductor substrate whose main surface is the {110} plane, and a silicon oxide film having a thickness of 20 nm to 50 nm is formed.
    前記酸化シリコン膜を通して前記単結晶半導体基板中に水素を添加して水素含有層を形成し、Hydrogen is added to the single crystal semiconductor substrate through the silicon oxide film to form a hydrogen-containing layer,
    前記単結晶半導体基板と支持基板とを貼り合わせ、Bonding the single crystal semiconductor substrate and the support substrate,
    前記支持基板上に主表面が{110}面である単結晶半導体層が残るように、熱処理により前記単結晶半導体基板を前記水素含有層に沿って分断し、The single crystal semiconductor substrate is divided along the hydrogen-containing layer by heat treatment so that a single crystal semiconductor layer whose main surface is a {110} plane remains on the support substrate.
    前記単結晶半導体層を活性層とする複数のTFTを形成することを特徴とする半導体装置の作製方法。A method for manufacturing a semiconductor device, comprising forming a plurality of TFTs using the single crystal semiconductor layer as an active layer.
  5. 請求項1乃至請求項のいずれか一において、前記単結晶半導体層とは単結晶シリコン層であることを特徴とする半導体装置の作製方法。In any one of claims 1 to 4, the method for manufacturing a semiconductor device, characterized in that said single crystal semiconductor layer is a single crystal silicon layer.
  6. 請求項1乃至請求項5のいずれか一において、前記TFTのゲート配線に、銅又は銅合金を用いることを特徴とする半導体装置の作製方法。  6. The method for manufacturing a semiconductor device according to claim 1, wherein copper or a copper alloy is used for the gate wiring of the TFT.
  7. 請求項1乃至請求項6のいずれか一の半導体装置の作製方法を用いて作製されたことを特徴とする電気光学装置。  An electro-optical device manufactured using the method for manufacturing a semiconductor device according to claim 1.
  8. 請求項1乃至請求項6のいずれか一の半導体装置の作製方法を用いて作製されたことを特徴とする半導体回路。  A semiconductor circuit manufactured using the method for manufacturing a semiconductor device according to claim 1.
  9. 請求項7に記載の電気光学装置または請求項8に記載の半導体回路を用いたことを特徴とする電子機器。  An electronic apparatus using the electro-optical device according to claim 7 or the semiconductor circuit according to claim 8.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120082800A (en) * 2010-07-26 2012-07-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same

Families Citing this family (194)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW408351B (en) * 1997-10-17 2000-10-11 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
US6686623B2 (en) 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
JP2000012864A (en) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6559036B1 (en) * 1998-08-07 2003-05-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP4476390B2 (en) 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
TW518637B (en) * 1999-04-15 2003-01-21 Semiconductor Energy Lab Electro-optical device and electronic equipment
JP2001217428A (en) * 2000-01-25 2001-08-10 Samsung Electronics Co Ltd Low temperature polycrystalline silicon type thin film transistor and its manufacturing method
FR2816445B1 (en) * 2000-11-06 2003-07-25 Commissariat Energie Atomique METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN LAYER ADHERING TO A TARGET SUBSTRATE
JP3716755B2 (en) * 2001-04-05 2005-11-16 株式会社日立製作所 Active matrix display device
TW487958B (en) * 2001-06-07 2002-05-21 Ind Tech Res Inst Manufacturing method of thin film transistor panel
US8195187B2 (en) * 2001-06-25 2012-06-05 Airvana Network Solutions, Inc. Radio network control
US7501303B2 (en) * 2001-11-05 2009-03-10 The Trustees Of Boston University Reflective layer buried in silicon and method of fabrication
AU2003215202A1 (en) * 2002-02-13 2003-09-04 The Regents Of The University Of California A multilayer structure to form an active matrix display having single crystalline drivers over a transmissive substrate
FR2842350B1 (en) * 2002-07-09 2005-05-13 Method for transferring a layer of concealed semiconductor material
US6953736B2 (en) * 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
JP4683817B2 (en) * 2002-09-27 2011-05-18 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP4454921B2 (en) * 2002-09-27 2010-04-21 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6707106B1 (en) 2002-10-18 2004-03-16 Advanced Micro Devices, Inc. Semiconductor device with tensile strain silicon introduced by compressive material in a buried oxide layer
JP2004172406A (en) * 2002-11-20 2004-06-17 Kobe Steel Ltd Semiconductor substrate with ceramics, semiconductor wafer with ceramics, and its manufacturing method
US7399681B2 (en) 2003-02-18 2008-07-15 Corning Incorporated Glass-based SOI structures
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
JP4442560B2 (en) * 2003-02-19 2010-03-31 信越半導体株式会社 Manufacturing method of SOI wafer
US6911379B2 (en) * 2003-03-05 2005-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming strained silicon on insulator substrate
US6949451B2 (en) * 2003-03-10 2005-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. SOI chip with recess-resistant buried insulator and method of manufacturing the same
US6902962B2 (en) * 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
JP4342826B2 (en) * 2003-04-23 2009-10-14 株式会社半導体エネルギー研究所 Manufacturing method of semiconductor element
US6864149B2 (en) * 2003-05-09 2005-03-08 Taiwan Semiconductor Manufacturing Company SOI chip with mesa isolation and recess resistant regions
JP4239676B2 (en) * 2003-05-15 2009-03-18 信越半導体株式会社 SOI wafer and manufacturing method thereof
US7538010B2 (en) * 2003-07-24 2009-05-26 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating an epitaxially grown layer
FR2857983B1 (en) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator PROCESS FOR PRODUCING AN EPITAXIC LAYER
JP2005070120A (en) * 2003-08-27 2005-03-17 Shin Etsu Chem Co Ltd Pellicle for lithography
US7625808B2 (en) * 2003-09-01 2009-12-01 Sumco Corporation Method for manufacturing bonded wafer
JP4554180B2 (en) * 2003-09-17 2010-09-29 ソニー株式会社 Method for manufacturing thin film semiconductor device
CN1742367A (en) * 2003-10-24 2006-03-01 索尼株式会社 Method for manufacturing semiconductor substrate and semiconductor substrate
US6902965B2 (en) * 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
US7161169B2 (en) * 2004-01-07 2007-01-09 International Business Machines Corporation Enhancement of electron and hole mobilities in <110> Si under biaxial compressive strain
FR2864970B1 (en) * 2004-01-09 2006-03-03 Soitec Silicon On Insulator Support substrate with thermal expansion coefficient determined
US7205210B2 (en) * 2004-02-17 2007-04-17 Freescale Semiconductor, Inc. Semiconductor structure having strained semiconductor and method therefor
JP2005311295A (en) * 2004-03-26 2005-11-04 Semiconductor Energy Lab Co Ltd Semiconductor device
US7279751B2 (en) * 2004-06-21 2007-10-09 Matsushita Electric Industrial Co., Ltd. Semiconductor laser device and manufacturing method thereof
DE102004032917B4 (en) * 2004-07-07 2010-01-28 Qimonda Ag Method for producing a double-gate transistor
US7560361B2 (en) * 2004-08-12 2009-07-14 International Business Machines Corporation Method of forming gate stack for semiconductor electronic device
JP2008511137A (en) * 2004-08-18 2008-04-10 コーニング インコーポレイテッド Semiconductor structure on insulator with high strain glass / glass-ceramic
JP2008510315A (en) * 2004-08-18 2008-04-03 コーニング インコーポレイテッド Strained semiconductor structure on insulator and method for making strained semiconductor structure on insulator
FR2874455B1 (en) * 2004-08-19 2008-02-08 Soitec Silicon On Insulator Heat treatment before bonding two plates
JP4816856B2 (en) * 2004-09-15 2011-11-16 信越半導体株式会社 Manufacturing method of SOI wafer
US7422956B2 (en) * 2004-12-08 2008-09-09 Advanced Micro Devices, Inc. Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers
US7348610B2 (en) * 2005-02-24 2008-03-25 International Business Machines Corporation Multiple layer and crystal plane orientation semiconductor substrate
US20060205129A1 (en) * 2005-02-25 2006-09-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR20070107180A (en) * 2005-02-28 2007-11-06 실리콘 제너시스 코포레이션 Substrate stiffness method and resulting devices
US7659892B2 (en) * 2005-03-17 2010-02-09 Semiconductor Energy Laboratory Co., Ltd. Display device and portable terminal
US7687372B2 (en) * 2005-04-08 2010-03-30 Versatilis Llc System and method for manufacturing thick and thin film devices using a donee layer cleaved from a crystalline donor
JPWO2006117900A1 (en) * 2005-04-26 2008-12-18 シャープ株式会社 Semiconductor device manufacturing method and semiconductor device
JP2007019191A (en) * 2005-07-06 2007-01-25 Fujitsu Ltd Semiconductor device and its manufacturing method
US7268051B2 (en) * 2005-08-26 2007-09-11 Corning Incorporated Semiconductor on glass insulator with deposited barrier layer
US7691730B2 (en) * 2005-11-22 2010-04-06 Corning Incorporated Large area semiconductor on glass insulator
FR2896618B1 (en) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator PROCESS FOR PRODUCING A COMPOSITE SUBSTRATE
JP5168788B2 (en) * 2006-01-23 2013-03-27 信越半導体株式会社 Manufacturing method of SOI wafer
FR2896619B1 (en) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator PROCESS FOR MANUFACTURING A COMPOSITE SUBSTRATE WITH IMPROVED ELECTRIC PROPERTIES
CN101351872B (en) * 2006-03-08 2010-04-14 夏普株式会社 Semiconductor device and process for producing the same
US7696024B2 (en) * 2006-03-31 2010-04-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070264796A1 (en) * 2006-05-12 2007-11-15 Stocker Mark A Method for forming a semiconductor on insulator structure
EP1950803B1 (en) * 2007-01-24 2011-07-27 S.O.I.TEC Silicon on Insulator Technologies S.A. Method for manufacturing silicon on Insulator wafers and corresponding wafer
US7755113B2 (en) * 2007-03-16 2010-07-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, semiconductor display device, and manufacturing method of semiconductor device
WO2008123117A1 (en) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
WO2008123116A1 (en) 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Soi substrate and method for manufacturing soi substrate
WO2008121262A2 (en) * 2007-03-30 2008-10-09 Corning Incorporated Glass-ceramic-based semiconductor-on-insulator structures and method for making the same
US7875881B2 (en) * 2007-04-03 2011-01-25 Semiconductor Energy Laboratory Co., Ltd. Memory device and semiconductor device
CN101281912B (en) 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi substrate and manufacturing method thereof, and semiconductor device
US20080248629A1 (en) * 2007-04-06 2008-10-09 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
WO2008132894A1 (en) 2007-04-13 2008-11-06 Semiconductor Energy Laboratory Co., Ltd. Display device, method for manufacturing display device, and soi substrate
EP2143146A1 (en) * 2007-04-13 2010-01-13 Semiconductor Energy Laboratory Co, Ltd. Photovoltaic device and method for manufacturing the same
KR101440930B1 (en) * 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method of manufacturing soi substrate
EP1986230A2 (en) * 2007-04-25 2008-10-29 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing SOI substrate and method of manufacturing semiconductor device
EP1986229A1 (en) * 2007-04-27 2008-10-29 S.O.I.T.E.C. Silicon on Insulator Technologies Method for manufacturing compound material wafer and corresponding compound material wafer
US7635617B2 (en) * 2007-04-27 2009-12-22 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor substrate and manufacturing method of semiconductor device
JP5289805B2 (en) * 2007-05-10 2013-09-11 株式会社半導体エネルギー研究所 Method for manufacturing substrate for manufacturing semiconductor device
KR101443580B1 (en) * 2007-05-11 2014-10-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor device
JP5137461B2 (en) * 2007-05-15 2013-02-06 株式会社半導体エネルギー研究所 Semiconductor device
KR101457656B1 (en) * 2007-05-17 2014-11-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Manufacturing method of semiconductor device, manufacturing method of display device, semiconductor device, display device, and electronic device
EP1993128A3 (en) * 2007-05-17 2010-03-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
EP1993126B1 (en) * 2007-05-18 2011-09-21 Semiconductor Energy Laboratory Co., Ltd. Manufacturing methods of semiconductor substrate
US9059247B2 (en) * 2007-05-18 2015-06-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
US8803781B2 (en) * 2007-05-18 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device
US8513678B2 (en) * 2007-05-18 2013-08-20 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device
KR101400699B1 (en) * 2007-05-18 2014-05-29 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor substrate, semiconductor device and manufacturing method thereof
EP1993127B1 (en) * 2007-05-18 2013-04-24 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate
KR101634970B1 (en) * 2007-05-18 2016-06-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
US7960262B2 (en) * 2007-05-18 2011-06-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device by applying laser beam to single-crystal semiconductor layer and non-single-crystal semiconductor layer through cap film
JP2008300709A (en) * 2007-06-01 2008-12-11 Semiconductor Energy Lab Co Ltd Semiconductor device, and manufacturing method thereof
JP5142831B2 (en) 2007-06-14 2013-02-13 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
US7772054B2 (en) * 2007-06-15 2010-08-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7875532B2 (en) * 2007-06-15 2011-01-25 Semiconductor Energy Laboratory Co., Ltd. Substrate for manufacturing semiconductor device and manufacturing method thereof
US7781306B2 (en) * 2007-06-20 2010-08-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate and method for manufacturing the same
US7763502B2 (en) 2007-06-22 2010-07-27 Semiconductor Energy Laboratory Co., Ltd Semiconductor substrate, method for manufacturing semiconductor substrate, semiconductor device, and electronic device
KR101484296B1 (en) 2007-06-26 2015-01-19 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor substrate, manufacturing method of the semiconductor substrate, and semiconductor device and electronic device using the same
US7795111B2 (en) * 2007-06-27 2010-09-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
US20090004764A1 (en) * 2007-06-29 2009-01-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
EP2009687B1 (en) * 2007-06-29 2016-08-17 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing an SOI substrate and method of manufacturing a semiconductor device
EP2009694A3 (en) * 2007-06-29 2017-06-21 Semiconductor Energy Laboratory Co, Ltd. Semiconductor device and manufacturing method thereof
US8354674B2 (en) * 2007-06-29 2013-01-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device wherein a property of a first semiconductor layer is different from a property of a second semiconductor layer
US7678668B2 (en) * 2007-07-04 2010-03-16 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
US8049253B2 (en) 2007-07-11 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US7790563B2 (en) * 2007-07-13 2010-09-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, electronic device and method for manufacturing semiconductor device
JP5486781B2 (en) * 2007-07-19 2014-05-07 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP5442224B2 (en) * 2007-07-23 2014-03-12 株式会社半導体エネルギー研究所 Manufacturing method of SOI substrate
JP5135935B2 (en) 2007-07-27 2013-02-06 信越半導体株式会社 Manufacturing method of bonded wafer
US20090032873A1 (en) * 2007-07-30 2009-02-05 Jeffrey Scott Cites Ultra thin single crystalline semiconductor TFT and process for making same
US8114722B2 (en) * 2007-08-24 2012-02-14 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
JP5205012B2 (en) 2007-08-29 2013-06-05 株式会社半導体エネルギー研究所 Display device and electronic apparatus including the display device
JP2009076890A (en) * 2007-08-31 2009-04-09 Semiconductor Energy Lab Co Ltd Manufacturing method of semiconductor device, semiconductor device, and electronic device
US8314009B2 (en) * 2007-09-14 2012-11-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
CN102646698B (en) * 2007-09-14 2015-09-16 株式会社半导体能源研究所 Semiconductor device and electronic equipment
US8232598B2 (en) * 2007-09-20 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5325404B2 (en) * 2007-09-21 2013-10-23 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
JP5463017B2 (en) * 2007-09-21 2014-04-09 株式会社半導体エネルギー研究所 Substrate manufacturing method
KR101499175B1 (en) * 2007-10-04 2015-03-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor substrate
US7989305B2 (en) * 2007-10-10 2011-08-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate using cluster ion
JP5511173B2 (en) * 2007-10-10 2014-06-04 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7799658B2 (en) 2007-10-10 2010-09-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
JP5527956B2 (en) * 2007-10-10 2014-06-25 株式会社半導体エネルギー研究所 Manufacturing method of semiconductor substrate
JP5506172B2 (en) 2007-10-10 2014-05-28 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor substrate
US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8101501B2 (en) * 2007-10-10 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
JP5490393B2 (en) * 2007-10-10 2014-05-14 株式会社半導体エネルギー研究所 Manufacturing method of semiconductor substrate
JP2009135430A (en) 2007-10-10 2009-06-18 Semiconductor Energy Lab Co Ltd Method of manufacturing semiconductor device
US8455331B2 (en) * 2007-10-10 2013-06-04 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
TWI493609B (en) 2007-10-23 2015-07-21 Semiconductor Energy Lab Method for manufacturing semiconductor substrate, display panel, and display device
KR101576447B1 (en) * 2007-10-29 2015-12-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Formation method of single crystal semiconductor layer, formation method of crystalline semiconductor layer, formation method of polycrystalline layer, and method for manufacturing semiconductor device
US7851318B2 (en) 2007-11-01 2010-12-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate and method for manufacturing the same, and method for manufacturing semiconductor device
CN101842910B (en) * 2007-11-01 2013-03-27 株式会社半导体能源研究所 Method for manufacturing photoelectric conversion device
US8163628B2 (en) * 2007-11-01 2012-04-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate
JP5548351B2 (en) * 2007-11-01 2014-07-16 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7816234B2 (en) 2007-11-05 2010-10-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090124038A1 (en) * 2007-11-14 2009-05-14 Mark Ewing Tuttle Imager device, camera, and method of manufacturing a back side illuminated imager
JP2009151293A (en) 2007-11-30 2009-07-09 Semiconductor Energy Lab Co Ltd Display device, manufacturing method of display device and electronic equipment
JP5464843B2 (en) * 2007-12-03 2014-04-09 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
US20090141004A1 (en) * 2007-12-03 2009-06-04 Semiconductor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5459900B2 (en) * 2007-12-25 2014-04-02 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US7842583B2 (en) 2007-12-27 2010-11-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
US20090179160A1 (en) * 2008-01-16 2009-07-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor substrate manufacturing apparatus
JP5404064B2 (en) 2008-01-16 2014-01-29 株式会社半導体エネルギー研究所 Laser processing apparatus and semiconductor substrate manufacturing method
JP5503876B2 (en) * 2008-01-24 2014-05-28 株式会社半導体エネルギー研究所 Manufacturing method of semiconductor substrate
US20090212397A1 (en) * 2008-02-22 2009-08-27 Mark Ewing Tuttle Ultrathin integrated circuit and method of manufacturing an ultrathin integrated circuit
US8003483B2 (en) * 2008-03-18 2011-08-23 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2009231376A (en) * 2008-03-19 2009-10-08 Shin Etsu Handotai Co Ltd Soi wafer and semiconductor device, and method of manufacturing the soi wafer
JP5654206B2 (en) * 2008-03-26 2015-01-14 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate and semiconductor device using the SOI substrate
JP2009260313A (en) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Method for manufacturing soi substrate, and method for manufacturing semiconductor device
JP2009260315A (en) * 2008-03-26 2009-11-05 Semiconductor Energy Lab Co Ltd Method for manufacturing soi substrate, and method for manufacturing semiconductor device
EP2105957A3 (en) * 2008-03-26 2011-01-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate and method for manufacturing semiconductor device
US7939389B2 (en) 2008-04-18 2011-05-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5503895B2 (en) * 2008-04-25 2014-05-28 株式会社半導体エネルギー研究所 Semiconductor device
JP5700617B2 (en) 2008-07-08 2015-04-15 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
US7943414B2 (en) * 2008-08-01 2011-05-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US8815657B2 (en) * 2008-09-05 2014-08-26 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device
JP5478166B2 (en) * 2008-09-11 2014-04-23 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
TWI514595B (en) 2008-09-24 2015-12-21 Semiconductor Energy Lab Photoelectric conversion device and manufacturing method thereof
US8048754B2 (en) * 2008-09-29 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing single crystal semiconductor layer
US20100081251A1 (en) * 2008-09-29 2010-04-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate
SG160302A1 (en) * 2008-09-29 2010-04-29 Semiconductor Energy Lab Method for manufacturing semiconductor substrate
US8741740B2 (en) * 2008-10-02 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2010114431A (en) 2008-10-10 2010-05-20 Semiconductor Energy Lab Co Ltd Method of manufacturing soi substrate
SG161151A1 (en) 2008-10-22 2010-05-27 Semiconductor Energy Lab Soi substrate and method for manufacturing the same
JP5611571B2 (en) * 2008-11-27 2014-10-22 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
SG182208A1 (en) * 2008-12-15 2012-07-30 Semiconductor Energy Lab Manufacturing method of soi substrate and manufacturing method of semiconductor device
JP5503995B2 (en) * 2009-02-13 2014-05-28 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
SG183670A1 (en) 2009-04-22 2012-09-27 Semiconductor Energy Lab Method of manufacturing soi substrate
KR20120032487A (en) * 2009-06-24 2012-04-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method reprocessing semiconductor substrate and method for manufacturing soi substrate
US8278187B2 (en) * 2009-06-24 2012-10-02 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments
KR101752901B1 (en) * 2009-08-25 2017-06-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 METHOD FOR REPROCESSING SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING REPROCESSED SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING SOl SUBSTRATE
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
KR101731809B1 (en) * 2009-10-09 2017-05-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
JP5926887B2 (en) * 2010-02-03 2016-05-25 株式会社半導体エネルギー研究所 Method for manufacturing SOI substrate
US8507966B2 (en) 2010-03-02 2013-08-13 Micron Technology, Inc. Semiconductor cells, arrays, devices and systems having a buried conductive line and methods for forming the same
US9608119B2 (en) 2010-03-02 2017-03-28 Micron Technology, Inc. Semiconductor-metal-on-insulator structures, methods of forming such structures, and semiconductor devices including such structures
US8288795B2 (en) 2010-03-02 2012-10-16 Micron Technology, Inc. Thyristor based memory cells, devices and systems including the same and methods for forming the same
US9646869B2 (en) 2010-03-02 2017-05-09 Micron Technology, Inc. Semiconductor devices including a diode structure over a conductive strap and methods of forming such semiconductor devices
US8513722B2 (en) 2010-03-02 2013-08-20 Micron Technology, Inc. Floating body cell structures, devices including same, and methods for forming same
JP5755931B2 (en) 2010-04-28 2015-07-29 株式会社半導体エネルギー研究所 Method for producing semiconductor film, method for producing electrode, method for producing secondary battery, and method for producing solar cell
JP5902917B2 (en) 2010-11-12 2016-04-13 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor substrate
JP2012156495A (en) 2011-01-07 2012-08-16 Semiconductor Energy Lab Co Ltd Manufacturing method of soi substrate
US8598621B2 (en) 2011-02-11 2013-12-03 Micron Technology, Inc. Memory cells, memory arrays, methods of forming memory cells, and methods of forming a shared doped semiconductor region of a vertically oriented thyristor and a vertically oriented access transistor
US8952418B2 (en) 2011-03-01 2015-02-10 Micron Technology, Inc. Gated bipolar junction transistors
US8519431B2 (en) 2011-03-08 2013-08-27 Micron Technology, Inc. Thyristors
US8802534B2 (en) 2011-06-14 2014-08-12 Semiconductor Energy Laboratory Co., Ltd. Method for forming SOI substrate and apparatus for forming the same
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
US8772848B2 (en) 2011-07-26 2014-07-08 Micron Technology, Inc. Circuit structures, memory circuitry, and methods
DE112012004373T5 (en) * 2011-10-18 2014-07-10 Fuji Electric Co., Ltd METHOD FOR SEPARATING A SUPPORTING SUBSTRATE FROM A SOLID PHASE-ASSEMBLED WAFER AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE
JP5831165B2 (en) * 2011-11-21 2015-12-09 富士通株式会社 Semiconductor optical device
US10002968B2 (en) 2011-12-14 2018-06-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display device including the same
DE102014111781A1 (en) * 2013-08-19 2015-03-12 Korea Atomic Energy Research Institute Process for the electrochemical production of a silicon layer
US9087689B1 (en) 2014-07-11 2015-07-21 Inoso, Llc Method of forming a stacked low temperature transistor and related devices
US9922866B2 (en) 2015-07-31 2018-03-20 International Business Machines Corporation Enhancing robustness of SOI substrate containing a buried N+ silicon layer for CMOS processing

Family Cites Families (200)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3964941A (en) * 1971-06-21 1976-06-22 Motorola, Inc. Method of making isolated complementary monolithic insulated gate field effect transistors
US4217153A (en) * 1977-04-04 1980-08-12 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device
JPS55130897A (en) * 1979-03-30 1980-10-11 Chiyou Lsi Gijutsu Kenkyu Kumiai Silicon single crystal
JPH0242725B2 (en) 1982-03-13 1990-09-25
EP0090624B1 (en) * 1982-03-26 1989-07-26 Fujitsu Limited Mos semiconductor device and method of producing the same
JPH0712210B2 (en) * 1982-06-02 1995-02-08 株式会社日立製作所 Imaging display device
JPH0379035B2 (en) 1984-05-28 1991-12-17 Taito Kk
US4768076A (en) * 1984-09-14 1988-08-30 Hitachi, Ltd. Recrystallized CMOS with different crystal planes
JPS6179315U (en) * 1984-10-26 1986-05-27
JPS6292361A (en) * 1985-10-17 1987-04-27 Toshiba Corp Complementary type semiconductor device
DE3779672T2 (en) * 1986-03-07 1993-01-28 Iizuka Kozo METHOD FOR PRODUCING A MONOCRISTALLINE SEMICONDUCTOR LAYER.
JPH0234170B2 (en) * 1986-03-24 1990-08-01 Sony Corp
US4753896A (en) * 1986-11-21 1988-06-28 Texas Instruments Incorporated Sidewall channel stop process
US4786955A (en) * 1987-02-24 1988-11-22 General Electric Company Semiconductor device with source and drain depth extenders and a method of making the same
JPH0687503B2 (en) * 1987-03-11 1994-11-02 株式会社日立製作所 Thin film semiconductor device
JPS63318779A (en) 1987-06-22 1988-12-27 Sanyo Electric Co Ltd Manufacture of semiconductor device
JPH01162376A (en) * 1987-12-18 1989-06-26 Fujitsu Ltd Manufacture of semiconductor device
US5059304A (en) 1988-02-12 1991-10-22 Chevron Research Company Process for removing sulfur from a hydrocarbon feedstream using a sulfur sorbent with alkali metal components or alkaline earth metal components
JP2685819B2 (en) 1988-03-31 1997-12-03 株式会社東芝 Dielectric isolated semiconductor substrate and manufacturing method thereof
JPH01264254A (en) * 1988-04-15 1989-10-20 Agency Of Ind Science & Technol Manufacture of laminate type semiconductor device
US4899202A (en) * 1988-07-08 1990-02-06 Texas Instruments Incorporated High performance silicon-on-insulator transistor with body node to source node connection
JPH02260442A (en) 1989-03-30 1990-10-23 Toshiba Corp Dielectric isolation type semiconductor substrate
US5002630A (en) * 1989-06-06 1991-03-26 Rapro Technology Method for high temperature thermal processing with reduced convective heat loss
US5215931A (en) * 1989-06-13 1993-06-01 Texas Instruments Incorporated Method of making extended body contact for semiconductor over insulator transistor
US5060035A (en) 1989-07-13 1991-10-22 Mitsubishi Denki Kabushiki Kaisha Silicon-on-insulator metal oxide semiconductor device having conductive sidewall structure
JPH0379035A (en) * 1989-08-22 1991-04-04 Nippondenso Co Ltd Mos transistor and manufacture thereof
FR2654258A1 (en) * 1989-11-03 1991-05-10 Philips Nv METHOD FOR MANUFACTURING A MITTED TRANSISTOR DEVICE HAVING A REVERSE "T" SHAPE ELECTRODE ELECTRODE
US5849627A (en) * 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
FR2663464B1 (en) * 1990-06-19 1992-09-11 Commissariat Energie Atomique INTEGRATED CIRCUIT IN SILICON-ON-INSULATION TECHNOLOGY COMPRISING A FIELD-EFFECT TRANSISTOR AND ITS MANUFACTURING METHOD.
EP0465961B1 (en) * 1990-07-09 1995-08-09 Sony Corporation Semiconductor device on a dielectric isolated substrate
US5750000A (en) * 1990-08-03 1998-05-12 Canon Kabushiki Kaisha Semiconductor member, and process for preparing same and semiconductor device formed by use of same
EP0469630B1 (en) * 1990-08-03 2002-05-08 Canon Kabushiki Kaisha Process for preparing a semiconductor body
JP2940880B2 (en) 1990-10-09 1999-08-25 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JPH0824193B2 (en) 1990-10-16 1996-03-06 セイコー電子工業株式会社 Manufacturing method of semiconductor device for driving flat plate type light valve
TW237562B (en) 1990-11-09 1995-01-01 Semiconductor Energy Res Co Ltd
JPH04206766A (en) 1990-11-30 1992-07-28 Hitachi Ltd Manufacture of semiconductor device
JPH04242958A (en) 1990-12-26 1992-08-31 Fujitsu Ltd Manufacture of semiconductor device
US5206749A (en) * 1990-12-31 1993-04-27 Kopin Corporation Liquid crystal display having essentially single crystal transistors pixels and driving circuits
US5289030A (en) 1991-03-06 1994-02-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with oxide layer
EP0510667B1 (en) * 1991-04-26 1996-09-11 Canon Kabushiki Kaisha Semiconductor device having an improved insulated gate transistor
US5261999A (en) * 1991-05-08 1993-11-16 North American Philips Corporation Process for making strain-compensated bonded silicon-on-insulator material free of dislocations
CA2069038C (en) * 1991-05-22 1997-08-12 Kiyofumi Sakaguchi Method for preparing semiconductor member
JPH04348532A (en) 1991-05-27 1992-12-03 Hitachi Ltd Semiconductor device and manufacture thereof
US6849872B1 (en) * 1991-08-26 2005-02-01 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor
FR2681472B1 (en) * 1991-09-18 1993-10-29 Commissariat A Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
JPH05166689A (en) 1991-11-19 1993-07-02 Sumitomo Metal Mining Co Ltd Method for joining semiconductor substrates
US5317433A (en) * 1991-12-02 1994-05-31 Canon Kabushiki Kaisha Image display device with a transistor on one side of insulating layer and liquid crystal on the other side
JP3179160B2 (en) 1991-12-19 2001-06-25 セイコーインスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
DE69317800T2 (en) 1992-01-28 1998-09-03 Canon Kk Method of manufacturing a semiconductor device
EP1043768B1 (en) * 1992-01-30 2004-09-08 Canon Kabushiki Kaisha Process for producing semiconductor substrates
JP3119384B2 (en) 1992-01-31 2000-12-18 キヤノン株式会社 Semiconductor substrate and manufacturing method thereof
JP3237888B2 (en) 1992-01-31 2001-12-10 キヤノン株式会社 Semiconductor substrate and method of manufacturing the same
JPH05218410A (en) 1992-01-31 1993-08-27 Toshiba Corp Semiconductor device and manufacture thereof
JPH05226620A (en) 1992-02-18 1993-09-03 Fujitsu Ltd Semiconductor substrate and its manufacture
US5424230A (en) * 1992-02-19 1995-06-13 Casio Computer Co., Ltd. Method of manufacturing a polysilicon thin film transistor
JP3506445B2 (en) 1992-05-12 2004-03-15 沖電気工業株式会社 Method for manufacturing semiconductor device
TW214603B (en) * 1992-05-13 1993-10-11 Seiko Electron Co Ltd Semiconductor device
JP3199847B2 (en) * 1992-07-09 2001-08-20 株式会社東芝 Semiconductor device and method of manufacturing the same
US5387555A (en) * 1992-09-03 1995-02-07 Harris Corporation Bonded wafer processing with metal silicidation
US5403759A (en) * 1992-10-02 1995-04-04 Texas Instruments Incorporated Method of making thin film transistor and a silicide local interconnect
TW232751B (en) * 1992-10-09 1994-10-21 Semiconductor Energy Res Co Ltd Semiconductor device and method for forming the same
JPH0798460A (en) * 1992-10-21 1995-04-11 Seiko Instr Inc Semiconductor device and light valve device
US5359219A (en) 1992-12-04 1994-10-25 Texas Instruments Incorporated Silicon on insulator device comprising improved substrate doping
US6875628B1 (en) * 1993-05-26 2005-04-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and fabrication method of the same
US5258323A (en) * 1992-12-29 1993-11-02 Honeywell Inc. Single crystal silicon on quartz
US5982002A (en) * 1993-01-27 1999-11-09 Seiko Instruments Inc. Light valve having a semiconductor film and a fabrication process thereof
US5818076A (en) * 1993-05-26 1998-10-06 Semiconductor Energy Laboratory Co., Ltd. Transistor and semiconductor device
DE69431636T2 (en) 1993-07-26 2003-06-26 Seiko Epson Corp Thin film semiconductor device, its manufacture and display system
US5529937A (en) * 1993-07-27 1996-06-25 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating thin film transistor
US5663077A (en) * 1993-07-27 1997-09-02 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films
US5576556A (en) * 1993-08-20 1996-11-19 Semiconductor Energy Laboratory Co., Ltd. Thin film semiconductor device with gate metal oxide and sidewall spacer
KR100333153B1 (en) * 1993-09-07 2002-12-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Process for fabricating semiconductor device
US5581092A (en) * 1993-09-07 1996-12-03 Semiconductor Energy Laboratory Co., Ltd. Gate insulated semiconductor device
TW297142B (en) * 1993-09-20 1997-02-01 Handotai Energy Kenkyusho Kk
JP3212060B2 (en) 1993-09-20 2001-09-25 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
JP3030368B2 (en) * 1993-10-01 2000-04-10 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
US5719065A (en) * 1993-10-01 1998-02-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with removable spacers
US5923962A (en) 1993-10-29 1999-07-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
TW264575B (en) 1993-10-29 1995-12-01 Handotai Energy Kenkyusho Kk
TW299897U (en) 1993-11-05 1997-03-01 Semiconductor Energy Lab A semiconductor integrated circuit
TW279275B (en) * 1993-12-27 1996-06-21 Sharp Kk
US5778237A (en) * 1995-01-10 1998-07-07 Hitachi, Ltd. Data processor and single-chip microcomputer with changing clock frequency and operating voltage
JP3257580B2 (en) * 1994-03-10 2002-02-18 キヤノン株式会社 Manufacturing method of semiconductor substrate
US20030087503A1 (en) * 1994-03-10 2003-05-08 Canon Kabushiki Kaisha Process for production of semiconductor substrate
US7148119B1 (en) 1994-03-10 2006-12-12 Canon Kabushiki Kaisha Process for production of semiconductor substrate
JP3294934B2 (en) 1994-03-11 2002-06-24 キヤノン株式会社 Method for manufacturing semiconductor substrate and semiconductor substrate
JP3192546B2 (en) 1994-04-15 2001-07-30 シャープ株式会社 Semiconductor device and method of manufacturing the same
US6433361B1 (en) * 1994-04-29 2002-08-13 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated circuit and method for forming the same
JP3312083B2 (en) * 1994-06-13 2002-08-05 株式会社半導体エネルギー研究所 Display device
JP3253808B2 (en) * 1994-07-07 2002-02-04 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
JP3361922B2 (en) 1994-09-13 2003-01-07 株式会社東芝 Semiconductor device
JPH08122768A (en) * 1994-10-19 1996-05-17 Sony Corp Display device
JP3109968B2 (en) 1994-12-12 2000-11-20 キヤノン株式会社 Method for manufacturing active matrix circuit board and method for manufacturing liquid crystal display device using the circuit board
US6421754B1 (en) 1994-12-22 2002-07-16 Texas Instruments Incorporated System management mode circuits, systems and methods
JPH08255907A (en) * 1995-01-18 1996-10-01 Canon Inc Insulated gate transistor and fabrication thereof
JP3364081B2 (en) * 1995-02-16 2003-01-08 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP3482028B2 (en) * 1995-03-01 2003-12-22 株式会社リコー Micro sensor
JPH08264802A (en) * 1995-03-28 1996-10-11 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor, manufacture of thin film transistor and thin film transistor
JP3292657B2 (en) 1995-04-10 2002-06-17 キヤノン株式会社 Thin film transistor and method for manufacturing liquid crystal display device using the same
JPH098124A (en) 1995-06-15 1997-01-10 Nippondenso Co Ltd Insulation separation substrate and its manufacture
US5841173A (en) * 1995-06-16 1998-11-24 Matsushita Electric Industrial Co., Ltd. MOS semiconductor device with excellent drain current
JPH0945882A (en) 1995-07-28 1997-02-14 Toshiba Corp Semiconductor substrate and manufacture thereof
FR2738671B1 (en) * 1995-09-13 1997-10-10 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS WITH SEMICONDUCTOR MATERIAL
JP3352340B2 (en) 1995-10-06 2002-12-03 キヤノン株式会社 Semiconductor substrate and method of manufacturing the same
JP2692659B2 (en) * 1995-10-13 1997-12-17 日本電気株式会社 SOI substrate and method for manufacturing the SOI substrate
KR0156178B1 (en) 1995-10-20 1998-11-16 구자홍 Method for producing lcd device
ZA9608485B (en) * 1995-11-01 1997-05-20 Lonza Ag Process for preparing nicotinamide
JPH09191111A (en) * 1995-11-07 1997-07-22 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
US5573961A (en) * 1995-11-09 1996-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Method of making a body contact for a MOSFET device fabricated in an SOI layer
JP3604791B2 (en) * 1995-11-09 2004-12-22 株式会社ルネサステクノロジ Method for manufacturing semiconductor device
TW324101B (en) * 1995-12-21 1998-01-01 Hitachi Ltd Semiconductor integrated circuit and its working method
JP3729955B2 (en) 1996-01-19 2005-12-21 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP3645380B2 (en) * 1996-01-19 2005-05-11 株式会社半導体エネルギー研究所 Manufacturing method of semiconductor device, information terminal, head mounted display, navigation system, mobile phone, video camera, projection display device
JP3645378B2 (en) * 1996-01-19 2005-05-11 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US5985740A (en) 1996-01-19 1999-11-16 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device including reduction of a catalyst
US6465287B1 (en) 1996-01-27 2002-10-15 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device using a metal catalyst and high temperature crystallization
JPH09213916A (en) 1996-02-06 1997-08-15 Nippon Telegr & Teleph Corp <Ntt> Manufacture of soi substrate
JP3476320B2 (en) * 1996-02-23 2003-12-10 株式会社半導体エネルギー研究所 Semiconductor thin film and method for manufacturing the same, semiconductor device and method for manufacturing the same
JPH09289167A (en) 1996-02-23 1997-11-04 Semiconductor Energy Lab Co Ltd Semiconductor thin film, manufacture thereof, semiconductor device and manufacture thereof
TW374196B (en) * 1996-02-23 1999-11-11 Semiconductor Energy Lab Co Ltd Semiconductor thin film and method for manufacturing the same and semiconductor device and method for manufacturing the same
TW317643B (en) * 1996-02-23 1997-10-11 Handotai Energy Kenkyusho Kk
JP3293736B2 (en) * 1996-02-28 2002-06-17 キヤノン株式会社 Semiconductor substrate manufacturing method and bonded substrate
JP3844538B2 (en) 1996-03-22 2006-11-15 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US5729045A (en) * 1996-04-02 1998-03-17 Advanced Micro Devices, Inc. Field effect transistor with higher mobility
JPH09289323A (en) 1996-04-23 1997-11-04 Matsushita Electric Works Ltd Manufacture of semiconductor device
TW411751B (en) * 1996-04-26 2000-11-11 Canon Kk Electronic apparatus
JPH09293876A (en) 1996-04-26 1997-11-11 Canon Inc Semiconductor element substrate, manufacture thereof, and semiconductor device using its substrate
FR2748851B1 (en) * 1996-05-15 1998-08-07 Commissariat Energie Atomique PROCESS FOR PRODUCING A THIN FILM OF SEMICONDUCTOR MATERIAL
JPH1012889A (en) * 1996-06-18 1998-01-16 Semiconductor Energy Lab Co Ltd Semiconductor thin film and semiconductor device
JP3383154B2 (en) 1996-06-20 2003-03-04 株式会社東芝 Semiconductor device
JPH1020331A (en) * 1996-06-28 1998-01-23 Sharp Corp Liquid crystal display device
US5989981A (en) 1996-07-05 1999-11-23 Nippon Telegraph And Telephone Corporation Method of manufacturing SOI substrate
TW548686B (en) * 1996-07-11 2003-08-21 Semiconductor Energy Lab CMOS semiconductor device and apparatus using the same
US5710057A (en) * 1996-07-12 1998-01-20 Kenney; Donald M. SOI fabrication method
SE513284C2 (en) * 1996-07-26 2000-08-14 Ericsson Telefon Ab L M Semiconductor component with linear current-to-voltage characteristics
JP4104682B2 (en) 1996-08-13 2008-06-18 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6287900B1 (en) * 1996-08-13 2001-09-11 Semiconductor Energy Laboratory Co., Ltd Semiconductor device with catalyst addition and removal
JP3260660B2 (en) 1996-08-22 2002-02-25 株式会社東芝 Semiconductor device and manufacturing method thereof
JP4103968B2 (en) 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 Insulated gate type semiconductor device
US5899711A (en) * 1996-10-11 1999-05-04 Xerox Corporation Method for enhancing hydrogenation of thin film transistors using a metal capping layer and method for batch hydrogenation
KR100500033B1 (en) * 1996-10-15 2005-09-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 A semiconductor device
JPH10125927A (en) 1996-10-15 1998-05-15 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
JP3662371B2 (en) 1996-10-15 2005-06-22 株式会社半導体エネルギー研究所 Thin film transistor manufacturing method and thin film transistor
TW451284B (en) 1996-10-15 2001-08-21 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
JP3948035B2 (en) 1996-10-18 2007-07-25 ソニー株式会社 Method for creating bonded SOI substrate
JPH10125879A (en) 1996-10-18 1998-05-15 Sony Corp Laminated soi substrate, its forming method and mos transistor formed on it
JP3645377B2 (en) 1996-10-24 2005-05-11 株式会社半導体エネルギー研究所 Integrated circuit fabrication method
JPH10135475A (en) * 1996-10-31 1998-05-22 Semiconductor Energy Lab Co Ltd Semiconductor device and its manufacture
JP3587636B2 (en) 1996-11-04 2004-11-10 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
US6118148A (en) * 1996-11-04 2000-09-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP3602279B2 (en) 1996-11-04 2004-12-15 株式会社半導体エネルギー研究所 Active matrix type display circuit and manufacturing method thereof
US6262438B1 (en) * 1996-11-04 2001-07-17 Semiconductor Energy Laboratory Co., Ltd. Active matrix type display circuit and method of manufacturing the same
JP3257624B2 (en) 1996-11-15 2002-02-18 キヤノン株式会社 Semiconductor member manufacturing method
US6054363A (en) 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
SG65697A1 (en) 1996-11-15 1999-06-22 Canon Kk Process for producing semiconductor article
KR100232886B1 (en) 1996-11-23 1999-12-01 김영환 Soi wafer fabricating method
US5904528A (en) * 1997-01-17 1999-05-18 Advanced Micro Devices, Inc. Method of forming asymmetrically doped source/drain regions
JP3753827B2 (en) 1997-01-20 2006-03-08 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
TW386238B (en) * 1997-01-20 2000-04-01 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
JP4401448B2 (en) 1997-02-24 2010-01-20 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
US6044474A (en) * 1997-04-08 2000-03-28 Klein; Dean A. Memory controller with buffered CAS/RAS external synchronization capability for reducing the effects of clock-to-signal skew
US6424011B1 (en) 1997-04-14 2002-07-23 International Business Machines Corporation Mixed memory integration with NVRAM, dram and sram cell structures on same substrate
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
JP2891237B2 (en) 1997-05-02 1999-05-17 日本電気株式会社 SOI structure semiconductor device and method of manufacturing the same
US6027988A (en) * 1997-05-28 2000-02-22 The Regents Of The University Of California Method of separating films from bulk substrates by plasma immersion ion implantation
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6452211B1 (en) 1997-06-10 2002-09-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor thin film and semiconductor device
JP3859821B2 (en) * 1997-07-04 2006-12-20 株式会社半導体エネルギー研究所 Semiconductor device
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
JP4282778B2 (en) 1997-08-05 2009-06-24 株式会社半導体エネルギー研究所 Semiconductor device
US6667494B1 (en) 1997-08-19 2003-12-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and semiconductor display device
US6388652B1 (en) * 1997-08-20 2002-05-14 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device
JP2000031488A (en) 1997-08-26 2000-01-28 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
JP4601731B2 (en) 1997-08-26 2010-12-22 株式会社半導体エネルギー研究所 Semiconductor device, electronic device having semiconductor device, and method for manufacturing semiconductor device
JPH11143379A (en) * 1997-09-03 1999-05-28 Semiconductor Energy Lab Co Ltd Semiconductor display device correcting system and its method
JPH11111991A (en) * 1997-09-30 1999-04-23 Sanyo Electric Co Ltd Thin-film transistor and method of manufacturing the thin-film transistor
JPH11111994A (en) * 1997-10-03 1999-04-23 Sanyo Electric Co Ltd Thin-film transistor and method for manufacturing the thin-film transistor
JP4044187B2 (en) * 1997-10-20 2008-02-06 株式会社半導体エネルギー研究所 Active matrix display device and manufacturing method thereof
US6686623B2 (en) * 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
JPH11163363A (en) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd Semiconductor device and its forming method
US6369410B1 (en) 1997-12-15 2002-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
US6063706A (en) * 1998-01-28 2000-05-16 Texas Instruments--Acer Incorporated Method to simulataneously fabricate the self-aligned silicided devices and ESD protective devices
JPH11233788A (en) 1998-02-09 1999-08-27 Semiconductor Energy Lab Co Ltd Semiconductor device
MY118019A (en) * 1998-02-18 2004-08-30 Canon Kk Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
JP3410957B2 (en) * 1998-03-19 2003-05-26 株式会社東芝 Semiconductor device and manufacturing method thereof
JPH11338439A (en) * 1998-03-27 1999-12-10 Semiconductor Energy Lab Co Ltd Driving circuit of semiconductor display device and semiconductor display device
US6268842B1 (en) 1998-04-13 2001-07-31 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor circuit and semiconductor display device using the same
JPH11307747A (en) * 1998-04-17 1999-11-05 Nec Corp Soi substrate and production thereof
US6331208B1 (en) * 1998-05-15 2001-12-18 Canon Kabushiki Kaisha Process for producing solar cell, process for producing thin-film semiconductor, process for separating thin-film semiconductor, and process for forming semiconductor
KR100301368B1 (en) * 1998-06-12 2001-10-27 윤종용 Power On Reset Circuit
US6165880A (en) 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
JP2000012864A (en) 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (en) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 Method for manufacturing semiconductor device
JP3720602B2 (en) * 1998-10-21 2005-11-30 株式会社リコー Image forming apparatus
US6356933B2 (en) * 1999-09-07 2002-03-12 Citrix Systems, Inc. Methods and apparatus for efficiently transmitting interactive application data between a client and a server using markup language
JP3840214B2 (en) * 2003-01-06 2006-11-01 キヤノン株式会社 Photoelectric conversion device, method for manufacturing photoelectric conversion device, and camera using the same
US20080123953A1 (en) * 2006-11-29 2008-05-29 Gateway Inc. Digital camera with histogram zoom

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120082800A (en) * 2010-07-26 2012-07-24 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same
KR101894570B1 (en) 2010-07-26 2018-09-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device and method for manufacturing the same

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