JP3216535B2 - SOI substrate and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor substrate and a method of manufacturing the same, and more particularly, to an SOI (Silicon on Insulator) useful for a power device.
or) a substrate.

[0002]

2. Description of the Related Art A silicon substrate bonding method has attracted attention as a method for manufacturing a substrate having a multilayer structure, particularly an SOI substrate, and has been developed.

[0003] This bonded SOI substrate has been put to practical use in high withstand voltage devices used for power control equipment.
Research and development on substrates for next-generation CMOS devices operating at low voltage have been actively conducted. Under these circumstances, the development of SOI substrates bonded to intelligent power IC substrates aiming for higher functionality, higher integration, and higher reliability has been developed based on the results of the practical use of high voltage devices in the field of power devices. It has been activated. In this intelligent power IC, it is necessary to mount a power device having a high withstand voltage and a large current operation and a CMOS device constituting a peripheral circuit for controlling the power device in a mixed manner. Therefore, the power device and the CMOS device constituting the peripheral circuit are formed on the same chip, and a bonded SOI substrate has been used to completely insulate and isolate them from each other.

Such a bonded SOI substrate is described in Japanese Patent Application Laid-Open No. 4-29353 (hereinafter referred to as a first conventional example) and Japanese Patent Application No. 6-15645.
No. 1 (hereinafter referred to as a second conventional example).

[0005] The conventional techniques described in these publications will be described below. FIG. 9 is a sectional view in the order of steps for explaining the first conventional example.

First, as shown in FIG. 9A, the surface of an n ⁺ -type single crystal silicon substrate 101 is selectively etched by a photolithography technique and a dry etching technique. Then, a shallow step is formed on the surface of n ⁺ -type single crystal silicon substrate 101. Next, the n ⁺
An insulating layer 102 is formed on the surface of the single-crystal silicon substrate 101. This insulating layer 102 is a silicon oxide film formed by thermal oxidation or chemical vapor deposition (CVD).

Next, as shown in FIG. 9B, the insulating layer 102 formed on the convex portion of the step is selectively removed by grinding or polishing. Thus, n ⁺
Surface 103 of insulating type single crystal silicon substrate 101 and insulating layer 1
02 surface is flattened to be the same surface.

Next, as shown in FIG. 9C, an n ⁻ -type single crystal silicon substrate 1 is formed on an n ⁺ -type single crystal silicon substrate 101.
04 is attached. Then, a single composite substrate which is subjected to the heat treatment and firmly bonded is obtained.

Next, n to the XY plane shown in FIG.
^The- type single crystal silicon substrate 104 is ground and polished. Then, n ⁻ -type single-crystal silicon substrate 104 is formed to have a desired film thickness and its surface is flattened. Thus, an active layer of single crystal silicon is formed. Hereinafter, this active layer is referred to as an SOI layer.

Next, a predetermined region of the SOI layer located on the insulating layer 102 is etched to form a separation groove reaching the insulating layer 102. Then, the surface of the isolation groove is oxidized, and an isolation insulating film 105 is formed as shown in FIG. Further, this separation groove is formed in the polycrystalline silicon film 10.
Filled with 6. Thus, the island-shaped SOI layer 10
7a is formed.

In such a bonded SOI substrate, the SOI layer 107 and the n ⁺ -type single crystal silicon substrate 101
A vertical high-voltage MOS transistor, which is a power device, is formed by using the above. In addition, the island-shaped SOI layer 107
A CMOS device for control is formed in a.

Next, a second conventional example will be described with reference to FIG. FIG. 10 is a sectional view in the order of steps for explaining a second conventional example.

As shown in FIG. 10A, the surface of an n ^- type single crystal silicon substrate 201 is selectively etched in the same manner as in the first conventional example. Then, a shallow step is formed on the surface of n ⁻ -type single crystal silicon substrate 201. Next, an insulating layer 202 is formed on the surface of the n ⁻ -type single crystal silicon substrate 201 on which the steps are formed. This insulating layer 202 is a silicon oxide film formed by thermal oxidation or CVD.

Next, as described in the first conventional example, the insulating layer 202 formed on the convex portion of the step is selectively removed by grinding or polishing. In this manner, an exposed surface is formed on n ⁻ -type single-crystal silicon substrate 201 so as to be flush with the surface of insulating layer 202.

Next, a polycrystalline silicon layer 203 is formed by CVD.
Is the exposed surface of n ⁻ -type single-crystal silicon substrate 201 and insulating layer 2
02 is formed. And this polycrystalline silicon layer 2
03 surface is polished and its surface is made mirror-finished.

Next, as shown in FIG. 10C, an n ⁺ -type single-crystal silicon substrate 204 is bonded to the polycrystalline silicon layer 203 on the n ^-- type single-crystal silicon substrate 201. Then, a single composite substrate which is subjected to the heat treatment and firmly bonded is obtained.

Next, the n ^- type single crystal silicon substrate 201 is ground and polished. Then, the n ^- type single crystal silicon substrate 2
01 is formed to a desired film thickness and its surface is flattened. Thus, an SOI layer is formed.

Next, a predetermined region of the SOI layer located on the insulating layer 202 is etched to form a separation groove reaching the insulating layer 202. Then, the surface of the isolation groove is oxidized, and an isolation insulating film 205 is formed as shown in FIG. Further, this separation groove is formed in the polycrystalline silicon film 2.
06. Thus, the island-shaped SOI layer 2
07a is formed.

In such a bonded SOI substrate, a high-concentration impurity is introduced into the polycrystalline silicon layer 203 from the n ⁺ -type single-crystal silicon substrate 204. Then, using the SOI layer 207 and the n ⁺ -type single crystal silicon substrate 204, a vertical high withstand voltage MOS transistor as a power device is formed. Also, island-shaped SOI
A control CMOS device is formed on the layer 207a.

[0020]

In the first prior art of the prior art described above, one of the bonded surfaces of the bonded SOI substrate, that is, the n ⁺ -type single crystal silicon substrate 1 is used.
On the surface 01, a single-crystal silicon surface and an insulating layer surface are mixed.

When flattening a surface in which such different materials are mixed, it is difficult to reduce the surface step of such a surface to 10 nm or less by today's grinding and polishing technology or etching technology. For this reason, the flatness of the bonding surface becomes insufficient, and the unbonded portion (void) is formed on the bonded surface.
Will occur. Then, in the process of manufacturing an intelligent power IC on such a bonded SOI substrate, peeling occurs at the void portion, and cracking or chipping of the substrate occurs. Then, for example, a problem occurs that the vertical MOS transistor does not function.

In the second conventional example, such voids are not generated, but a step of forming a polycrystalline silicon layer 203 and polishing the surface to a mirror surface is added. For this reason, the manufacturing cost of such a bonded SOI substrate increases.

The n ⁺ -type single crystal silicon substrate 204 of the SOI substrate is on the drain side of the vertical MOS transistor to be mounted.
3 is sandwiched on the drain side, so that the vertical MOS
The on-resistance of the transistor increases. Then, the operation speed of the intelligent power IC also decreases.

It is an object of the present invention to provide a structure in which no voids are generated at a bonding surface of a bonded SOI substrate, particularly at a bonding surface of a region where a vertical MOS transistor as a power device is formed, and no crack or chip is generated in a device manufacturing process. SOI
It is to provide a substrate and a method for manufacturing the same.

[0025]

For this purpose, the SO of the present invention is used.
In the I-substrate, an insulating layer having thermal fluidity is formed in a concave portion provided in a predetermined region on the main surface of the first semiconductor substrate, and the main surface of the first semiconductor substrate and the surface of the insulating layer form The bonded SOI substrate is bonded to a second semiconductor substrate, and the back surface of the first semiconductor substrate is polished or etched to form an SOI layer having a predetermined thickness.

Here, the first semiconductor substrate is a silicon semiconductor substrate of one conductivity type containing low concentration impurities, and the second semiconductor substrate is a silicon substrate of the same conductivity type containing high concentration impurities. It is . Alternatively, the insulating layer is made form an inorganic glass coating liquid coated on the first insulating layer you deposited in the recess. Alternatively, the surface of the insulating layer contains high concentration impurities.

[0027] Then, a wafer of the above laminated SOI substrate, the SOI layer of the wafer peripheral portion is removed with a constant width. Or, bonding SO
An I-substrate wafer, wherein the insulating layer is completely covered with the SOI layer and formed so as not to be exposed to the outside.
You.

Alternatively, the method for manufacturing an SOI substrate according to the present invention comprises the steps of: forming a concave portion by etching a predetermined region of the main surface of the first semiconductor substrate; and forming an insulating layer selectively in the concave portion. Selectively ion-implanting high-concentration impurities into the surface of the insulating layer, and heat-treating the insulating layer, and then bonding the second semiconductor substrate to the main surface of the first semiconductor substrate to perform a high-temperature heat treatment. The first semiconductor substrate and the second
Bonding the semiconductor substrate to the semiconductor substrate.

Here, the ion implantation of the high concentration impurity is performed only on the entire surface of the insulating layer formed in the concave portion or only on the surface of the end portion . Further, the method for manufacturing an SOI substrate according to the present invention includes, after bonding the first semiconductor substrate and the second semiconductor substrate, chamfering only a peripheral portion of the first semiconductor substrate; After chamfering, the first
Grinding and polishing the back side of the first semiconductor substrate to form an SOI layer.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the present invention will be described first.
A reference example will be described with reference to FIGS. 1 and 2 are cross-sectional views of a bonded SOI substrate according to the present embodiment in the order of manufacturing steps. Hereinafter, the structure of the semi-conductor substrate in the description of the manufacturing process are also described.

As shown in FIG. 1A, a recess 2 is formed in a predetermined region of an n ⁻ -type single-crystal silicon substrate 1 as a first semiconductor substrate. The recess 2 is formed by etching a part of the n ⁻ -type single-crystal silicon substrate 1 by a known photolithography technique and a dry etching technique. Here, the specific resistance of the n ⁻ -type single crystal silicon substrate 1 is 0.1 to 1
0 Ω · cm, and the depth of the concave portion 2 is determined by the design withstand voltage of the device, and is set in the range of 0.5 to 2 μm.

Next, a first insulating layer 3 is formed in the recess 2. For example, when the depth of the recess is 1 μm, the thickness of the first insulating layer 3 is set to 0.1 to 0.9 μm. Here, it is important that first insulating layer 3 is formed so as to recede from the main surface of n ⁻ -type single-crystal silicon substrate 1. The first insulating layer 3 is formed by thermal oxidation or CVD.
This is a silicon oxide film formed by a method.

Next, the surface of n ^- type single crystal silicon substrate 1 is washed with a hydrofluoric acid aqueous solution. By this processing, the exposed surface of the single crystal silicon of the n ⁻ type single crystal silicon substrate 1 becomes hydrophobic. Here, in this process, it is necessary to control so that the first insulating layer is not removed. For example, in the case where the first insulating layer 3 is a silicon oxide film formed by a thermal oxidation method, the first insulating layer is made of a hydrofluoric acid aqueous solution obtained by diluting 49% hydrofluoric acid (HF) with 200 times pure water. Layer etch rate is 2nm
/ Min, so that the treatment with the hydrofluoric acid aqueous solution is performed for 20 minutes or less.

Next, as shown in FIG. 1B, a filling liquid 4 is applied to the entire surface of the n ⁻ -type single-crystal silicon substrate 1.
Here, an inorganic glass coating liquid is used as the filling liquid 4. At this time, the surface of the first insulating layer 3 is hydrophilic and n ⁻
Since the surface of the type single crystal silicon substrate 1 is hydrophobic, the inorganic glass coating liquid serving as the filling liquid 4 adheres only to the first insulating layer 3 and is repelled on the surface of the n ⁻ type single crystal silicon substrate 1.

However, as shown in FIG. 1B, the surface of the n ^-- type single-crystal silicon substrate 1 is filled with a filling liquid 4a in the form of water droplets.
Remains. Therefore, the n ⁻ -type single-crystal silicon substrate 1 is rotated to remove the water-like filling liquid 4a. here,
The viscosity of the inorganic glass coating solution is preferably set to 2 × 10 ⁻³ Pa · S or less.

In this way, as shown in FIG. 1C, the filling liquid 4 is formed only on the surface of the first insulating layer 3 formed in the concave portion 2 of the n ^- type single crystal silicon substrate 1. Become.

Next, heat treatment at a low temperature is performed to remove the solvent in the filling liquid 4. Here, this heat treatment is performed at 150 ° C.
In a nitrogen atmosphere for about 20 minutes. In addition, the filling liquid 4 is thermally cured by this heat treatment, and its viscosity is increased, but it has thermal fluidity.

Next, the n ^- type single crystal silicon substrate 1 is placed in a mixed solution of an aqueous ammonia solution, a hydrogen peroxide solution and pure water, and the entire surface of the substrate becomes hydrophilic.

Next, as shown in FIG. 2A, the n ^- type single crystal silicon substrate 1 as the first semiconductor substrate and the n ⁺ type single crystal silicon as the second semiconductor substrate are formed. The heat treatment is performed with the substrate 5 being bonded. here,
The specific resistance of this n ⁺ type single crystal silicon substrate 5 is 0.005
0.03 Ω · cm. The temperature of this heat treatment is about 1100 ° C. During this heat treatment, the filling liquid 4 flows and fills the gaps, thereby enabling strong bonding between the n ⁻ -type single-crystal silicon substrate 1 and the n ⁺ -type single-crystal silicon substrate 5. Finally, the filling liquid 4 becomes a solid insulator, and becomes the second insulating layer 6 as shown in FIG.

Next, as shown in FIG. 2B, the SOI layer 7 is formed by grinding or polishing the n ⁻ -type single-crystal silicon substrate 1 to a predetermined thickness.

As described above, the second insulating layer and the first insulating layer 3 are laminated in a predetermined region on the n ⁺ -type single-crystal silicon substrate 5, and the SOI layer 7 is formed thereon. The SOI substrate is completed.

In the reference example described above, the bonding S
The single crystal silicon surface and the surface of the filling liquid 4 are mixed on one of the bonding surfaces of the OI substrate, that is, the surface of the n ⁻ -type single crystal silicon substrate 1. Then, the filling liquid 4 has thermal fluidity and is deformed to function as an adhesive.

For this reason, even if the flatness of the bonding surface is insufficient and there are irregularities of about 30 nm, the two single-crystal silicon substrates are sufficiently bonded. Then, even when the flatness of the bonding surface is insufficient, no void is generated on the bonding surface.

Next, a first embodiment of the present invention will be described with reference to FIGS. 3 and 4 are cross-sectional views in the order of manufacturing steps of the bonded SOI substrate of the present invention. Hereinafter, the structure of the semiconductor substrate of the present invention will be described in the description of the manufacturing process. The same components as those described in the above reference example are denoted by the same reference numerals.

As shown in FIG. 3A, a first insulating film mask 8 is formed on the surface of the n ⁻ -type single crystal silicon substrate 1,
On this first insulating film mask 8, a second insulating film mask 9 is formed. Here, the first insulating film mask 8 is formed of a silicon oxide film. The second insulating film mask 9 is formed of a silicon nitride film. Then, using the resist mask 10 as an etching mask, the first insulating film mask 8 and the second
The insulating film mask 9 is dry-etched. Furthermore, n
^- the surface of the type single crystal silicon substrate 1 is also concave portion 2 is dry-etched to form.

Next, the resist mask 10 is removed, and the surface of the recess 2 is thermally oxidized using the second insulating film mask 9 as a thermal oxidation mask. Then, as shown in FIG. 3B, an insulating layer 11 having a thickness of about 1 μm is formed.

Next, the second insulating film mask 9 is removed, and subsequently, the first insulating film mask 8 is removed by etching. In this step, the surface of the insulating layer 11 is also etched. In this way, as shown in FIG. 3C, the exposed surface 12 is formed on the surface of the n ⁻ -type single crystal silicon substrate 1, and the insulating layer 11 is formed in a predetermined region. Here, the level difference between the exposed surface 12 and the insulating layer 11 after the etching removal is 0.
It is controlled to be 1 μm or less.

Next, the entire surface of the n ^- type single crystal silicon substrate 1 is oxidized, and a silicon oxide film having a thickness of about 50 nm is formed on the entire surface.

Next, as shown in FIG. 4A, a resist mask 13 is formed, and impurity ions 14 are ion-implanted on the insulating layer 11 using this as a mask for ion implantation. Here, the impurity ions 14 are boron ions, phosphorus ions, arsenic ions, or the like. These doses are set to about 1 × 10 ¹⁵ / cm ² .

Then, the resist mask 13 is removed and a heat treatment is performed. Thus, the upper region of the insulating layer 11 becomes a silicon oxide film containing impurities of 10 ²⁰ atoms / cm ³ or more.

Next, the entire surface of the substrate is ground and polished. In this manner, as shown in FIG. 4B, an insulating layer 11 which is flush with the exposed surface 12 is formed on the surface of the n ⁻ -type single-crystal silicon substrate 1.

Next, as described in the reference example , the n ⁻ -type single-crystal silicon substrate 1 and the n ⁺ -type single-crystal silicon substrate 5 are bonded to each other and a heat treatment is performed. Then, n ⁻ -type single-crystal silicon substrate 1 and n ⁺ -type single-crystal silicon substrate 5 are firmly bonded. Further, n ⁻ -type single-crystal silicon substrate 1 is ground and polished to a predetermined thickness to form SOI layer 7.

As described above, the insulating layer 11 is formed in a predetermined region on the n ⁺ -type single crystal silicon substrate 5, and the bonded SOI substrate having the structure in which the SOI layer 7 is formed thereon is completed.

In the first embodiment, since the surface of the insulating layer 11 contains high-concentration impurities, it has thermal fluidity. For this reason, the insulating layer 1 having irregularities after thermal oxidation
1 is flattened. Further, as described in the reference example , the viscosity of the surface of the insulating layer 11 is reduced and easily deformed to function as an adhesive. Therefore, even if the flatness of the bonding surface is insufficient, the two single-crystal silicon substrates are sufficiently bonded. Then, no void is generated at the joint surface.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 corresponds to FIG. 4A described in the first embodiment. In this embodiment, that the impurity ions are selectively ion-implanted only to the end portion of the insulating layer is different from the first embodiment.

As described in the first embodiment, FIG.
The insulating layer 11 is selectively formed on the surface of the n ⁻ -type single-crystal silicon substrate 1 through the steps described in (1).

Next, as shown in FIG. 5, a resist mask 15 is formed. In this case, a region located at the end of the insulating layer 11 is exposed. Then, using this as a mask for ion implantation, impurity ions 14 are implanted into the end of the insulating layer 11. Here, the conditions of the ion implantation are shown in FIG.
This is the same as described in (a).

As described above, the insulating layer 1 after the thermal oxidation
The surface of No. 1 has considerable irregularities. This unevenness becomes particularly large at the end of the insulating layer 11. Therefore, by introducing a high-concentration impurity into this region to facilitate heat flow, the effect described in the first embodiment can be obtained.

The steps up to the bonding of the two single-crystal silicon substrates are the same as those in the first embodiment, so that the description will be omitted.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a sectional view of a part of the bonded SOI substrate of the present invention in the order of manufacturing steps. Here, the same components as those described in the first embodiment are denoted by the same reference numerals.

[0061] As shown in FIG. 6 (a), similarly to the first embodiment, n ^- first on the surface of type single crystal silicon substrate 1
An insulating film mask 8 is formed, and a second insulating film mask 9 is formed on the first insulating film mask 8. Here, the first insulating film mask 8 is formed of a silicon oxide film having a small thickness, for example, about 20 nm. The second insulating film mask 9 is
It is composed of a silicon nitride film which is considerably thicker than in the case of the first embodiment. Then, these are patterned by known photolithography technology and dry etching technology. Further, the surface of n ⁻ -type single-crystal silicon substrate 1 is also dry-etched to form recess 2.

Next, using the second insulating film mask 9 as a thermal oxidation mask, the surface of the concave portion 2 is thermally oxidized. And
As shown in FIG. 6B, an insulating layer 11 having a thickness of about 1.5 μm is formed.

Next, as shown in FIG. 6C, the second insulating film mask 9 is used as it is as a mask for ion implantation. Then, the impurity ions 14 are ion-implanted on the insulating layer 11. Here, conditions for ion implantation are the same as those described in the second embodiment.

The steps up to the bonding of the two single-crystal silicon substrates are the same as in the first embodiment, so that the description will be omitted.

In the method for manufacturing a bonded SOI substrate as described in the first to third embodiments, the adhesiveness of the bonded substrate is greatly improved, and the generation of voids and the like is completely suppressed. Is done.

Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a plan view and a cross-sectional view of a bonded SOI substrate wafer of the present invention. Here, the same components as those described in the above embodiment are denoted by the same reference numerals.

As shown in FIG. 7A, n having an insulating layer selectively formed as described in the above embodiment mode is used.
^{The −} type single crystal silicon substrate 1 is bonded to the n ⁺ type single crystal silicon substrate 5. Then, about 3 mm of the outer peripheral portion of the n ⁻ -type single crystal silicon substrate 1 is removed in the chamfering step.
By doing so, peeling of the wafer and cracking of the wafer in the step of manufacturing a device using the wafer of the bonded SOI substrate can be reduced.

Further, as shown in FIG. 7B, in the wafer state of the bonded SOI substrate, the insulating layer 11 is
So that it is completely covered with. That is, the insulating layer 11 is formed so as not to be exposed. By doing this,
In the process of manufacturing a device using a bonded SOI substrate wafer, there is no wafer peeling or wafer cracking.

On the other hand, as shown in FIG. 7C, when a part of the insulating layer 11 is exposed, the exposed insulating layer is exposed in a device manufacturing process, for example, a process of dipping in a hydrofluoric acid aqueous solution. Is etched away. And the cavity 16
Are formed between the n ⁺ -type single-crystal silicon substrate 5 and the SOI layer 7 at the edge of the wafer. In the device manufacturing process, the SOI layer in the 16 cavities becomes defective and becomes a source of particle contamination. Also in this respect, the structure of FIG. 7B is very effective.

Next, a fifth embodiment of the present invention will be described with reference to FIG. This embodiment is a combination of the reference example and the fourth embodiment. Here, FIG.
Is a cross-sectional view of the bonded SOI substrate wafer thus formed.

As shown in FIG. 8, a second insulating layer 6 and a first insulating layer 3 are selectively laminated on an n ⁺ -type single crystal silicon substrate 5. Then, the n ⁻ -type single-crystal silicon substrate is laminated and polished and polished to form an SOI layer 7.

Next, a predetermined region of the SOI layer 7 located on the first insulating layer 3 is etched to form a separation groove reaching the first insulating layer 3. Then, the surface of the isolation groove is oxidized, and an isolation insulating film 17 is formed. Further, this isolation groove is filled with a polycrystalline silicon film 18. Thus, an island-like SOI layer is formed.

[0073] In the above embodiment, n ^- if the type single crystal silicon substrate is n ⁺ type single crystal silicon substrate are bonded together is explained. The present invention is not limited to such bonding of semiconductor substrates. In addition, the present invention is similarly applied to the bonding of silicon substrates having different conductivity types. Further, it should be noted that the present invention can be similarly applied to bonding of different types of semiconductor substrates.

Although the case where a silicon oxide film is used for the insulating layer has been described in the embodiment, it should be noted that a silicon nitride film or a silicon oxynitride film can be used as the insulating layer.

[0075]

In the embodiment described above, a single crystal semiconductor crystal surface and an insulating layer surface are mixed on one bonding surface of a bonded SOI substrate. Then, this insulating layer has thermal fluidity and is deformed to function as an adhesive.

In the bonded SOI substrate wafer, the periphery of the SOI layer is removed in a chamfering step, and the insulating layer is formed so as not to be exposed from the SOI layer.

Therefore, even if the flatness of the bonding surface is insufficient, the two semiconductor substrates are sufficiently bonded. Then, even when the flatness of the bonding surface is insufficient, no void is generated on the bonding surface.

When a device such as an intelligent power IC is manufactured using the bonded SOI substrate of the present invention, the bonded SOI substrate does not peel or chip in the manufacturing process. Further, the method of the present invention is simple, and the manufacturing cost of the bonded SOI substrate is reduced.

As described above, the present invention improves the reliability of a power device such as an intelligent power IC and promotes its development.

[Brief description of the drawings]

FIG. 1 is a sectional view in the order of steps for explaining a reference example in the present invention.

FIG. 2 is a cross-sectional view in the order of steps for describing a reference example in the present invention.

FIG. 3 is a cross-sectional view in the order of steps for explaining the first embodiment of the present invention.

FIG. 4 is a cross-sectional view in the order of steps for explaining the first embodiment of the present invention.

FIG. 5 is a cross-sectional view in a process order for explaining a second embodiment of the present invention.

FIG. 6 is a sectional view illustrating a third embodiment of the present invention in the order of steps for explaining the third embodiment.

FIG. 7 is a plan view and a cross-sectional view of a wafer explaining a fourth embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a fifth embodiment of the present invention;
It is sectional drawing of an OI board.

FIG. 9 is a cross-sectional view illustrating a conventional technique in the order of manufacturing steps.

FIG. 10 is a cross-sectional view illustrating a related art in the order of manufacturing steps.

[Explanation of symbols]

1,104,201 n ^- type single-crystal silicon substrate 2 concave portion 3 first insulating layer 4,4a filling liquid 5,101,204 n ⁺ -type single-crystal silicon substrate 6 second insulating layer 7,107,107a, 207,207a SOI layer 8 First insulating film mask 9 Second insulating film mask 10, 13, 15 Resist mask 11, 102, 202 Insulating layer 12, 103 Exposed surface 14 Impurity ion 16 Cavity 17, 105, 205 Isolation insulating film 18, 106, 203,206 Polycrystalline silicon film

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-24641 (JP, A) JP-A-3-265154 (JP, A) JP-A-61-164238 (JP, A) JP-B-44 9025 (JP, B1) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/762 H01L 21/02 H01L 27/12

Claims (8)

(57) [Claims] An insulating layer having thermal fluidity is formed in a concave portion provided in a predetermined region of a main surface of the first semiconductor substrate, and a main surface of the first semiconductor substrate, a surface of the insulating layer, Second
Semiconductor substrate is adhered, and the back surface of the first semiconductor substrate is ground or polished to obtain a SO
The wafer of the bonded SOI substrate which is the I layer
Therefore, the SOI layer around the wafer has a constant width.
An SOI substrate which has been removed . . 2. The semiconductor device according to claim 1, wherein the first semiconductor substrate is a silicon semiconductor substrate of one conductivity type containing a low concentration impurity, and the second semiconductor substrate is a silicon substrate of the same conductivity type containing a high concentration impurity. 2. The SO according to claim 1, wherein
I substrate. 3. The S according to claim 1, wherein the insulating layer is formed of an inorganic glass coating liquid applied on the first insulating layer adhered to the recess.
OI substrate. 4. The SOI substrate according to claim 1, wherein a high concentration impurity is contained in a surface of said insulating layer. 5. The SOI substrate according to claim 1, wherein said insulating layer is completely covered with said SOI layer and formed so as not to be exposed to the outside. . 6. A step of etching a predetermined region of the main surface of the first semiconductor substrate to form a concave portion, a step of selectively forming an insulating layer in the concave portion, and a step of selectively forming a surface portion of the insulating layer. Ion-implanting a high-concentration impurity into the first semiconductor substrate and heat-treating the insulating layer. Then, a second semiconductor substrate is brought into close contact with the main surface of the first semiconductor substrate, and a high-temperature heat treatment is performed. Bonding the semiconductor substrate to the second semiconductor substrate,
A method for manufacturing an SOI substrate, comprising: 7. The method for manufacturing an SOI substrate according to claim 6 , wherein the ion implantation of the high-concentration impurity is performed only on a surface portion of the insulating layer formed at an end of the concave portion. 8. A step of bonding the first semiconductor substrate and the second semiconductor substrate and then chamfering only a peripheral portion of the first semiconductor substrate, and after the chamfering, the first back surface. claim, characterized in that it comprises a step of the first semiconductor substrate to grinding and polishing the side in the SOI layer 6 or claim 7
The manufacturing method of the described SOI substrate.