JPH11126910A - Manufacture of semiconductor substrate for pressure sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin diaphragm with accuracy in a semiconductor pressure sensor which has a pressure reference chamber. SOLUTION: A hydrogen ions are implanted at high density to a given depth in an ion-implantation layer forming step P1, to form an ion-implantation layer in a first substrate. A recessed part for a reference chamber and a pressure- reducing though-hole are formed by etching in a second substrate in a recessed part forming step P2. The first and second substrates are bonded in a bonding step P3. The first substrate is peeled at its ion-implantation layer by high- temperature heat treatment in a peeling step P4 for forming a semiconductor layer on the second substrate. A signal processing circuit element is formed in an element forming step 5. The inside of the pressure reference chamber is reduced in pressure to a vacuum state althrough a pressure reducing through- hole by using a CVD method and sealed by forming a protective film in a reduced pressure sealing step P6. In this case, the semiconductor layer covering the pressure reference chamber functions as a diaphragm, so its thickness is made accurate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate used in a pressure sensor which electrically detects a pressure applied to a diaphragm based on a stress generated by a pressure difference from a pressure reference chamber.

[0002]

Some semiconductor pressure sensors for detecting the pressure applied to a diaphragm have a pressure reference chamber provided therein. In this case, the pressure reference chamber is in a state in which the inside is decompressed to a state close to a vacuum, thereby suppressing fluctuations in the internal pressure due to temperature fluctuations and the like and improving the detection accuracy of the pressure applied to the diaphragm. It is what it was.

As a semiconductor substrate used for manufacturing such a semiconductor pressure sensor, a semiconductor substrate in which a portion corresponding to the above-described pressure reference chamber is formed in advance is provided. this is,
For example, a method in which a pressure reference chamber and a diaphragm are formed by a bonding technique using two single crystal silicon substrates.

[0004] First, a recess for a pressure reference chamber is formed in a silicon substrate as a support substrate by a method such as etching. This silicon substrate and a separately prepared silicon substrate for forming a diaphragm are bonded by a bonding technique. Next, the thickness of the bonded silicon substrate for the diaphragm is adjusted by grinding and polishing until the thickness of the silicon substrate reaches the thickness of the diaphragm. Thus, the pressure reference chamber is provided on the silicon substrate as the support substrate, and the diaphragm can be formed so as to cover the pressure reference chamber.

However, after bonding as described above, the substrate for forming the diaphragm is ground and
The polishing method is uneconomic in that a silicon substrate for forming a diaphragm needs to be polished until a desired thickness of the diaphragm is obtained, and most of the bonded silicon substrate is removed by grinding and polishing. At the same time, it is technically difficult to polish itself to leave a thin film portion such as a diaphragm in terms of controllability.

In the control of the film thickness by the polishing process, it is difficult to polish while directly measuring the film thickness of the silicon substrate left by polishing. For example, the polishing speed is measured and the desired thickness is controlled by time management. There is a method of controlling so as to leave, or a method of providing a polishing stopper in advance on a silicon substrate to be polished.

In the method of providing a polishing stopper, for example,
A groove of a predetermined depth dimension is formed on the diaphragm side of the silicon substrate, and the inside of the groove is filled with silicon oxide, and from the back side to the position where the bottom part of this silicon oxide is exposed during polishing. When reached, the polishing of silicon is automatically stopped because the oxide film has a lower polishing rate than silicon.

However, even when polishing is performed with good controllability by using such various techniques, as long as the polishing method is employed, deflection is caused at the portion where the recess for the pressure reference chamber is present during polishing. It is easy to occur, and it is difficult to form the thickness of the diaphragm portion uniformly. In addition, it is also difficult to make the thickness dimensions of the plurality of diaphragms formed in the substrate uniform.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a method of manufacturing a semiconductor substrate for a pressure sensor capable of forming a diaphragm with a uniform thickness and good dimensional accuracy. Is to provide.

[0010]

According to the first aspect of the present invention, the pressure sensor has a structure in which a pressure received by a diaphragm is electrically detected based on a stress generated by a pressure difference from a pressure reference chamber. In the case of a semiconductor substrate, an ion-implanted layer for peeling is formed at a predetermined depth of a first semiconductor substrate for forming a diaphragm by an ion-implanted layer forming step, and a pressure reference chamber is formed by a concave portion forming step. The second substrate is provided with a recess for a pressure reference chamber, the first and second substrates are bonded in a bonding step, and the first substrate bonded in a subsequent peeling step is bonded to the ion-implanted layer portion. By forming a semiconductor layer on the surface of the second substrate by peeling off the substrate, a diaphragm and a pressure reference chamber are formed, so that a diaphragm having a desired thickness dimension is controlled in the depth of the ion implantation layer. It is possible to precisely form by grinding, since the unnecessary processing by methods such as grinding can be manufactured in a simple and short, and further,
The first substrate can be reused, so that the cost can be reduced.

According to the second aspect of the present invention, in the concave portion forming step, the concave portion is formed by etching the surface of the second substrate, so that the semiconductor layer serving as the diaphragm and the pressure reference chamber can be formed. Become like

According to the third aspect of the present invention, a semiconductor layer for forming a diaphragm is provided through a bonding step and a peeling step. At this time, an oxide film is provided between the second substrate and the semiconductor layer. Is provided, the semiconductor layer can be formed in a state in which the semiconductor layer is insulated and separated from the second substrate. For example, in a region of the semiconductor layer other than the diaphragm portion, a so-called SOI (Silicon) is formed.
A circuit element for signal processing can be formed on a semiconductor layer having an On Insulator structure, and a MOS element and a bipolar element can be integrated on the same chip.

According to the fourth aspect of the present invention, in the concave portion forming step, the column portion is formed on the bottom surface of the concave portion for the pressure reference chamber and has the same length as the depth dimension and can be selectively etched. In the step of bonding to the first substrate using the part, it is possible to adhere to the tip of the pillar part even in the region inside the concave part, and in the peeling step, the semiconductor for reliably forming the diaphragm The layers can be peeled off.

In particular, when forming an ion-implanted layer at a shallow position on the first substrate in order to reduce the thickness of the diaphragm, the semiconductor layer to be peeled becomes thin. The diaphragm can be formed more reliably than in the case where there is no support portion. In addition, even when the dose of the ion-implanted layer formed in the ion-implanted layer forming step is insufficient, the semiconductor layer can be reliably formed by peeling.

According to the fifth aspect of the present invention, in the recess forming step, the support formed on the inner bottom surface of the recess is constituted by a plurality of supports, so that the coupling force with the surface of the first substrate is further increased. In the case where a diaphragm having a small thickness is to be formed, the peeling of the semiconductor layer can be reliably performed.

According to the sixth and seventh aspects of the present invention, in the recess forming step, the pillar is formed by providing a pattern for forming the pillar during the etching process for forming the recess in the second substrate. Since the pillar portion is made to be an oxide by performing a thermal oxidation process, it is possible to perform a selective etching process. Therefore, when the first substrate is bonded, the pillar portion provided on the surface of the second substrate and the concave portion is provided. After the semiconductor layer is peeled and formed through a peeling step in a state where it is bonded to the support, the support can be removed by selective etching using a hydrofluoric acid aqueous solution or the like so that the diaphragm can be formed. Become.

According to the present invention, the recess for the pressure reference chamber formed on the second substrate is formed in the second step in the oxide film forming step.
Since an oxide film is formed on the surface of the substrate and a recess is formed by forming an opening in the oxide film in the recess forming step, for example, in a configuration in which a recess having a shallow depth dimension is provided, an etching process is performed. The recess for the pressure reference chamber can be formed by adopting a process that simplifies the process described above, and a recess having no depth variation due to etching can be formed.

According to the ninth aspect of the present invention, the semiconductor layer in the predetermined region other than the diaphragm portion of the semiconductor layer formed on the surface of the second substrate is removed by the semiconductor layer removing step performed after the peeling step. As a result, a region for forming an element is exposed on the surface of the second substrate.
Even when the element formation cannot be performed sufficiently with the thickness of the semiconductor layer for the diaphragm, the element can be formed on the second substrate side. The degree of heat dissipation can be increased, and the heat radiation effect of the element to be formed can be enhanced.

According to the tenth aspect of the present invention, in the recess forming step, the pressure reducing chamber is formed with a depressurizing communication section in which the recess for the pressure reference chamber communicates with the outside, and the depressurizing sealing step performed after the peeling step performs the depressurizing communication step. The pressure reference chamber is depressurized and sealed via the depressurization communication hole formed by the part, so that the pressure reference chamber is depressurized or vacuumed to minimize the gas contained therein to reduce the pressure reference due to temperature fluctuations etc. A configuration for suppressing the pressure fluctuation in the room and performing a more accurate pressure detection operation can be formed simply and with good controllability.

According to the eleventh aspect of the present invention, in the concave portion forming step, the pressure reducing communication portion is formed as a groove along the surface portion of the second substrate, and the surface portion is formed by the semiconductor layer formed after the peeling step. , The pressure-reducing communication hole is formed, so that the pressure-reducing communication hole can be formed using the process for forming the diaphragm, and can be easily performed without adding a special process. .

According to the twelfth aspect of the present invention, in the recess forming step, the depth dimension of the communication section for pressure reduction is formed to be the same as the depth dimension of the recess. Therefore, the number of steps can be reduced and the device can be easily manufactured.

According to the thirteenth aspect of the present invention, in the recess forming step, the pressure reducing communication hole is formed as an opening communicating with the back surface of the second substrate. By reducing the pressure in the pressure reference chamber from the back side and sealing the opening, it is possible to obtain the same characteristics.

According to the fourteenth aspect of the present invention, in the reduced pressure sealing step, a film is formed by a CVD method in a reduced pressure atmosphere so as to seal the opening of the communication hole for pressure reduction. The decompression sealing step can be performed without performing. Then, when a protective film or the like is formed on the final surface, a reduced-pressure sealing step can be performed at the same time as performing the step of forming the protective film. Can be carried out without adding a special step.

According to the fifteenth aspect of the present invention, since the non-single-crystal layer such as the amorphous layer or the polycrystalline layer is included in the layer for forming the semiconductor layer by performing the bonding, the first substrate is formed. The semiconductor layer can be formed in a state where the mechanical strength of the semiconductor layer portion formed by separation is increased as compared with the case where the bonding step and the separation step are performed while the surface layer portion of the semiconductor layer remains single crystal. .

According to the sixteenth to eighteenth aspects of the present invention, the non-single-crystal layer is configured so that its constituent elements include the same kind of constituent elements as those of the first semiconductor substrate (4). It is possible to provide a non-crystalline layer or a polycrystalline layer of exactly the same element alone, or a non-single-crystal layer of a compound of the same kind of element, so that the non-single-crystal layer can be easily formed. Further, when a silicon substrate is used as the first semiconductor substrate, an amorphous silicon film or a polycrystalline film, which is an amorphous silicon film, is used as the non-single-crystal film, or a silicon oxide film, a silicon nitride film, or the like is used. A film or the like can be used. Thus, as described above, the mechanical strength of the semiconductor layer portion formed by separation is increased as compared with the case where the bonding step and the separation step are performed while the surface layer of the first substrate remains single crystal as in the above. A semiconductor layer can be formed.

According to the nineteenth aspect of the present invention, the non-single-crystal layer is formed on the surface of the first semiconductor substrate by a deposition method. A non-single-crystal layer can be formed using a selective film-forming method or the like, and a non-single-crystal layer can be easily and inexpensively provided without using a special process.

According to the twentieth aspect of the present invention, since the non-single-crystal layer is formed in the first semiconductor substrate by the ion implantation method, for example, a material having a relatively large ion mass is selected by the ion implantation method. By embedding in the inside, it becomes possible to form an amorphous layer as a non-single-crystal layer on the substrate surface or an arbitrary region inside.

According to the twenty-first aspect, when the non-single-crystal layer is made of the same element as that of the first semiconductor substrate, heat treatment is performed after the separation step to recrystallize the non-single-crystal layer. As a result, the semiconductor layer is formed as a single-crystal layer, so that the mechanical strength of the semiconductor layer in the bonding and peeling steps is improved while the single-crystal layer is formed as the same as the configuration of the finally obtained semiconductor substrate. As a result, a stable electrical characteristic can be obtained for the characteristic of the pressure sensor as a diaphragm.

According to the twenty-second aspect, a semiconductor substrate having an oxygen concentration of 1 × 10 ¹⁸ atoms / cm ³ or more is used as the first substrate, so that the first substrate has a mechanical strength lower than that of a semiconductor substrate used for normal use. Higher, the handling performance in the processing step is improved, and the reliability is improved.

According to the twenty-third aspect, when bonding the first substrate and the second substrate, the direction of the side of the opening of the concave portion on the second substrate and the direction of cleavage of the first substrate Positioning is performed by adjusting in the direction that intersects with the substrate, so that when peeled in the peeling step, the portion located in the recessed region of the second substrate is cleaved by the impact received by the peeling. It is possible to prevent the occurrence of such a phenomenon and to prevent a decrease in mechanical strength, and it is possible to reliably form the diaphragm portion.

According to the twenty-fourth and twenty-fifth aspects of the present invention, in the above case, the direction of the side of the opening of the recess formed on the second semiconductor substrate and the cleavage direction of the first substrate have the largest angle. For example, when the plane orientation of the first semiconductor substrate is (100), the angle is adjusted so as to intersect with an angle centered at 22 to 23 °. By doing so, it is possible to maximize the effects described above,
It can be manufactured with good reproducibility while increasing the mechanical strength.

According to the twenty-sixth aspect, in the cleaning step performed prior to the bonding step, at least the second semiconductor substrate of the first and second semiconductor substrates to be bonded is made hydrophobic. The treatment removes the moisture attached to the surface during the dehydration process, so that it is possible to prevent moisture from remaining on the surface of the substrate and in the formed concave portion as much as possible, and to adhere to the substrate during bonding. It is possible to prevent moisture from remaining at the interface portion to be formed or moisture from remaining in the concave portion to suppress deterioration of characteristics.

According to the twenty-seventh aspect of the present invention, since the bonding step is performed in a reduced-pressure atmosphere, when the first substrate and the second substrate are brought into close contact with each other, moisture remaining on the surface of the substrate or the concave portion is removed. The removal can be carried out after sufficient dehydration in a reduced-pressure atmosphere, so that the adhesion can be improved. Further, when the recess is sealed in a reduced pressure state by the bonding step, it is not necessary to separately perform a step for degassing the inside of the recess in a later step, so that the number of steps can be reduced. Become like

According to the twenty-eighth aspect of the present invention, an insulating film separating substrate in which a semiconductor layer is formed on a supporting substrate via an insulating film is used as the second substrate, and the pressure reference chamber is the insulating film separating substrate. Because it is formed in the semiconductor layer of
A diaphragm and a pressure reference chamber can be formed on an insulating film separation substrate, thereby enabling a pressure sensor control circuit to be formed in an insulating film separation region located around the pressure reference chamber, thereby forming an element isolation structure. And electrical characteristics such as withstand voltage can be improved.

According to the twenty-ninth aspect of the present invention, the second substrate region is removed from the back surface of the insulating film separation substrate bonded on the second substrate by a method such as grinding or polishing using the buried insulating film as a stopper. Thereafter, the buried insulating film is selectively removed by a method such as etching, so that only the semiconductor layer can be formed on the second substrate. In this way, by forming the semiconductor layer on the surface of the insulating film separation substrate in a state where the thickness of the semiconductor layer is uniform, the thickness of the semiconductor layer in a portion to be a diaphragm after bonding is formed with the formation accuracy. It is possible to relatively easily provide a diaphragm as designed with high accuracy.

According to the thirty-fifth aspect of the present invention, in the above case, as a method of forming the insulating separation substrate, an ion implantation layer is formed at a predetermined depth of the third substrate, and the ion implantation layer is bonded to the fourth substrate. In addition, since the semiconductor layer is formed by peeling at the portion of the ion-implanted layer, it is possible to obtain an insulating separation substrate in which a semiconductor layer having a desired thickness is accurately formed,
The semiconductor layer to be formed on the diaphragm can be formed relatively easily and accurately with a uniform film thickness.

According to the thirty-first aspect of the present invention, in the above case, the ion implantation layer is formed in the insulating film separating layer of the insulating film separating substrate or deeper than the insulating film separating layer, and is bonded to the second substrate. After the alignment, the insulating film separation substrate can be separated at the portion of the ion implantation layer. Thereafter, the semiconductor layer can be formed over the second substrate by removing the buried insulating layer. Therefore, it is possible to easily remove the supporting substrate portion of the insulating film separation substrate by eliminating the steps such as grinding and polishing to remove the supporting substrate portion. It can be used as a support substrate for an insulating film separation substrate.

According to the thirty-second aspect of the present invention, in the recess forming step, the recess is formed by etching the surface of the second substrate, so that the semiconductor layer serving as the diaphragm and the pressure reference chamber can be formed. Become like

According to the thirty-third aspect of the present invention, since the bonding step is performed in a reduced-pressure atmosphere, when the first substrate and the second substrate are brought into close contact with each other, moisture remaining on the surface of the substrate or the concave portion is removed. The removal can be carried out after sufficient dehydration in a reduced-pressure atmosphere, so that the adhesion can be improved. Further, when the recess is sealed in a reduced pressure state by the bonding step, it is not necessary to separately perform a step for degassing the inside of the recess in a later step, so that the number of steps can be reduced. Become like

According to the thirty-fourth aspect of the present invention, as the second substrate, an insulating film separating substrate having a semiconductor layer formed on a supporting substrate via an insulating film is used, and the pressure reference chamber is formed of the insulating film separating substrate. Because it is formed in the semiconductor layer of
A diaphragm and a pressure reference chamber can be formed on an insulating film separation substrate, thereby enabling a pressure sensor control circuit to be formed in an insulating film separation region located around the pressure reference chamber, thereby forming an element isolation structure. And electrical characteristics such as withstand voltage can be improved.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG.
(E) shows a schematic cross section of the sensor chip 1 as a semiconductor substrate for a pressure sensor, and shows a second substrate serving as a support substrate.
Formed on a single-crystal silicon substrate 2 as a first substrate with a silicon oxide film 3 interposed therebetween using a single-crystal silicon substrate 4 (see FIG. 2) as a first substrate for forming a diaphragm. A single-crystal silicon film 5 as a semiconductor layer having a predetermined thickness is formed, and a diaphragm 6 is provided.

In the center of the sensor chip 1, a pressure reference chamber 7 is provided.
Is provided, and the pressure is reduced so that the inside is substantially in a vacuum state. On the side of the pressure reference chamber 7, there is formed a pressure-reducing communication hole 8 which is open to the outside so as to communicate with the pressure reference chamber 7. As will be described later, the inside of the pressure reference chamber 7 is depressurized through the pressure-reducing communication hole 8. After that, the opening 8a is sealed with a protective film 9 to form a reduced pressure state.

A resistor 10 having a piezoresistive effect for pressure detection is formed on the diaphragm 6, and a signal processing circuit is formed on the single-crystal silicon film 5 located around the pressure reference chamber 6. Various circuit elements 11 such as MOS transistors are formed, and a detection output is obtained by amplifying and processing a pressure detection signal detected by the resistor 10.

According to the above configuration, when the diaphragm 6 receives a pressure from the outside, a force corresponding to a difference between the pressure and the pressure reference chamber 7 acts to generate a distortion. Since the resistance of the resistor 10 formed on the diaphragm 6 changes due to this distortion due to the piezoresistance effect, this is detected as a change in voltage by a circuit connected in a bridge, and is detected as a detection signal corresponding to the pressure by a signal processing circuit. Can be output.

In this case, since the pressure inside the pressure reference chamber 7 is reduced to a substantially vacuum state, unlike the state in which a gas is present, the internal pressure does not fluctuate due to the temperature change of the measurement environment, so that the accuracy is always high. The pressure detection operation can be performed. Further, in the above-described configuration, since the diaphragm 6 is formed by the single-crystal silicon film 5 formed as described later using the single-crystal silicon substrate 4 as the first substrate, a thin film is formed uniformly and accurately. Therefore, the stability and accuracy of the pressure detection accuracy can be improved.

Next, the manufacturing process of the above-described pressure sensor will be described. FIG. 1 shows an outline of the manufacturing process. Hereinafter, the manufacturing process will be described with reference to FIGS. 2 and 3. (1) Ion-implanted layer forming step (P1) First, a single-crystal silicon substrate 4 as a first substrate is prepared with at least one surface thereof mirror-polished, and ion implantation is performed on the mirror-polished surface side. Implants, for example, hydrogen ions (protons) to form a high-concentration ion-implanted layer 12
Is formed (see FIG. 2). In this case, the single-crystal silicon substrate 4 has, for example, an oxygen concentration of 1 × 10 ¹⁸ atoms / cm ³ higher than that used for a normal device.
As described above, the material formed to have a density of about 5 × 10 ¹⁸ atoms / cm ³ is used, thereby increasing the mechanical strength. The oxygen concentration is 1 × 10 ¹⁸ to 1 × 10 ²⁰ atom
s / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 1
A range of 0 ¹⁹ atoms / cm ³ is suitable.

The depth at which the ion-implanted layer 12 is formed is set to a predetermined depth according to the acceleration voltage and the dose, and is provided corresponding to the thickness of the diaphragm 6 to be formed. The dose of the ion implantation layer 12 is 1 × 10 ¹⁶ atoms / cm ² or more, for example, 5 × 10
^Although it is set to ¹⁶ atoms / cm ² , the larger the dose, the better the peeling property in the peeling step P4. By forming an oxide film in advance on the side where ions are implanted, it is possible to alleviate damage to the surface layer due to ion implantation and reduce impurity contamination.

(2) Concavity Forming Step (P2) Next, a single crystal silicon substrate 2 as a second substrate is prepared in a state where at least one surface thereof is mirror-polished, and the surface side on which the mirror polishing is performed Recess 2a for pressure reference chamber 7
Is formed by dry etching or wet etching with an aqueous solution such as TMAH or KOH (a potassium hydroxide solution). In addition,
If the bonding is not performed under a reduced pressure atmosphere such as a vacuum atmosphere in the bonding step (P3) in the subsequent step, at this time, the groove 2b as the pressure reducing communication portion is similarly formed by dry etching or KOH. It must be formed by a method such as wet etching (see FIG. 3).

In this case, the recess 2a for the pressure reference chamber 7 is
Appropriate dimensions are adopted depending on the range and magnitude of the pressure to be measured, but one side is 10 to 1000 μm
For example, a square shape of about 100 μm is set within the range of about 1 μm, and an appropriate dimension is set within a range of about 1 to 10 μm. The groove 2b has, for example, a width dimension of 1
The length is set to about 10 μm in the range of about 100 μm, and the length dimension is set to about several hundred μm in the range of about 10 to 1000 μm.

Then, on the surface of the single crystal silicon substrate 2,
The oxide film 3 is formed by a method such as thermal oxidation or a CVD method. This oxide film 3 may be simultaneously formed on the side wall and the bottom surface of the recess 2 a and the groove 2 b of the single crystal silicon substrate 2.

(3) Bonding Step (P3) Next, the surface of the single crystal silicon substrate 2 on which the concave portion 2a is formed is bonded to the surface of the single crystal silicon substrate 4 on which the ion implantation layer 12 is formed (FIG. 4). (A)). In the substrate cleaning step performed prior to the bonding step P3, the ion-implanted single-crystal silicon substrate 4 is completely removed by using a hydrofluoric acid aqueous solution or the like to completely remove the oxide film 4a for preventing contamination formed on the surface. The surface can be removed for contamination and flattened. After that, a natural oxide film is formed on the surface to be hydrophilic by washing with a treatment solution or the like in which H ₂ SO ₄ and H ₂ O ₂ are mixed at a ratio of 4: 1.

For the single crystal silicon substrate 2,
After forming a, a natural oxide film is formed by washing with a processing solution or the like in which H ₂ SO ₄ and H ₂ O ₂ are mixed at a ratio of 4: 1 to make the surface hydrophilic. Then, two single-crystal silicon substrates 2,
Bonding is performed by bringing 4 into close contact. Regarding the substrate cleaning, cleaning is performed by using a processing solution in which H ₂ SO ₄ and H ₂ O ₂ are mixed at a ratio of 4: 1 without removing the oxide film 4 a for preventing contamination on the single crystal silicon substrate 4. By removing contaminants on the surface, planarization can be performed, and bonding can be performed.

In the above case, a hydrofluoric acid solution or the like is used instead of performing the hydrophilization treatment by washing using a treatment solution or the like in which H ₂ SO ₄ and H ₂ O ₂ are mixed at a ratio of 4: 1. Applying a hydrophobic treatment by washing with water is also an effective means. In comparison with the case where the hydrophilic treatment is performed, performing the hydrophobic treatment lowers the bonding strength between the substrates, but the bonding itself can be performed. Performing this hydrophobizing treatment also increases the adhesion strength, and performing the bonding in a vacuum has a great effect of preventing gas remaining in the bonding surface.

In other words, when bonding is performed in a vacuum (in a reduced pressure atmosphere) in the state where the hydrophobic treatment is performed, generation of an unbonded region due to gas, moisture, or the like existing at the interface can be prevented. In addition, the diaphragm 6 can be prevented from being damaged by a decrease in the degree of vacuum due to moisture remaining in the pressure reference chamber 7 and expansion of the moisture, and a stable product can be manufactured. Further, by performing the bonding in a vacuum, it is not necessary to separately perform a reduced pressure sealing step.

In the step of bonding the single-crystal silicon substrates 2 and 4, the single-crystal silicon substrate 4 is bonded to the side of the quadrilateral forming the opening of the recess 2a on the single-crystal silicon substrate 2 side. When the direction is parallel to the direction of the cleavage plane when the cleavage is performed, the strength is disadvantageous. Therefore, it is preferable that the bonding is performed by arranging in a direction that intentionally avoids this. (FIG. 5
(See (a) and (b)). Thereby, in a peeling step described later, the effect of preventing damage at the portion corresponding to the pressure reference chamber 7 by the force received by the impact at that time is enhanced.

In this case, for example, the single crystal silicon substrate 4
When the plane orientation of (100) plane is used, the plane orientation that is easily cleaved is, as shown in FIG.
Appear as lines parallel or orthogonal to the direction of
There is a (110) plane which appears as a 0) plane or a line inclined at 45 ° in the OF direction. Therefore, in order not to be parallel to this direction, a direction having an inclination so as to form the largest angle with respect to both of them is, for example, 22 to 23.
It is effective to set the temperature to about 25 ° (accurately, 22.5 ° = 45 ° / 2) and stick them together. As a result, the mechanical strength can be increased, breakage can be prevented even at the time of peeling, and a product of good quality can be obtained.

(4) Peeling Step (P4) Thereafter, the bonded single-crystal silicon substrates 2 and 4 are subjected to a heat treatment in a nitrogen atmosphere or an oxygen atmosphere. In this heat treatment, for example, a temperature in the range of 400 ° C. to 600 ° C. and 5
There is a method in which the first heat treatment performed at about 00 ° C. and the second heat treatment performed at about 1000 ° C. or more and about 1100 ° C. are sequentially performed, and a method in which the temperature is continuously increased and performed at once.

By performing this heat treatment, a dehydration condensation reaction occurs on the bonding surfaces of the two substrates 2 and 4,
The bonding state can be made stronger. Also,
In the hydrogen ion-implanted layer 12, defects are locally concentrated by this heat treatment, and bubbles are generated, so that the surface is separated (see FIG. 4B).

Thus, the single-crystal silicon film 5 having a thickness of, for example, about 2 μm (for example, preferably formed in a range of about 1 to 10 μm) on the surface of the single-crystal silicon substrate 4 is formed on the single-crystal silicon substrate 2 side. The pressure reference chamber 7 and the diaphragm 6 can be formed because they are left in the bonded state. Thereafter, the surface of the separated single crystal silicon film 5 is reduced in surface roughness by a method such as polishing to improve smoothness. In addition, this polishing process,
This is not always necessary when the next element formation step is not performed.

(5) Element Forming Step (P5) In the above state, the single crystal silicon film 5 is formed on the single crystal silicon substrate 2 as the second substrate by the oxide film 3 as the insulating film.
, The substrate structure is an SOI (Silicon On Insulator) structure. On the single crystal silicon film 5, a resistor 10 having a piezoresistive effect for pressure detection is formed, and various elements 11 such as MOS transistors constituting a signal processing circuit are formed.
Is formed (see FIG. 3C). The resistor 10 is wired so that a bridge circuit is formed by the wiring pattern, and the input / output terminals are wired so as to be connected to the signal processing circuit.

(6) Pressure Reduction Sealing Step (P6) Next, in the bonding step P2, when manufacturing a type in which bonding is not performed in a vacuum atmosphere,
Since it is necessary to reduce the pressure in the pressure reference chamber 7 to a vacuum or a predetermined pressure, a pressure reduction sealing step P6 described below is performed. That is, an opening 8a is formed in the single crystal silicon film 5 at the end of the pressure reducing communication hole 8 formed by the groove 2b and the single crystal silicon film 5 opposite to the pressure reference chamber 7 (FIG. )reference). In this case, the opening 8a is formed from the surface side of the single crystal silicon film 5 by an etching process or the like.

Thereafter, the insulating protection film 9 is formed on the surface of the single crystal silicon film 5 formed as described above by a CVD apparatus or the like.
Is formed, the opening 8a is simultaneously sealed under reduced pressure. The pressure in the pressure reference chamber 7 is reduced through the pressure reducing communication hole 8 by decompressing the pressure reference chamber 7 while placing it in the CVD apparatus and exposing it to a vacuum atmosphere. In a state where the inside is evacuated, an insulating protective film 9 such as a silicon nitride film or a silicon oxide film is formed by depositing over the entire surface, thereby forming the opening 8.
a is simultaneously sealed. Thereafter, the protective film 9 on the diaphragm 6 is peeled off by photolithography to form the sensor chip 1.

According to the first embodiment, when forming the diaphragm 6 having the pressure reference chamber 7 therein, the single-crystal silicon Since the film is formed by performing heat treatment and peeling after bonding the substrate 4, a uniform and thin film is formed as compared with the conventional method of controlling the film thickness of the diaphragm to a predetermined size by polishing after bonding. Thick diaphragm 6 can be formed with good reproducibility,
As a result, a pressure sensor with high detection accuracy can be provided.

Further, according to the first embodiment, the pressure reference chamber 7 can be formed in a substantially vacuum state by the decompression sealing step P6, so that the pressure in the pressure reference chamber 7 can be set accurately. Thus, it is possible to provide a pressure sensor capable of performing a highly accurate pressure detection operation while minimizing a pressure change in the pressure reference chamber 7 due to a change in the environmental temperature.

In the above embodiment, the sensor chip 1 having the structure in which the oxide film 3 is interposed between the single-crystal silicon substrates 2 and 4 has been described. Instead, for example, the oxide film 3 is provided. There may be no configuration. In other words, when the single crystal silicon substrates 2 and 4 are directly bonded to each other instead of the SOI structure, and there is no restriction as a signal processing circuit of the sensor chip, the single crystal silicon film 5 has such a configuration. The circuit element 11 can be formed in the portion.

When the diaphragm 6 is formed thick, a bipolar element can be formed. In the case where the oxide film 3 is not provided, heat generated in the signal processing circuit is easily transmitted to the single crystal silicon substrate 2 as the second substrate. The effect is enhanced, and the operation characteristics are improved.

Further, an insulating film separation substrate can be used as the second semiconductor substrate for forming the recess 2a. As a result, the diaphragm 6 and the pressure reference chamber 7 can be formed on the insulating film separation substrate, and a pressure sensor control circuit for processing an electric signal obtained from the diaphragm 6 and the pressure reference chamber 7 is provided around the pressure reference chamber 7. When it is formed in a region, it can be provided in a state where it is insulated and separated from the supporting substrate side of the base,
The element isolation structure can be easily formed, and the performance can be improved in terms of electrical characteristics such as withstand voltage of the circuit element to be formed.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
This embodiment is different from the first embodiment in that the depths of the recess 2a and the groove 2b formed on the surface of the single-crystal silicon substrate 2 as the second substrate are set to the same size. That is. That is, in the recess forming step P2, a photoresist pattern as shown in FIG. 7B is formed on the surface of the single crystal silicon substrate 2, and the etching process is performed simultaneously in this state, whereby the recess 2 is formed.
Thus, a concave portion 2c is formed in which a and the groove 2b are integrated at the same depth.

In this case, when there is no structural restriction in the pressure measurement conditions and the like, the concave portion 2a and the groove portion 2b in the first embodiment are integrated into the concave portion 2c by one photolithography. Since it can be formed by processing, there is an advantage that the number of steps is reduced.

(Third Embodiment) FIG. 8 to FIG.
The third embodiment of the present invention is different from the first embodiment in that a MOS circuit element 1 for a signal processing circuit is used.
The semiconductor layer removing step Q1 is provided after the peeling step P4 so as to remove the portion of the semiconductor layer 5 located at the peripheral part of the diaphragm 6 where 1 has been formed.

That is, in the first embodiment, an M element such as a MOS transistor is used as an element for a signal processing circuit.
OS circuit element 11 (can be formed in an area of 2-3 μm in depth)
Since the configuration in which the single crystal silicon film 5 is formed is intended, the single crystal silicon film 5 used as the diaphragm 6 can be formed even when the film thickness is relatively small.

However, for example, when an attempt is made to form a bipolar element 13 (see FIG. 9E) such as a bipolar transistor often used in a signal processing circuit of a sensor, a depth of about 10 μm is used in a normal configuration. Since the size of the diaphragm 6 is required, when the diaphragm 6 is formed thin, the size of the junction depth is particularly restricted, and it may be difficult to form a circuit configuration.

Therefore, the third embodiment provides a sensor chip 14 having a structure which is not restricted by the thickness of the single crystal silicon film 5 forming the diaphragm 6.
In this configuration, as a region for forming a bipolar circuit element 13 such as a bipolar transistor, the surface 15 of the single crystal silicon substrate 2 as the second substrate is partially exposed and formed there.

Next, a method of manufacturing the sensor chip 14 having the above configuration (see FIG. 8) will be described. The ion-implanted layer forming step P1, the concave part forming step P2, the bonding step P3, and the peeling step P4 are performed in the same manner as in the first embodiment, and a configuration as shown in FIG. 9A is obtained. Next, in a semiconductor layer removing step Q1, in order to remove a portion of the single crystal silicon film 5 excluding the region of the diaphragm 6, the single crystal silicon film 5 is patterned into a shape as shown in FIG. The oxide film 3 formed under the film 5 is removed by performing an etching process using the oxide film 3 as an etching stopper. Subsequently, the exposed oxide film 3 is similarly removed by etching. Thereby, the surface 15 of the single crystal silicon substrate 2 is partially exposed (see FIG. 9B).

Next, in the element forming step P5, a low antibody 10 is formed on the diaphragm 6 in the same manner as described above, and the surface 15 of the single-crystal silicon substrate 2 exposed in the above-described step is formed on the surface 15 of the single crystal silicon substrate 2 for a signal processing circuit. Of the MOS circuit element 11 and the bipolar circuit element 13 (see FIG. 3C).

Thereafter, a pressure reduction sealing step P6 is performed in the same manner as in the first embodiment to form an opening 8a in the single crystal silicon film 5 at the end of the pressure reduction communication hole 8 (FIG. )), The inside of the pressure reference chamber 7 is reduced to a vacuum state by the CVD method, and the protective film 9 is formed on the entire surface to form the opening 8a.
Is sealed. Thereafter, the sensor chip 14 is obtained by removing the protective film 9 from the diaphragm 6.

According to the third embodiment, by performing the semiconductor layer removing step Q 1, the single crystal silicon film 5 around the diaphragm 6 is removed and the surface 15 of the single crystal silicon substrate 2 is exposed. In this state, the signal processing circuits such as the MOS circuit element 11 and the bipolar circuit element 13 are formed in this portion. Therefore, the circuit for the signal processing circuit is not restricted by the thickness of the single crystal silicon film 5. Elements 11 and 13 can be formed.
In addition, since the circuit elements 11 and 13 are formed directly on the single crystal silicon substrate 2 as described above, the effect of dissipating heat generated in the circuit is improved.

In the third embodiment described above, the sensor chip 1 has a structure in which the oxide film 3 is not interposed.
4 can be formed. In this case, in the semiconductor layer removing step Q1, the single crystal silicon film 5 is removed.
Since there is no oxide film 3 serving as an etching stopper when etching is performed, the thickness of the single-crystal silicon film 5 is removed by the etching process, and then a portion near the junction where a defect is generated is etched. It is preferable to form the circuit elements 11 and 13 in a state where the circuit elements 11 and 13 have been removed.

In the above embodiment, the MOS circuit element 11 is formed in the single crystal silicon film 5 (the area having the SOI structure), and the single crystal silicon film 5 and the oxide film in the area where the bipolar circuit element 13 is formed. The bipolar circuit element 13 may be formed on the surface 15 of the single crystal silicon substrate 2 which is the second substrate exposed by removing only 3.

(Fourth Embodiment) FIGS. 11 to 13
Shows a fourth embodiment of the present invention, which is different from the first embodiment in that a method for forming a recess for the pressure reference chamber 7 and a groove for the pressure reduction communication hole 8 constituting the sensor chip 16 is described. It is. That is, as shown in FIG.
The sensor chip 16 has a concave portion 17a and a groove portion 17b formed by providing a silicon oxide film 17 having a predetermined thickness on the upper surface of a single crystal silicon substrate 2 as a second substrate and removing a part of the silicon oxide film 17 by etching. ing. A single-crystal silicon film 5 is formed on the upper surface in the same manner as described above, a diaphragm 6 is provided, and a pressure reference chamber 7 is provided.

Next, a method of manufacturing the sensor chip 16 (FIG. 1)
1) will be described. The ion implantation layer forming step P1 is performed in the same manner as in the first embodiment. An oxide film forming step R1 is performed on the single crystal silicon substrate 2 as the second substrate prior to the concave part forming step P2. An oxide film 17 having a predetermined thickness is formed on the surface of single crystal silicon substrate 2 by a method such as thermal oxidation or CVD. In this case, the maximum thickness of the oxide film 17 is about 2 μm by the thermal oxidation method.
Since the maximum thickness is about 5 μm in the CVD method, it is appropriately selected and formed as needed.

Next, in the recess forming step P2, unlike the first embodiment, openings 17a and 17b serving as recesses and grooves are formed in the oxide film 17 by etching (FIGS. 12A and 12A). b)). Hereinafter, in the same manner as described above, the bonding step P3 (see FIG. 13A), the peeling step P4 (see FIG. 13B), the element forming step P5 (see FIG. 13C), and the reduced pressure sealing step P6. ((D),
(Refer to (e)).

Thus, a single crystal silicon film 5 as a semiconductor layer is formed, and the diaphragm 6 and the pressure reference chamber 7 are formed.
After forming the resistor 10 and the circuit element 11, an opening 8 a is formed, and the pressure is reduced from the opening 8 a via the pressure reducing communication hole 8 by the CVD method so that the inside of the pressure reference chamber 8 is in a vacuum state. Then, sealing is performed by forming a protective film 9. By removing the protective film 9 on the diaphragm 6, a sensor chip 16 is formed.

According to the fourth embodiment, the recess forming step P2 for forming the recess 17a for the pressure reference chamber 7 and the groove 17b for the pressure-reducing communicating hole 8 includes the oxide film 1
7 is formed and a window portion is formed therein, so that when the depth dimension of the concave portion 17a meets the conditions, the sensor chip 16 can be formed through a simple processing step. become able to.

(Fifth Embodiment) FIGS. 14 and 15
Shows a fifth embodiment of the present invention, and differs from the fourth embodiment in that a semiconductor layer removing step Q1 is performed after a peeling step P4. That is, in the sensor chip 18 according to the present embodiment, as described in the third embodiment, the bipolar circuit element 13
Is provided.

Next, a method of manufacturing the sensor chip 18 (FIG. 1)
4) will be described. That is, by performing the peeling step P4 in the same manner as described above, the single crystal silicon film 5 is formed.
After forming the diaphragm 6 and the pressure reference chamber 7 (see FIG. 15A), a semiconductor layer removing step Q1 is performed to remove the single crystal silicon film 5 around the diaphragm 6 and to form an oxide film. By removing 17, the single crystal silicon substrate 2 is formed in a state where the surface 15 is exposed (see FIG. 2B).

Thereafter, through an element forming step P5, a MOS circuit element 11 and a bipolar circuit element 13 are formed on the surface 15 of the single crystal silicon substrate 2 to provide a signal processing circuit (see FIG. 3C). Subsequently, in a reduced pressure sealing step P6, an opening 8a is formed in the communication hole 8 for reduced pressure (see FIG. 4D), and a protective film 9 is formed by a CVD method to seal the opening 8a. The sensor chip 18 can be obtained by removing the protective film 9 from the diaphragm 6.

According to the fifth embodiment, the circuit element 1 to be formed is simplified while the recess forming step P2 for obtaining the pressure reference chamber 7 is simplified by using the oxide film 17.
A signal processing circuit can be formed on the surface 15 of the single crystal silicon substrate 2 in order to improve the heat radiation effect on the substrates 1 and 13.

(Sixth Embodiment) FIGS. 16 to 20
Shows a sixth embodiment of the present invention, and different portions from the first embodiment will be described below. This embodiment is particularly effective when the film thickness of the diaphragm 6 when formed as the sensor chip 19 is small or when the dose amount of the ion implantation layer 12 is insufficient.
When the single-crystal silicon film 5 is formed by peeling, the single-crystal silicon substrate 4 can be reliably peeled.

The structure of the completed sensor chip 19 is the same as that of the sensor chip 1 described in the first embodiment, and undergoes a different process in an intermediate manufacturing process (see FIG. 16). That is, the single-crystal silicon substrate 4 as the first substrate is subjected to the ion implantation layer 1 under a predetermined condition in the ion implantation layer forming step P1 in the same manner as described above.
2 is formed (see FIG. 17A).

Next, in the recess forming step P2, unlike the above, the recess 2a corresponding to the pressure reference chamber 7 and the communication hole 8 for reducing pressure are formed in the single crystal silicon substrate 2 as the second substrate.
When forming the groove 2b corresponding to the above, a portion where silicon is not etched in the concave portion 2a and the groove 2b is left as the silicon pillar 20. The silicon pillar portion 20 is formed by performing patterning and etching so as to remain on the bottom of the concave portion 2a and the groove portion 2b, for example, in a prismatic shape of about 0.1 to 3 μm (FIG. 17).
(B)).

In this case, as shown in FIG. 20, the grooves 2b are formed on both sides of the concave portion 2a due to the etching process in the later step (in FIGS. 17 and 18, in order to avoid complication). Only one groove 2b is shown), and a large number of silicon pillars 20 are formed in the two grooves 2b and the recesses 2a. Here, the silicon support portion 20 is formed in a prismatic shape, but may be formed in a cylindrical shape or another shape.

Next, in the thermal oxidation step S1, the single-crystal silicon substrate 2 is thermally oxidized to oxidize the silicon of the silicon pillars 20 completely to silicon oxide, thereby forming the silicon oxide pillars 20a. At this time, the oxide film 3 is also formed on the inner bottom and the side wall of the recess 2a and the groove 2b (see FIG. 17C).

Thereafter, a bonding step P3 and a peeling step P
4, a single crystal silicon film 5 on the single crystal silicon substrate 2
To form At this time, the bonding step P3 (FIG. 18)
(See (a)), in the concave portions 2a,
Since the front end position of the silicon oxide support 20a formed in the groove 2b is on the same plane as the substrate surface, the surface of the bonded single crystal silicon substrate 4 is in contact with the silicon oxide support 20a so as to be in close contact therewith. become.

Thus, the two single-crystal silicon substrates 2
When the peeling step P4 is performed in a state where the substrate 4 is adhered, the portion of the single crystal silicon film 5 which becomes the diaphragm 6 is in close contact with the concave portion 2a and the silicon oxide support portion 20a formed in the groove portion 2b on the single crystal silicon substrate 2 side. Because it is a state
When peeling occurs in the ion-implanted layer 12 of the single-crystal silicon substrate 4, this part cannot be completely peeled and is broken around, and incomplete peeling occurs in a state of being attached to the single-crystal silicon substrate 4 side as the first substrate. The problem that occurs can be avoided. This contributes as a major factor particularly when the thickness of the single-crystal silicon film 5 to be peeled is small, so that the structure is effective for reliably performing the peeling step P4.

Now, in the state where the single crystal silicon film 5 is formed by performing the peeling step P4 as described above, the silicon oxide support 20a remains in the pressure reference chamber 7 and the pressure reducing communication hole 8. (See FIG. 3B). Then, in this state, the next element forming step P5
To form the low antibody 10 on the diaphragm 6 portion of the single crystal silicon film 5 and the MOS circuit element 11 for the signal processing circuit in the outer peripheral region of the diaphragm 6 (see FIG. 3C).

Next, in the pillar etching step S2, the single-crystal silicon film 5 located at the ends of the two pressure reduction communication holes 8 is formed.
Is removed by etching to form an opening 8a (see FIG. 19A, only one opening 8a is shown in the figure), and a hydrogen fluoride solution is internally formed through the two openings 8a. The silicon oxide support 20a and the oxide film 3 are selectively etched and removed by flowing a silicon oxide etchant such as that shown in FIG. in this case,
Since the openings 8a are formed in two places, the etching liquid easily flows inside.

Then, in the reduced pressure sealing step P6, the inside of the pressure reference chamber 7 is evacuated using the CVD apparatus in the same manner as described above to form the protective film 9, thereby forming the two openings 8a.
Is covered with a protective film 9 and sealed. Then, the sensor chip 19 is formed by removing the protective film 9 from the diaphragm 6.

According to the sixth embodiment, since the silicon oxide support 20a is formed in the recess 2a and the groove 2b prior to the bonding step P3, the bonding of the diaphragm 6 in the bonding step P3 is performed. The state can be improved, and the single-crystal silicon film 5 can be surely prevented by avoiding a problem such as partial peeling in the peeling step P4.
Can be peeled off.

Then, the silicon oxide pillar 20a is formed as the silicon pillar 20 when the single crystal silicon substrate 2 is etched simultaneously with the formation of the recess 2a and the groove 2b, and this is thermally oxidized in the thermal oxidation step S1. Since it is formed, the number of steps does not increase significantly. Further, prior to the reduced pressure sealing step P6, the silicon oxide support 20a is
Since the etching is selectively removed by the support pillar etching step S2, the completed sensor chip 19 is not affected at all.

(Seventh Embodiment) FIGS. 21 and 22
Shows a seventh embodiment of the present invention. The difference from the sixth embodiment is that the semiconductor layer removing step Q1 described in the third embodiment is performed prior to the element forming step P5. The circuit element 1 of the signal processing circuit is provided on the surface 15 of the single crystal silicon substrate 2 as the second substrate.
1 and 13 have been formed (the manufacturing process is shown in FIG.
reference).

After performing the ion-implanted layer forming step P1, the recess forming step P2, the thermal oxidation step S1, the bonding step P3, and the peeling step P4 (see FIG. 22A) in the same manner as in the sixth embodiment, The semiconductor layer removing step Q1 is performed to etch and remove the single crystal silicon film 5 and the oxide film 3 around the diaphragm 6, thereby exposing the surface 15 of the single crystal silicon substrate 2, which is the second substrate. Fig. (B).

Next, in the element forming step P5, the resistor 10 is formed on the surface of the diaphragm 6 and the MOS circuit element 11 serving as a circuit element for a signal processing circuit is formed on the exposed surface 15 of the single crystal silicon substrate 2. Then, a bipolar circuit element 13 is formed (see FIG. 3C).

Thereafter, in the same manner as described above, in the column etching step S2, after the opening 8a is formed in the pressure-reducing communication hole 8 (see FIG. 4D), the opening 8a is formed in the recess 2a and the groove 2b. The silicon oxide support 20a is selectively removed by etching (see FIG. 3E), and then the pressure inside the pressure reference chamber 7 is reduced to a vacuum in a reduced pressure sealing step P6. The opening 8a is formed by forming the protective film 9 by
And the protective film 9 in the diaphragm 6 is removed by etching, whereby the sensor chip 21 can be obtained (see FIG. 6F).

According to the seventh embodiment, the sixth embodiment
The same effect as that of the embodiment can be obtained, and when the bipolar circuit element 13 is formed, it can be formed without being restricted by the film thickness of the diaphragm 6, and furthermore, the heat generation of the signal processing circuit can be reduced. The effect of radiating heat to the back side of the single crystal silicon substrate 2 as the second substrate can be enhanced.

(Eighth Embodiment) FIGS. 23 to 26
Shows an eighth embodiment of the present invention. The difference from the sixth embodiment is that an oxide film 3 on the surface of a single crystal silicon substrate 2 which is a second substrate is formed as a structure of a sensor chip 22. In order to avoid such a configuration, a nitride film forming step T1 (see FIG. 23) is provided prior to the concave part forming step P2 in the manufacturing process.

That is, after performing the ion-implanted layer forming step P1 in the same manner as described above (see FIG. 24A), the single-crystal silicon substrate 2 serving as the second substrate is subjected to the nitride film forming step T1. A silicon nitride film 23 is formed on the mirror-polished surface. Thereafter, in the recess forming step P2, a part thereof is patterned by photolithography to form the recess 2a for the pressure reference chamber 7 and the groove 2b of the pressure reducing communication hole 8 in the same manner as described in the second embodiment. Are removed by etching so as to form a concave portion 2c (see FIG. 7) having an integral shape (see FIG. 24B).

At this time, a large number of silicon pillars 20 are formed in the recess 2c, as in the sixth embodiment. Then, by performing the thermal oxidation step S1, the silicon support 20 is completely made of silicon oxide to form the silicon oxide support 20a, and the oxide film 3 is also formed on the bottom and side surfaces of the concave portion 2c (FIG. c)). In the thermal oxidation step S1, an oxide film is not formed on the portion of the single crystal silicon substrate 2 where the silicon nitride film 23 is formed as a mask.

Thereafter, the state in which the silicon nitride film 23 has been removed by etching is set in the next bonding step P3.
(See FIG. 26A). Hereinafter, the peeling step P4
(See FIG. 2B) and an element forming step P5 are performed to form the resistor 10 and the MOS circuit element 11 on the single crystal silicon film 5 (see FIG. 2C). Subsequently, the sensor chip 22 can be obtained through the pillar etching step S2 (see FIG. 26A) and the reduced pressure sealing step P6 (see FIGS. 26B and 28C).

In this case, the structure of the sensor chip 22 is such that the oxide film 3 is not provided on the surface of the single crystal silicon substrate 2, so that in the pillar etching step S2, the oxide film 3 as in the sixth embodiment is used. It is not necessary to consider the problem caused by over-etching, and therefore, control can be performed so that the silicon oxide support portion 20a is surely removed by etching.

According to the eighth embodiment, the sixth embodiment
The same effect as that of the embodiment can be obtained, and the controllability of the etching process in the pillar etching step S2 can be improved.

In the above case, the recess forming step P2 is performed in a state where an oxide film is first formed on the surface of the single crystal silicon substrate 2 as the second substrate, and the silicon nitride film 23 is provided thereon. Alternatively, the concave portion forming step P2 may be performed using a photoresist provided on the silicon nitride film 23 as a mask material.

(Ninth Embodiment) FIGS. 27 and 28
Shows a ninth embodiment of the present invention. What is different from the first embodiment is that the surface on the side where the ion implantation layer 12 is formed is formed with respect to the single crystal silicon substrate 4 which is the first substrate. Film forming step U1 (FIG. 2) for amorphizing the surface layer portion of FIG.
7).

That is, after the ion implantation layer 12 is formed on the single crystal silicon substrate 4, in the amorphous film forming step U1,
For example, a rare gas ion such as a silicon ion or an argon ion is implanted into the surface layer portion by an ion implantation method, thereby forming an amorphous silicon layer 24 as an amorphous film in a region shallower than the ion implantation layer 12 (FIG. 2
8). Thereby, the mechanical strength of the portion of the single crystal silicon substrate 4 to be separated can be increased, and the occurrence of partial cracks, tears, and the like can be prevented when the single crystal silicon substrate 4 is separated in the separation step P4. become.

Further, the formed amorphous layer 24
Through the high-temperature heat treatment step in the separation step P4, single-crystal silicon remaining in the separated part can be rearranged as a seed to be single-crystallized, thereby obtaining the single-crystal silicon film 5. .

According to the ninth embodiment, in order to prevent the single crystal silicon film 5 from being cracked or broken in the peeling step P4, the amorphous film forming step U1 is performed to reduce the mechanical strength. Since improvement is achieved, the occurrence of cracks is reduced as much as possible, and the single crystal silicon film 5 can be surely peeled off. The above-described amorphous film forming step U1 may be performed before the ion-implanted layer forming step P1.

(Tenth Embodiment) FIG. 29 shows a tenth embodiment of the present invention. The difference from the ninth embodiment is that a single crystal silicon substrate 4 as a first substrate is used. And an amorphous silicon film 25 as an amorphous film.
Is formed by depositing.

That is, as shown in FIG. 29, before or after the ion implantation layer forming step P1, the amorphous silicon film 25 is formed by the CVD method or the PVD (physical deposition method). Thus, the same function and effect as in the ninth embodiment can be obtained. In this case, the same effect can be obtained by forming a polycrystalline silicon film, a silicon oxide film, or a silicon nitride film instead of the amorphous silicon film 25. Further, the amorphous silicon film 25 can be monocrystallized in the peeling step P4 as described above.

(Eleventh Embodiment) FIGS. 30 and 31
Shows an eleventh embodiment of the present invention. The difference from the first embodiment is that, as the structure of the sensor chip 26, the communication hole 8 for pressure reduction is formed in the single crystal silicon substrate 2 as the second substrate. It is just formed as an opening 27 leading to the back side.

That is, in this embodiment, the manufacturing process is the same as that of the first embodiment (see FIG. 1), and the ion-implanted layer forming process P1 (FIG.
(See (a)), the recess forming step P2 is performed, and the process proceeds to the bonding step P3 (see FIG. (B)). At this time, in the recess forming step P2, an opening 27 is formed by etching so that the bottom surface of the recess 2a of the single crystal silicon substrate 2 communicates with the back surface separately from the recess 2a for the pressure reference chamber 7.

Hereinafter, a peeling step P4 (see FIG. 14C),
An element forming step P5 (see FIG. 31A) and a reduced pressure sealing step P6 (see FIGS. 31B and 31C) are performed to form the sensor chip 26. In this case, in the decompression sealing step P6, the inside of the pressure reference chamber 7 is depressurized through the opening 27 to be in a vacuum state, and then sealed by the sealing member 28. Separately, the protective film 9 is formed on the surface of the sensor chip 26 except for the diaphragm 6.

According to the eleventh embodiment, the same operation and effect as described above can be obtained. In the above-described case, as one of the usage modes of the sensor chip 26, for example, when the pressure reference chamber 7 is opened to the atmosphere and the detection operation is performed based on the pressure difference applied to the diaphragm 6, the sealing member 28 is used. It is also possible to use as a configuration without providing.

(Twelfth Embodiment) FIGS. 32 to 35
Shows a twelfth embodiment of the present invention, and the points different from the first embodiment will be described below. In this embodiment, as shown in FIG. 35 (h), a semiconductor substrate 29 for a pressure sensor is formed by forming a silicon oxide film 31 as an insulating film on a surface of a single crystal silicon substrate 30 serving as a support substrate.
Is formed, which includes a silicon oxide film 3 in a predetermined region.
A pressure reference chamber 33 is formed by the recess 1 formed to a predetermined depth of the silicon single crystal substrate 1 and the silicon single crystal substrate 30.

Then, a single-crystal silicon thin film 34 as a semiconductor layer is formed on the surface of the single-crystal silicon substrate 30 so as to close the pressure reference chamber 33, and a diaphragm 35 is formed.
Is provided. The pressure inside the pressure reference chamber 33 is reduced,
The pressure is set close to the vacuum state. Therefore, the structure is basically the same as the structure of the sensor chip 1 which is the semiconductor substrate for a pressure sensor shown in the first embodiment.
In the drawing, the single-crystal silicon thin film 34 is shown without a resistor or a sensor circuit for measuring pressure.

Next, with reference to the outline of the manufacturing process shown in FIGS. 32 and 33, the manufacturing process of the pressure sensor semiconductor substrate 29 will be schematically described. (1) Ion Implantation Layer Forming Step V1 First, the process of forming the insulating film separation substrate 36 as the first substrate will be described with reference to the step shown in FIG. 32 and the schematic sectional view of FIG. The insulating film separation plate 36 is used to enable the thickness dimension of the diaphragm 35 to be set with high accuracy when the single crystal silicon thin film 34 formed of the first substrate is used as the diaphragm 35 ( FIG.

First, a single-crystal silicon substrate 37 as a third substrate is prepared, and a high-concentration ion-implanted layer 38 in which hydrogen ions (protons) have been implanted at a predetermined depth from the surface is formed thereon. (See FIG. 34A). In this case, the depth at which the ion implantation layer 38 is formed is determined by the implantation acceleration voltage.
In order to determine the thickness dimension of No. 5, it is necessary to previously set the thickness to a desired value.

Specifically, a 2.0 μm diaphragm 3
In order to obtain 5, 220 keV is required, and 1.0 keV is required.
In order to obtain the μm diaphragm 35, 120 keV
Hydrogen ions are implanted at a moderate acceleration voltage. Further, the ion implantation dose is 1 × 10 ¹⁶ atoms / cm ² or more, and preferably 5 × 10 ¹⁶ atoms / cm ² or more. In addition, the surface of the single crystal silicon substrate 37 to be ion-implanted is previously oxidized by thermal oxidation or a film forming method.
By this, it is possible to alleviate damage to the surface layer due to ion implantation and prevent impurity contamination.

(2) Laminating Step V2 Next, both are laminated using a single-crystal silicon substrate 37 as a third substrate and a single-crystal silicon substrate 40 as a fourth substrate separately prepared. (See FIG. 34B). In the substrate cleaning step performed prior to the bonding step, the single-crystal silicon substrate 37 on which the ion-implanted layer 38 is formed is covered with an oxide film 39 for preventing contamination formed on the surface.
Is completely removed by using an etching solution such as a hydrofluoric acid aqueous solution, whereby the surface can be contaminated and flattened, and then H ₂ SO ₄ (sulfuric acid) and H ₂ O ₂ (hydrogen peroxide solution) By washing the solution with a 4: 1 mixture,
A natural oxide film is formed on the surface, and a hydrophilic treatment is performed.

Single-crystal silicon substrate 40 as fourth substrate
As for the method, a silicon oxide film 41 functioning as a buried oxide film (insulating film) of the insulating film separation substrate 36 is formed in advance, and then washed with a mixed solution of H ₂ SO ₄ and H ₂ O ₂ at a ratio of 4: 1. As a result, a natural oxide film is formed on the surface, and a hydrophilic treatment is performed. Thereafter, the two substrates are brought into close contact with each other to perform bonding. As for the substrate cleaning, the single-crystal silicon substrate 37 is cleaned only with a solution in which H ₂ SO ₄ and H ₂ O ₂ are mixed at a ratio of 4: 1 without removing the oxide film 39 for preventing contamination. By removing contaminants on the surface, planarization can be performed, and bonding with the single crystal silicon substrate 40 can also be performed.

Further, by washing with a solution in which H ₂ SO ₄ and H ₂ O ₂ are mixed in a ratio of 4: 1, a natural oxide film is formed on the surface and the substrate is replaced with the above-described method of performing the hydrophilic treatment. It is also effective to carry out a hydrophobizing treatment such as a hydrofluoric acid aqueous solution for the cleaning treatment. Although the bonding strength is slightly reduced by performing the hydrophobizing treatment, when a certain level of bonding strength is obtained, residual moisture on the bonding surface can be reduced as much as possible. This is because when the bonding is performed in a vacuum atmosphere, when the pressure reference chamber 33 is formed at the same time, the occurrence of unbonded regions (voids) and the residual moisture in the pressure reference chamber 33 are particularly prevented. Can be bonded.

(3) Peeling Step V3 Next, a heat treatment is performed in a state where the two substrates are bonded to each other, thereby strengthening the bonding strength of the bonding surface and increasing the pressure of the injected hydrogen in the ion implantation layer 38. (See FIG. 34C). The heat treatment temperature at this time needs to be about 400 ° C. to 600 ° C., and the heat treatment apparatus may be an electric furnace or a short heat treatment by lamp heating. Note that peeling can be performed in any of a heat treatment atmosphere and an atmospheric pressure (for example, a nitrogen atmosphere) or a vacuum.

At the portion where the hydrogen ion implanted layer 38 is formed, the single crystal silicon thin film 34 serving as a semiconductor layer is peeled off and adhered to a single crystal silicon substrate 40 as a fourth substrate via an oxide film 41. It is brought into a state of being joined, whereby the structure of the insulating film separation substrate can be obtained. Since sufficient bonding strength cannot be obtained by the above-described heat treatment at about 400 ° C. to 600 ° C., the heat treatment is actually performed at a temperature of 1000 ° C. or higher, preferably 1100 ° C. or higher after peeling.

The surface roughness of the peeled surface was 5 to 1 in Ra value.
0 nm, and a single-crystal silicon substrate (second
In order to achieve the bonding with the substrate 30, the surface roughness Ra needs to be equal to or less than 0.5 nm, and the mechanical polishing method CMP (Chemical Mechanical Polishing) is used.
It is necessary to achieve smoothing of the surface by heat treatment, or to smooth the oxide film only by etching after thermally oxidizing the peeled surface. As a result, the insulating film separation substrate 36 can be formed as a first substrate.

(4) Concave Forming Step P2 In this step, the same step as that described in the first embodiment is performed, and the concave 32 is formed in the single crystal silicon substrate 30 as the second substrate by etching. (Fig. 3
5 (d) right side). However, in this case, in the description of this embodiment, unlike the case of the first embodiment, the step of forming the pressure reference chamber 33 without providing the pressure-reducing communication portion 2b is adopted, so that the subsequent steps are slightly There are changes. However, also in this embodiment, similarly to the first embodiment, it is possible to adopt a step of providing the pressure-reducing communication portion 2b.

(5) Ion Implanted Layer Forming Step V4 In this step, a stripped ion implanted layer 42 is formed inside the oxide film 41 formed on the insulating film separation substrate 36 or at a position deeper than the oxide film 41. (See (d) on the left side of the figure). In this case, the ion implantation layer 42 is formed as a high-concentration hydrogen ion implantation layer by implanting, for example, hydrogen ions (protons). Since the depth at which the ion implantation layer 42 is formed is determined by the implantation acceleration voltage, the oxide film 4
It is set so that the implantation peak is located within the substrate 1 or inside the substrate at a position deeper than that. At this time, the ion implantation amount is 1 × 10 ¹⁶ atoms / cm ² or more, preferably 5 × 10 ¹⁶ atoms / cm ^2.
1 is required ⁶ atoms / cm ² or more.

(6) Bonding Step P3 Here, the insulating separation film substrate 36 is bonded to the single crystal silicon substrate 30 having the concave portions 34 formed thereon (FIG. 35E).
reference). In a substrate cleaning step performed prior to the bonding step, a natural oxide film is formed on the surface by cleaning with a mixed solution of H ₂ SO ₄ and H ₂ O ₂ at a ratio of 4: 1.
Perform hydrophilic treatment. With respect to the single crystal silicon substrate 30, an oxide film 31 is formed on the surface in advance, a natural oxide film is formed on the surface, and a hydrophilic treatment is performed. After this, 2
Bonding is performed by bringing two substrates into close contact.

At this time, the atmosphere for the bonding may be atmospheric pressure or vacuum. At this time, by performing the bonding in a vacuum, it is possible to prevent the air remaining in the bonding surface and to prevent the unbonded region (void)
In addition, since the inside of the concave portion 34 for the pressure reference chamber 33 can be dehydrated, the decompression sealing step performed after forming the element can be omitted. As a result, the diaphragm 35
After the formation, the occurrence of breakage of the diaphragm 35 due to the expansion of water can be prevented.

(7) Support Substrate Thinning Step V5 In order to thin the insulating film separation substrate 36, peeling at the ion-implanted layer 42 is performed. 2 to cause delamination
In a state where the two substrates are bonded to each other, heat treatment is performed to cause a rise in the pressure of the implanted hydrogen in the ion-implanted layer 42, thereby causing separation (see FIG. 35F). In addition, the joint strength of the joint surface is simultaneously enhanced by this heat treatment. The heat treatment temperature and other conditions are almost the same as those in the peeling step V3 described above.
As a result, a single-crystal silicon thin film 34 as a semiconductor layer can be formed on the single-crystal silicon substrate 30 with the buried oxide film 34 interposed therebetween.

In this state after the separation, oxide film 41 and a part of single crystal silicon substrate 40 remain on single crystal silicon thin film 34. The part to be finally used for element formation is the part of the single-crystal silicon thin film 34, which is formed irrespective of the peeled surface. There is no need to perform the conversion process.

On the other hand, the peeled single-crystal silicon substrate 40 is separated only by the peeling of the surface layer, and is largely peeled off as it is in the substrate state. If it can be reused for the same purpose or another purpose, cost can be reduced.

(8) Buried oxide film removing step V6 Next, the thin film of the single-crystal silicon substrate 40 and the oxide film 41 remaining on the peeled surface are removed to provide the semiconductor layer 34 with high uniformity in film thickness. It is formed in a state where First, regarding the removal of the thin film of the single crystal silicon substrate 40, the oxide film 4 is removed.
1 is used as a stopper to remove by performing a TMAH treatment or a treatment with an alkaline solution such as KOH, or an etching treatment with a mixed solution of nitric acid and hydrofluoric acid (FIG. 3G)
reference). The removal of the thin film of the single crystal silicon substrate 40 can be similarly performed by a mechanical and chemical polishing method using the oxide film 41 as a stopper.

Thereafter, the exposed oxide film 41 is removed by etching with a hydrofluoric acid aqueous solution or the like (FIG. 11H).
reference). As a result, the single-crystal silicon thin film 34 as a semiconductor layer can be formed while being left on the surface. After the peeling step, the single-crystal silicon thin film 34 can be formed to have a predetermined thickness without directly acting from the outside, and can be obtained as a film having improved film thickness accuracy. . As a result, the diaphragm 35 and the pressure reference chamber 33 are formed.

(9) Element Forming Step P5 In the above-described state, the single-crystal silicon thin film 34 is formed on the single-crystal silicon substrate 30 as the second substrate by the insulating film 4.
1, the substrate structure is an SOI (Silicon On Insulator) structure.
On the single crystal silicon thin film 34, a resistor having a piezoresistive effect for pressure detection is formed, and various elements such as MOS transistors forming a circuit for signal processing are formed. The resistor is wired so that a bridge circuit is formed by the wiring pattern, and the input and output terminals are wired so as to be connected to the signal processing circuit.

(10) Reduced pressure sealing step P6 Next, in the bonding step P3, when manufacturing a type in which bonding is not performed in a vacuum atmosphere,
Since it is necessary to reduce the pressure in the pressure reference chamber 33 to a vacuum or a predetermined pressure, a reduced pressure sealing step P6 described below is performed. That is, an opening is formed in the single-crystal silicon thin film 34 at the end of the pressure-reducing communication hole formed by the groove and the single-crystal silicon film 34 opposite to the pressure reference chamber 33. In this case, the opening is formed by etching or the like from the surface side of the single-crystal silicon thin film 34.

Thereafter, an insulating protective film is formed on the surface of the single-crystal silicon thin film 34 formed as described above using a CVD apparatus or the like, and the openings are simultaneously sealed under reduced pressure. For example, the pressure in the pressure reference chamber 33 is reduced through a pressure reducing communication hole by exposing the pressure reference chamber 33 to a vacuum atmosphere while being placed in a CVD apparatus. In a state where the inside is in a vacuum, an insulating protective film such as a silicon nitride film or a silicon oxide film is formed by depositing on the entire surface, thereby simultaneously sealing the inside of the opening. Thereafter, the protective film on the diaphragm 35 is removed by photolithography to form a sensor chip.

According to the twelfth embodiment, in addition to the effect of the first embodiment, in the support substrate thinning step V5 using the insulating film separation substrate 36 as the first substrate, the semiconductor layer is Oxide film 4 on single crystal silicon thin film 34
Since the peeling is performed in a state where 1 is left, and the oxide film 41 is removed in a later step, the thickness and the like of the single-crystal silicon thin film 34 can be accurately formed.

In the oxide film separation substrate 36, a portion to be the semiconductor layer 34 is formed by forming an ion implantation layer 38 therein and peeling it in a peeling step V3. The used substrate can be reused, and the cost can be reduced.

Further, in this embodiment, the pressure reference chamber 3
3 is bonded in the bonding step P3 in a vacuum to simultaneously seal the inside in a vacuum state, so that a manufacturing method that does not employ the reduced-pressure sealing step P6 in the subsequent step can also be used. In addition, the process can be simplified.

In this embodiment, in the bonding steps V2 and P3, a hydrophobizing treatment can be performed instead of the hydrophilicizing treatment. Thus, it is possible to prevent the diaphragm 35 from being damaged after the bonding.

In the above embodiment, the recess 32
Single crystal silicon substrate 30 as a second substrate for forming
By adopting an insulating film separation substrate in advance,
The diaphragm 35 and the pressure reference chamber 33 can be formed on the insulating film separation substrate. As a result, when the pressure sensor control circuit is formed around the pressure reference chamber, it can be formed in the insulating film isolation region, which facilitates the formation of the element isolation structure and improves the electrical characteristics such as withstand voltage. You can plan.

(Thirteenth Embodiment) FIG. 36 shows a thirteenth embodiment of the present invention. The difference from the twelfth embodiment is that the thirteenth embodiment differs from the twelfth embodiment in forming the semiconductor substrate 43 for a pressure sensor. The second substrate uses an insulating separation substrate 44.

That is, FIG. 17A is a schematic sectional view of a semiconductor substrate 43 for a pressure sensor. A silicon oxide film or the like is formed on a single crystal silicon substrate 40 instead of the second substrate 30. A single crystal silicon thin film 46 as a semiconductor layer is provided with the insulating film 45 interposed therebetween. In other words, by adopting the configuration employing the insulating film separation substrate 44, the single crystal silicon thin film 46 in which the pressure reference chamber 33 and the circuit formation area around the pressure reference chamber 33 are provided in a state where the single crystal silicon substrate 40 is separated from the single crystal silicon substrate It is formed in the part.

Thus, when the pressure sensor control circuit is formed around the pressure reference chamber, it can be formed in the insulating film isolation region, thereby facilitating the formation of the element isolation structure and the electrical characteristics such as the withstand voltage. Can be improved. Here, the semiconductor substrate 43 for a pressure sensor having the configuration shown in FIG. 3A shows a state in which the bottom portion of the pressure reference chamber 33 is formed in the single-crystal silicon thin film 46, and the element formation region is The thickness of the single crystal silicon thin film 46 necessary for forming
Is a shallow depth dimension.

On the other hand, the pressure sensor semiconductor substrate 47 shown in FIG. 17B has the same basic structure as the pressure sensor semiconductor substrate 43, and the depth dimension of the pressure reference chamber 33 is a single crystal silicon thin film. The thickness of the pressure reference chamber 33 is set to be the same as the thickness of the insulating film 45 and the bottom of the pressure reference chamber 33 is set to be the same as that of the insulating film 45. Note that the pressure sensor semiconductor substrates 43 and 47 may be ones that conform to the conditions for forming pressure sensors and circuit elements formed as needed.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. Instead of the insulating protective film 9, polycrystalline silicon may be formed as a material for sealing the opening 8a. The inside of the pressure reference chamber 7 may be formed in a state where the pressure is reduced to a predetermined pressure level in addition to the case where the pressure is set in a vacuum state. The film thickness of the diaphragm 6, the size of the pressure reference chamber 7, or the size of the communication hole 8 for pressure reduction can also be set to appropriate dimensions according to the pressure range to be measured.

[Brief description of the drawings]

FIG. 1 is a schematic process explanatory view showing a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a first substrate after an ion implantation layer forming step.

FIG. 3 is a schematic cross-sectional view and a top view of a second substrate after a concave portion forming step.

FIG. 4 is a schematic cross-sectional view in each step after a bonding step.

FIG. 5 is a diagram showing a relationship between a direction of a substrate shown in a bonded state and a shape of an opening of a concave portion.

FIG. 6 is a diagram showing a silicon substrate having a plane orientation of (100), its cleavage direction, and a recommended bonding direction.

FIG. 7 is a view corresponding to FIG. 3, showing a second embodiment of the present invention;

FIG. 8 is a diagram corresponding to FIG. 1, showing a third embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view in each step after the peeling step.

FIG. 10 is a schematic cross-sectional view and a top view after a semiconductor layer removing step.

FIG. 11 is a view corresponding to FIG. 1, showing a fourth embodiment of the present invention;

FIG. 12 is a diagram corresponding to FIG. 3;

FIG. 13 is a diagram corresponding to FIG. 4;

FIG. 14 is a view corresponding to FIG. 1, showing a fifth embodiment of the present invention;

FIG. 15 is a diagram corresponding to FIG. 7;

FIG. 16 is a view corresponding to FIG. 1, showing a sixth embodiment of the present invention;

FIG. 17 is a schematic cross-sectional view in each step (part 1).

FIG. 18 is a schematic sectional view of each step (part 2).

FIG. 19 is a schematic cross-sectional view in each step (part 3).

FIG. 20 is a top view showing the arrangement of pillars formed in a concave portion;

FIG. 21 is a view corresponding to FIG. 1, showing a seventh embodiment of the present invention;

FIG. 22 is a diagram corresponding to FIG. 7;

FIG. 23 is a view corresponding to FIG. 1, showing an eighth embodiment of the present invention;

FIG. 24 is a schematic cross-sectional view in each step (part 1).

FIG. 25 is a schematic sectional view of each step (part 2).

FIG. 26 is a schematic sectional view in each step (part 3).

FIG. 27 is a view corresponding to FIG. 1, showing a ninth embodiment of the present invention;

FIG. 28 is a schematic cross-sectional view illustrating an amorphous film forming step U1.

FIG. 29 is a view corresponding to FIG. 26, showing a tenth embodiment of the present invention;

FIG. 30 is a schematic cross-sectional view in each step showing the eleventh embodiment of the present invention (part 1).

FIG. 31 is a schematic sectional view of each step (part 2).

FIG. 32 is a view (part 1) corresponding to FIG. 1 showing a twelfth embodiment of the present invention;

FIG. 33 is a diagram corresponding to FIG. 1 (part 2);

FIG. 34 is a schematic sectional view of each step (part 1).

FIG. 35 is a schematic cross-sectional view of each step (part 2).

FIG. 36 is a schematic sectional view showing a thirteenth embodiment of the present invention.

[Explanation of symbols]

1, 14, 16, 18, 19, 21, 22, 26 are sensor chips (semiconductor substrates for pressure sensors), 2 is a single-crystal silicon substrate (second substrate), 2a is a recess for a pressure reference chamber, 2
b is a groove for a communication hole for pressure reduction, 2c is a recess, 3 is an oxide film, 4
Is a single crystal silicon substrate (first substrate), 5 is a single crystal silicon film (semiconductor layer), 6 is a diaphragm, 7 is a pressure reference chamber, 8 is a communication hole for pressure reduction, 8a is an opening, and 9 is an insulating protective film. Reference numeral 10, a resistor, 11 a MOS circuit element, 12 an ion implantation layer, 13 a bipolar circuit element, 15 a surface of the second substrate, 17 an oxide film, 20 a silicon support, 20
a is a silicon oxide support, 23 is a silicon nitride film (nitride film), 24 is an amorphous layer (amorphous film), 25 is an amorphous silicon film (amorphous film), 27 is an opening, 29
Is a semiconductor substrate for a pressure sensor, 30 is a second substrate, 31 is a silicon oxide film, 32 is a concave portion, 33 is a pressure reference chamber, 34
Is a single crystal silicon thin film (semiconductor layer), 35 is a diaphragm, 36 is an insulating film separation substrate, 37 is a single crystal silicon substrate (third substrate), 38 is an ion implantation layer, 40 is a single crystal silicon substrate (fourth 42) ion-implanted layer, 4
Reference numerals 3 and 47 are semiconductor substrates for pressure sensors, 44 is an insulating film separation substrate, 45 is an insulating film, and 46 is a single crystal silicon thin film (semiconductor layer).

Claims (34)

[Claims] 1. A semiconductor substrate (1, 14, 16, 16) for use in a pressure sensor which electrically detects a pressure applied to a diaphragm (6) based on a stress generated by a pressure difference from a pressure reference chamber (7). 18, 19, 21, 22, 26)
In the manufacturing method, the ion implantation layer (1) for peeling is formed at a predetermined depth of a first semiconductor substrate (4) for forming the diaphragm (6).
Forming an ion-implanted layer (P1) for forming 2); and forming recesses (2a, 2c) for the pressure reference chamber (7) in the second substrate (2) to form the pressure reference chamber (7). Providing a concave portion forming step (P2), a bonding step (P3) for bonding the first and second substrates (4, 2); and bonding the bonded first substrate (4) to the ion-implanted layer ( A peeling step (P4) of forming the diaphragm (6) and the pressure reference chamber (7) by forming a semiconductor layer (5) on the surface of the second substrate (2) by peeling at a portion 12); A method for manufacturing a semiconductor substrate for a pressure sensor, comprising: 2. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein in the recess forming step (P2), a surface of the second substrate (2) is subjected to an etching treatment to thereby form the recess ( A method for manufacturing a semiconductor substrate for a pressure sensor, comprising forming 2a). 3. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein in the bonding step (P3), an oxide film (3) is formed on a surface of the second substrate (2). In the state provided, the first
A method for manufacturing a semiconductor substrate for a pressure sensor, comprising bonding the substrate to the substrate (4). 4. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein in the recess forming step (P2), a recess (2a) for the pressure reference chamber (7) is provided. A pillar portion (20, 20) having a length equal to its depth dimension and capable of selective etching is provided on the bottom surface.
A method for manufacturing a semiconductor substrate for a pressure sensor, comprising the step of forming a). 5. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 4, wherein in the recess forming step (P2), the recess (2) is formed.
a) A method of manufacturing a semiconductor substrate for a pressure sensor, wherein a column portion (20, 20a) formed on an inner bottom surface is constituted by a plurality of columns. 6. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 4, wherein in the recess forming step (P2), a recess (2a) is formed in the second substrate (2). The pillar portion (20) is formed by providing a pattern for forming the pillar portion (20) at the time of processing, and thereafter, the pillar portion (20) is converted to an oxide (20a) by performing a thermal oxidation step (S1). A) a method of manufacturing a semiconductor substrate for a pressure sensor, wherein a selective etching process is enabled. 7. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 4, wherein the pillar portion (20a) is removed by a selective etching process after the peeling step (P4). A method for manufacturing a semiconductor substrate for a pressure sensor, comprising a step (S2). 8. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein an oxide film (17) is formed on a surface of the second substrate (2) prior to the recess forming step (P2). An oxide film forming step (R1) is provided. In the concave portion forming step (P2), the oxide film (1) is formed.
7) A method of manufacturing a semiconductor substrate for a pressure sensor, wherein the recess (2c) is formed by forming an opening in the opening. 9. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein the semiconductor formed on the surface of the second substrate after the peeling step (P4). By removing the semiconductor layer (5) in a predetermined area of the layer (5) other than the diaphragm (6), an area for element formation is exposed on the surface (15) of the second substrate (2). A method of manufacturing a semiconductor substrate for a pressure sensor, comprising a step (Q1) of removing a semiconductor layer formed in a state. 10. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein in the recess forming step (P2), the recess (2a) for the pressure reference chamber (7) is formed. Forming a pressure-reducing communication portion (2b) communicating with the outside, and after the peeling step (P4), forming the pressure-reducing communication portion (2b).
b) a pressure-reducing sealing step (P6) for reducing the pressure inside the pressure reference chamber (7) through a pressure-reducing communication hole (8) and sealing the pressure reference chamber (7). Substrate manufacturing method. 11. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 10, wherein, in the recess forming step (P2), the pressure-reducing communication portion (2b) is formed on a surface of the second substrate (2). The pressure reducing communication hole (8) is formed by forming a groove portion (2b) along the portion and covering a surface portion with the semiconductor layer (5) formed after the peeling step (P4). Of manufacturing a semiconductor substrate for a pressure sensor. 12. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 10, wherein in the recess forming step (P2), the pressure-reducing communication part (2b) is formed to have a depth equal to the depth of the recess (2a). A method of manufacturing a semiconductor substrate for a pressure sensor, comprising a concave portion (2c) formed to have the same depth dimension as the dimension. 13. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 10, wherein, in the recess forming step (P2), the pressure-reducing communication hole (8) is formed on the back surface of the second substrate (2). A method for manufacturing a semiconductor substrate for a pressure sensor, comprising forming an opening (27) communicating with a portion. 14. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 10, wherein in the pressure reduction sealing step (P6), the pressure reduction communication hole (CVD) is formed in a reduced pressure atmosphere by a CVD method. 8) Opening (8)
A method for manufacturing a semiconductor substrate for a pressure sensor, comprising forming a film (9) so as to seal a). 15. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein the first substrate (4) has an amorphous portion in a portion to be the semiconductor layer (5). Layer or non-single-crystal layer such as polycrystalline layer (2
4. A method of manufacturing a semiconductor substrate for a pressure sensor, the method comprising: forming a semiconductor substrate for a pressure sensor. 16. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 15, wherein the non-single-crystal layers (24, 25) are composed of the same kind of elements as those of the first substrate (4). A method for manufacturing a semiconductor substrate for a pressure sensor, comprising: 17. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 16, wherein the first substrate (4) uses a silicon substrate, and the non-single-crystal layers (24, 25) A method for manufacturing a semiconductor substrate for a pressure sensor, wherein the method is formed as a silicon amorphous film or a polycrystalline film. 18. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 17, wherein the amorphous silicon film is an amorphous silicon film,
A method for manufacturing a semiconductor substrate for a pressure sensor, wherein the method is formed using either a silicon oxide film or a silicon nitride film. 19. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 15, wherein said non-single-crystal layer (24, 25) is deposited on a surface of said first substrate (4). A method for manufacturing a semiconductor substrate for a pressure sensor, wherein the method is provided by using a method. 20. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 15, wherein said non-single-crystal layer (24, 25) is ionized with respect to said first substrate (4). A method for manufacturing a semiconductor substrate for a pressure sensor, characterized by being formed by an injection method. 21. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 16, wherein said non-single-crystal layer (24, 25) is formed on said first substrate (4).
In the case of being composed of the same kind of element as above, the peeling step (P
A semiconductor substrate for a pressure sensor, wherein the non-single-crystal layers (24, 25) are recrystallized by performing a heat treatment after 4) to form the semiconductor layer (5) as a single-crystal layer. Manufacturing method. 22. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein the first substrate has an oxygen concentration of 1 × 10 ^18.
A method for manufacturing a semiconductor substrate for a pressure sensor, comprising using a semiconductor substrate of atoms / cm ³ or more. 23. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein in the bonding step (P3), the pressure reference formed on the second substrate (2) is used. Recess (2) for chamber (7)
a) the direction of the side of the opening and the direction in which the cleavage direction of the first substrate (4) intersects the second substrate;
A method for manufacturing a semiconductor substrate for a pressure sensor, comprising bonding the substrate (2) and the first substrate (4). 24. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 23, wherein an opening of the recess (2a) for the pressure reference chamber (7) formed on the second substrate (2). Side direction and the first
Wherein the cleavage direction of the substrate (4) is adjusted so as to intersect at a maximum angle. 25. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 24, wherein when the plane orientation of the first substrate (4) is (100), on the second substrate (2). The direction of the side of the opening of the recess (2a) for the pressure reference chamber (7) formed in
22 to 23 ° with respect to the direction of the (100) plane and the direction of the (110) plane, which are the cleavage directions of the substrate (4).
A method of manufacturing a semiconductor substrate for a pressure sensor, wherein the directions are adjusted so as to intersect with each other at an angle around the center. 26. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein the first substrate is bonded in a cleaning step performed prior to the bonding step (P3). (4) At least the second substrate (2) of the second substrate (2) is subjected to a hydrophobizing treatment to remove moisture attached to the surface in a dehydration process. A method for manufacturing a semiconductor substrate for a pressure sensor. 27. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein in the bonding step (P3), the first substrate (4) and the second substrate ( 2. A method for manufacturing a semiconductor substrate for a pressure sensor, wherein 2) and 2) are adhered to each other by bringing them into close contact in a reduced pressure atmosphere. 28. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 1, wherein an insulating film separation substrate (44) is used as the second substrate, and the pressure reference chamber (33) is used. Is the insulating film separation substrate (4
4) A method of manufacturing a semiconductor substrate for a pressure sensor, which is formed in the semiconductor layer (46). 29. A semiconductor substrate (29, 43, 47) for use in a pressure sensor which electrically detects a pressure applied to a diaphragm (35) based on a stress generated by a pressure difference from a pressure reference chamber (33). In the manufacturing method of (1), a second substrate (3) is formed for forming the pressure reference chamber (33).
0), a concave portion forming step (P2) for providing a concave portion (34) for the pressure reference chamber (33), and a semiconductor layer (34) having a predetermined thickness for forming the diaphragm (35) are formed on the first substrate ( 40) on the insulating film (4
A bonding step (P3) of bonding the insulating film separation substrate (36) formed through 1) to the second substrate (30); and bonding the bonded insulating film separation substrate (36) to the back surface. After exposing the insulating film (41) from the thin film and removing the insulating film (41), the second substrate (30) is removed.
Forming a semiconductor layer (34) on the surface of the substrate to form the diaphragm (35) and the pressure reference chamber (33). 30. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 29, wherein the insulating film separation substrate (36) is peeled to a predetermined depth from one surface side of a third substrate (37). An ion implantation layer forming step (V1) for forming an ion implantation layer (38) for use in the third substrate (37) and a fourth substrate (40) separately prepared from the third substrate (37). Bonding the third substrate (37) with the ion implantation layer (38) to form an insulating film (41) on the fourth substrate (40). A semiconductor substrate for a pressure sensor, which is formed through a peeling step (V3) of forming a semiconductor layer (34) through a gap and a smoothing step of smoothing a surface of the peeled semiconductor layer (34). Manufacturing method. 31. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 29, wherein the insulating film is separated from the insulating film separating substrate (36) or deeper than the insulating film (41). (P3) forming an ion implantation layer (42) for use and bonding the substrate with the second substrate (30); and bonding the bonded insulating film separation substrate (36) to the ion implantation layer (42). By peeling, the insulating film separation substrate (36) is thinned, and the first substrate (40) is formed on the surface.
Alternatively, after exposing the insulating film (41), the first substrate (40) and the insulating film (41) are removed to form a semiconductor layer (3) on the surface of the second substrate (30).
4) A method for manufacturing a semiconductor substrate for a pressure sensor, comprising forming the diaphragm (35) and the pressure reference chamber (33). 32. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 29, wherein, in the recess forming step (P2), the surface of the second substrate (30) is etched. Forming the concave portion (32) by the method. 33. The method of manufacturing a semiconductor substrate for a pressure sensor according to claim 29, wherein in the bonding step (P3), the insulating film separation substrate (36) and the second substrate are provided. (30) in a reduced-pressure atmosphere, the method comprising the steps of: 34. The method for manufacturing a semiconductor substrate for a pressure sensor according to claim 29, wherein an insulating film separation substrate (44) is used as the second substrate. A method for manufacturing a semiconductor substrate.