JPH1174208A - Manufacture of semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a semiconductor substrate having a thick semiconductor layer without the use of an ion implantation apparatus of high energy output. SOLUTION: An element isolation groove as a separation groove is formed on a semiconductor layer substrate by etching (P1), and the surface thereof is thermally oxidized to form an oxide film (P2). Ions are implanted to the bottom of the element isolation groove, thus selectively forming an ion implantation layer (P3). The substrate is bonded (P5) with a supporting substrate having an oxide film formed thereon (P4). By carrying out heat treatment, peeling is carried out (P6). In this case, when defects are concentrated at the ion implantation layer portion for generating peeling-off, a peeling is induced also in other regions within the plane where the ion implantation layer is not formed, and that entire surface is peelid. The peeled surface is smoothed by polishing, and a semiconductor substrate is provided. The semiconductor layer of a large thickness can be formed, and damages due to ion implantation can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor substrate having a semiconductor layer for forming an element in an insulated state on a support substrate.

[0002]

As a semiconductor substrate having a single-crystal semiconductor layer for element formation in an insulating state on a support substrate, for example, an SOI (Silicon On Silicon) having a structure in which a silicon single crystal is provided as a semiconductor layer is used. Insulator) There is a substrate. This has a structure in which an oxide film is formed on a silicon substrate serving as a support substrate, and a silicon single crystal film is formed thereon. By using such a semiconductor substrate, an insulating separation process from the substrate is performed. Need not be separately performed, the separation performance is good, and an element can be formed on a silicon single crystal film with a high degree of integration to form an integrated circuit.

[0003] In this case, there are various conventional methods for manufacturing a silicon single crystal film provided on an SOI substrate. Among them, there is a semiconductor thin film manufacturing method which is manufactured through the following three steps. The technology is disclosed in Japanese Patent Laid-Open No. 5-211128.
Is disclosed. Hereinafter, the manufacturing method will be schematically described.

First, as a first step, a hydrogen gas or a rare gas is ionized into a single crystal silicon substrate, accelerated with a predetermined implantation energy, and implanted to a predetermined depth from the surface of the single crystal silicon substrate. An ion implantation region is formed so that ions are distributed. Next, as a second step, a support substrate formed of at least one rigid material is bonded to the surface of the single crystal silicon substrate on the side where the ions have been implanted by a bonding method or the like. In this case, it is preferable that an insulating film such as an oxide film is formed in that a semiconductor substrate can be used as the supporting substrate and an SOI substrate is finally formed.

Next, as a third step, heat treatment is performed in a state where the single-crystal silicon substrate and the supporting substrate are bonded to each other, so that the single-crystal silicon is formed with the microvoids (microbubbles) formed in the ion-implanted region as boundaries. The substrate and the thin film portion are separated so as to be separated, and an SOI substrate having a structure in which a silicon single crystal film is bonded over a supporting substrate with an insulating film interposed therebetween is formed.

Actually, since the peeled surface has irregularities of about several nm, the peeled surface is polished and etched to finish the silicon single crystal film flat and to have a predetermined thickness ( The thickness of the SOI substrate is adjusted to, for example, 0.1 μm.

In the above-mentioned technique, the principle is that a defect layer is formed in an ion-implanted region formed in a single-crystal silicon substrate and separation is performed. Therefore, the thickness of a single-crystal silicon film to be formed is reduced. Is set by the level of ion implantation energy for controlling the depth of the ion implantation region. However, in this case, for example, when the single crystal silicon film is formed as a relatively thick layer of about 10 μm, the acceleration energy of the hydrogen ions to be implanted requires a high level of acceleration energy exceeding 1 MeV.

Therefore, in reality, to perform such ion implantation, a high energy output ion implantation apparatus is required, which makes the apparatus expensive, and requires a large amount of electric power to perform the ion implantation processing. Therefore, there is a problem that the running cost becomes high, and a problem arises in the feasibility as a general-purpose technology.

In the above-described manufacturing method, the surface of the single-crystal silicon substrate is damaged in the ion implantation step, and oxygen and heavy metals are mixed due to the knock-on phenomenon. When the portion formed above and separated from the portion is used as a silicon single crystal film, there is a problem that the crystal quality as a single crystal film for forming an element is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to form a semiconductor substrate having a thick semiconductor layer by providing a high energy output to increase the thickness of the semiconductor layer. To provide a method for manufacturing a semiconductor substrate, in which a defect layer for peeling can be easily formed at low cost without using an ion implantation apparatus, and damage to a semiconductor layer can be reduced as much as possible. It is in.

[0011]

According to the first aspect of the present invention, in the groove forming step, a depth dimension corresponding to a film thickness of a semiconductor layer to be formed in a subsequent step is formed with respect to a semiconductor layer substrate. A separation groove is formed, and in the next ion implantation layer forming step, ion implantation is selectively performed on the inner bottom surface of the separation groove to form an ion implantation layer for separation. This allows
On the surface of the semiconductor layer substrate, an ion implanted layer is not formed at a portion used as a semiconductor layer, but an ion implanted layer is formed at a predetermined depth from the bottom of the peeling groove, and the whole is viewed. Then, an ion implantation layer is provided partially on the semiconductor layer substrate.

Thereafter, in a bonding step, a supporting substrate is bonded to the semiconductor layer substrate obtained through the above-described steps to form a close contact state, and in a subsequent peeling step, heat treatment is performed to form an ion-implanted layer. When the defective layer is concentrated and peeled, the entire surface including the ion-implanted layer is peeled, and the semiconductor layer is bonded to the supporting substrate.

Accordingly, even when a relatively thick semiconductor layer is formed, the thickness can be set by the depth of the separation groove. It is not necessary to use an ion implanter with high energy output, and this can be achieved by selectively performing ion implantation to a depth located slightly inward from the bottom surface of the separation groove.

Further, since an ion implantation layer is not formed in the semiconductor layer portion to be formed on the supporting substrate but is selectively implanted only into the inner bottom surface portion of the separation groove as described above, the ion implantation is performed. By doing so, it is possible to avoid a problem that the semiconductor layer is damaged or heavy metal contamination remains.

According to the second aspect of the present invention, in the groove forming step, the element separating groove for separating the semiconductor layer for each element forming region is formed as a separating groove, so that the element forming step is substantially performed. A separation groove can be provided as a part which also serves as a necessary element isolation region, and an area occupied by separation is eliminated, so that the chip area does not increase.

According to the third aspect of the present invention, in the oxide film forming step performed prior to the ion implanted layer forming step, the semiconductor layer substrate is thermally oxidized to form an oxide film on the surface.
An oxide film can be obtained in a state where an oxide film is formed on a side wall portion around a semiconductor layer which is finally formed through a peeling step, and when the surface of the semiconductor layer after the peeling is polished, the oxide film is a polishing stopper. It can be used as.

According to the fourth aspect of the present invention, the trench is formed at the position where the peeling groove is formed by the trench forming step performed prior to the groove forming step. The trench is formed at a position deeper than the trench for use, and the ion-implanted layer formed at the time of performing the ion-implanted layer forming step is at a predetermined depth from the bottom of the separation groove and shallower than the bottom of the trench. And an ion implantation layer separately formed at a predetermined depth from the bottom surface of the trench.

After that, when the semiconductor layer substrate and the support substrate are bonded in the bonding step, the trench and the separation groove are sealed inside by the two substrates. Then, when the peeling step is performed, when the entire temperature rises due to the heat treatment, the gas in the sealed trench and the peeling groove expands to increase the internal pressure.

By the action of the internal pressure, a force is applied in a direction in which the bottom surface of the trench is peeled when the semiconductor layer substrate is peeled off in the ion-implanted layer portion while leaving the semiconductor layer portion, so that the peeling is promoted. Peeling can be reliably performed on the surface including the ion-implanted layer.

According to the fifth aspect of the present invention, in the step of forming the ion-implanted layer, the mask member used for forming the separation groove in the groove formation step is reused to selectively form the bottom portion of the separation groove. Since the ion implantation is performed, it is not necessary to perform patterning for the ion implantation layer forming step, and the process can be simplified.

According to the sixth aspect of the present invention, the polishing step is performed after the peeling step is completed, whereby the surface of the semiconductor layer peeled and formed on the supporting substrate is polished to separate the semiconductor layer by the peeling groove. The semiconductor layer can be formed in a smooth state, and the surface of the semiconductor layer can be finished in a smooth state suitable for element formation.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG.
(C) schematically shows a cross section of the SOI substrate 1 which is a semiconductor substrate manufactured by the manufacturing method of the present invention. A silicon oxide film 3 as an insulating film is formed on a single crystal silicon substrate 2 as a supporting substrate, and a single crystal silicon layer 4 as a semiconductor layer is formed on the silicon oxide film 3 as an insulating film. An oxide film 5 is formed on the single-crystal silicon layer 4 on the side wall and the bottom surface. In the SOI substrate 1 having the above-described configuration, a concave region interposed between the adjacent single-crystal silicon layers 4 is buried with an insulating film such as an oxide film or polycrystalline silicon if necessary. The entire surface is formed to be flat.

Next, a method of manufacturing the SOI substrate 1 having the above-described configuration will be described with reference to the schematic diagram of FIG. First, a single crystal silicon substrate 6 (FIG. 2) as a semiconductor layer substrate having at least one surface mirror-polished.
(See (a)), an element isolation groove 7 which also functions as a separation groove is formed in an element isolation groove forming step P1 (see FIG. (B)). To form the element isolation groove 7,
This is performed by etching the surface patterned by photolithography to a predetermined depth using a method such as dry etching.

At this time, the element isolation groove 7 has, for example, a width of about 0.5 to 5 μm and a depth of 0.5 to 30 μm.
m. This depth dimension sets the thickness of the single crystal silicon layer 4 which is a semiconductor layer obtained by performing a peeling step, as described later, so that the depth in accordance with the specification is determined. Set so that it becomes the size. Next, in the thermal oxidation step P2, the single crystal silicon substrate 6 is thermally oxidized to form an oxide film 5 on its surface and also on the bottom and side walls in the element isolation trench 7 (see FIG. 3C). ).

Subsequently, in an ion implantation layer forming step P3, a photoresist 8 is formed by photolithography.
Is patterned so that only the element isolation groove 7 is exposed. Thereafter, ion implantation is performed using the photoresist 8 as a mask. Thus, the ion-implanted layer 9 is selectively formed at a predetermined depth only on the bottom surface of the element isolation groove 7 (see FIG. 4D). Thereafter, the photoresist 8 remaining on the surface of the single crystal silicon substrate 6 is removed.

The single-crystal silicon substrate 2 as a support substrate, which is a substrate to be bonded to the single-crystal silicon substrate 6 as a semiconductor layer substrate formed as described above,
In the oxide film forming step P4, an oxide film 3 is formed on the surface. Here, the oxide film forming step P4 is provided as a configuration in which the oxide film 3 is provided on the single-crystal silicon substrate 2 on the supporting substrate side, but the process proceeds to the bonding step P5 without providing the oxide film 3. It is also possible.

Subsequently, in the bonding step P5,
The surface of the single-crystal silicon substrate 2 on which the oxide film 3 is formed is bonded to the surface of the single-crystal silicon substrate 6 on which the element isolation groove 7 is formed (see FIG. 3A). In this case, at the time of bonding, each of the single-crystal silicon substrates 2 and 6 is subjected to a hydrophilic treatment, for example, by using H ₂ SO ₄ and H ₂ SO _4.
The substrate is washed with a treating solution in which ₂ O ₂ is mixed at a ratio of 4: 1 and also with pure water, and thereafter, a treatment is performed in a state where the amount of moisture adsorbed on the surface is controlled by spin drying. As a result, both of the single crystal silicon substrates 2 and 6 are bonded by the hydrogen bond between the silanol groups formed on the respective surfaces and the water molecules adsorbed on the surfaces.

Thereafter, in the peeling step P6, the bonded single-crystal silicon substrates 2 and 6 are subjected to a heat treatment in a nitrogen atmosphere or an oxygen atmosphere. In this heat treatment, for example, 4
A method of sequentially performing a first heat treatment performed at about 500 ° C. in the range of 00 ° C. to 600 ° C., and a second heat treatment performed at about 1000 ° C. or more and about 1100 ° C .; There is a way to do it all at once.

By performing this heat treatment, a dehydration condensation reaction occurs on the bonding surfaces of the two substrates 2 and 6,
The bonding state can be made stronger. Also,
In the hydrogen ion-implanted layer 9, defects are locally concentrated by this heat treatment. At this time, the ratio of the area occupied by the defect layer to the entire surface of the bonded single-crystal silicon substrates 2 and 6 is equal to or more than a predetermined value depending on the conditions set in advance. The entire surface is peeled off in that plane (see FIG. 3B).

Thus, single crystal silicon layer 4 can be formed on surface of single crystal silicon substrate 2 with oxide films 3 and 5 interposed therebetween. The thickness of the single-crystal silicon layer 4 at this time is substantially equal to the depth dimension of the element isolation groove 7 because the single-crystal silicon layer 4 is separated at the surface where the ion-implanted layer 9 is formed. Have been. Further, since the ion implantation layer 9 is not formed in the single crystal silicon layer 4, it is possible to prevent the single crystal silicon layer 4 from being adversely affected by damage caused by ion implantation.

The above-mentioned area ratio depends on the ion-implanted layer 9.
It is anticipated that the region occupied by the element isolation groove 7 for forming the ion-implanted layer 9 substantially varies depending on various conditions such as the dose amount, width dimension, depth dimension, and substrate size. Therefore, it is preferable that the area be as small as possible so that peeling can be surely performed.

Thereafter, in a polishing step P7, the surface of the single-crystal silicon layer 4 is polished so as to reduce the surface roughness by polishing the peeled surface so that the element isolation groove 7 is exposed. I do. As a result, FIG.
The semiconductor substrate 1 as shown in FIG.

According to the present embodiment, in order to form the SOI substrate 1 in which the thickness of the single crystal silicon layer 4 formed by peeling is increased to 1 μm or more, the SOI substrate 1 is formed from the bottom of the element isolation groove 7. Irrespective of the film thickness, this can be achieved by forming the ion-implanted layer 9 at a shallow depth with a low acceleration voltage, so that it is not necessary to use a device capable of implanting high-energy ion implantation acceleration energy on the order of MeV.

Further, according to the present embodiment, the entire surface is peeled at the time of peeling while the ion-implanted layer 9 is selectively formed on the bottom surface of the element isolation groove 7, so that it is formed on the surface of the single-crystal silicon substrate 2. Hydrogen ions are not implanted into the single-crystal silicon layer 4 by ion implantation, and a high-quality single layer without defects or metal contamination due to ion implantation can be obtained.

(Second Embodiment) FIGS. 4 to 6 show a second embodiment of the present invention. Hereinafter, portions different from the first embodiment will be described. In the second embodiment, the SOI substrate 1 to be finally formed is
0 is substantially the same as the SOI substrate 1 in the first embodiment, but in the manufacturing process, as shown in FIG.
A different step is provided in the processing step for.

First, in the same manner as described above, a trench 11 is formed in a trench forming step S1 on a single crystal silicon substrate 6 as a semiconductor layer substrate having at least one surface mirror-polished (FIG. 5A). reference). To form the trench 11, a surface patterned by photolithography is formed by a method such as dry etching. The trench 11 is patterned so as to be located at the center of the element isolation groove 7 to be formed later. For example, the trench 11 has a width of about 0.5 to 2 μm and a depth of about 0.5 μm.
It is formed to about 30 μm.

Subsequently, in the element isolation groove forming step S2 as a groove forming step, the trench 11 is formed as described above.
Is formed to form the element isolation groove 7. in this case,
The trench 11 is set to have a smaller width and a larger depth than the element isolation groove 7. Also,
The element isolation groove 7 and the trench 11 are formed so as not to open from the end of the wafer constituting the single-crystal silicon substrate 6, so that the state is sealed when the bonding step S <b> 6 is performed.

Next, in the ion implantation layer forming step S3, hydrogen ions are implanted again using the photoresist 8 used for forming the element isolation trench 7 as a mask member. As a result, the ion-implanted layer 9 is formed at a predetermined depth from the bottom surface of the isolation trench 7 and the trench 11 is formed.
The ion implanted layer 9a is formed in the same size from the bottom surface of FIG. In this case, the formation depth of the ion implantation layer 9 is set to be a position shallower than the bottom surface of the trench 11. Thereafter, the photoresist 8 on the surface of the single crystal silicon substrate 6 is removed.

Subsequently, in the thermal oxidation step S4, the single-crystal silicon substrate 6 is subjected to thermal oxidation to form an oxide film 5 on the surface thereof and also on the bottom and side walls in the isolation trenches 7 and the trenches 11 (FIG. FIG. (D)). At this time, the heat treatment causes the defects to concentrate on the ion-implanted layers 9 and 9a, but at this stage, the peeling phenomenon does not occur.

This is because the ion implantation layers 9 and 9a are formed only on the bottom surfaces of the element isolation trenches 7 and the trenches 11, that is, the ion implantation layers are not formed on the entire substrate. This is because it can be avoided. In order to prevent the separation phenomenon from occurring at this stage, the ion implantation amount (dose amount) to the ion implantation layers 9 and 9a may be set to be small.

Next, an oxide film forming step S5 for forming an oxide film 3 on the single crystal silicon substrate 2 as a support substrate is performed, and a bonding step S6 is performed to bond the single crystal silicon substrates 2 and 6 together. (See FIG. 6A), and the element isolation groove 7 and the trench 1 as described above.
Since 1 is formed so as not to open at the end of the wafer, it is in a sealed state isolated from the outside.

In the subsequent stripping step S7, heat treatment is performed in the same manner as described above. In this case, in this case, the element isolation grooves 7,
Since the inside of the trench 11 is formed as the closed space A, the gas such as air existing inside expands and the internal pressure increases. Thereby, in a state where the peeling phenomenon occurs,
The internal pressure acts in the direction in which peeling occurs, thereby promoting the peeling phenomenon. At this time, the part firmly bonded by bonding remains on the single crystal silicon substrate 2 side, and in a plane where the separation phenomenon occurs in the region where the ion-implanted layer 9 is formed, the separation phenomenon causes a chain. A peeling phenomenon occurs (see FIG. 3B).

As a result, the single-crystal silicon layer 4 can be peeled off on the surface of the single-crystal silicon substrate 2. Thereafter, a polishing step S8 is performed to polish the peeled surface, which is the surface of the single crystal silicon layer 4, so as to reduce the surface roughness of the surface and to polish the element isolation groove 7 so as to be exposed. As a result, a semiconductor substrate 10 as shown in FIG. Also in the second embodiment, it is preferable that the area ratio of the element isolation groove 7 is set to a minimum area such that the separation can be surely performed.

According to such a second embodiment, the first
The same effect as that of the embodiment can be obtained, and the separation phenomenon is promoted by increasing the internal pressure in the separation step by forming the element isolation groove 7 and the trench 11 in a sealed state, thereby improving the ion implantation step S3. The dose can be set lower than in the first embodiment,
As a result, the separation can be reliably performed, and the time required for ion implantation can be reduced.

(Third Embodiment) FIGS. 7 and 8 show a third embodiment of the present invention. The difference from the first embodiment is that an SOI substrate 12 (FIG. c)), the thermal oxidation step P2 (FIG. 1)
(See FIG. 3), the oxide film 5 formed also in the element isolation groove 7 is not provided, and the subsequent steps are performed, and the oxide film forming step P4 for the supporting substrate is not performed.

That is, in the element isolation trench forming step P1, an oxide film 13 is first formed on the surface of a single crystal silicon substrate 6 which is a semiconductor layer substrate (see FIG. 7A) (see FIG. 7A). (See (b)), a window 13a for the element isolation groove 7 is formed in the oxide film 13 by photolithography, and the photoresist 13 is removed. Then, the oxide film 13 is used as a mask member for etching. By doing so, an element isolation groove 7 as a separation groove is formed (see FIG. 3C).

In the next ion implantation layer forming step P3 (the thermal oxidation step P2 in the first embodiment is not performed), the oxide film 13 is used as a mask member as it is, and the bottom portion in the element isolation groove 7 is formed. Only in this case, the ion implantation layer 9 is selectively formed at a predetermined depth (see FIG. 4D).
Next, unlike the first embodiment, the process proceeds to the bonding step P5 without forming the oxide film 3 on the single-crystal silicon substrate 2 as the support substrate. Then, the SOI substrate 11 can be obtained through a bonding step P5 (see FIG. 8A), a peeling step P6 (see FIG. 8B), and a polishing step P7 (see FIG. 8C). Become.

In this embodiment, the oxide film 13 formed on the single-crystal silicon substrate 6 is left as it is after the ion-implanted layer forming step P3 and is used for bonding. The film 13 may be peeled off by etching prior to the bonding step P5. Alternatively, the oxide film 3 may be formed by performing the oxide film forming step P4 on the single crystal silicon substrate 2 which is a supporting substrate. it can. Further, an oxide film forming step P4 of forming the oxide film 3 on the single crystal silicon substrate 2 while leaving the oxide film 13 may be performed.

Then, the SO formed as described above is formed.
The I-substrate 11 has a state in which the single-crystal silicon film 4 as a semiconductor layer is separated and arranged in an island shape by the element isolation trenches 7. By embedding an insulating film such as an oxide film, polycrystalline silicon, or the like in a concave region interposed therebetween, the entire surface is formed in a flat state.

(Fourth Embodiment) FIGS. 9 to 12 show a fourth embodiment of the present invention. The difference from the second embodiment is that an SOI substrate 14 as a semiconductor substrate is used.
In the manufacturing process shown in FIG. 10C, the trench forming process S1 is different, and the thermal oxidation process S4 is not performed.

That is, in the trench forming step S1, etching is performed by photolithography so as to form a shallow groove 11a. In this case, the depth of the groove 11a may be a depth larger than the depth of the ion-implanted layer 9, and may be, for example, about 0.5 μm (FIG. 9).
(A)). Next, in an element isolation groove forming step S2, the photoresist 8 is similarly formed by photolithography.
Is patterned into a shape for forming the element isolation groove 7. Thereafter, an etching process is performed using the photoresist as a mask member to form the element isolation groove 7 and the trench 11 (see FIG. 3B).

The trench 11 is formed by advancing the etching at the same etching rate so that the portion where the groove 11a is formed is etched in the same step shape as it is. In addition,
Since the trench 11 is formed in this manner, there is an advantage that the photolithography process can be performed without any problem compared to the case where only the trench 11 is formed in advance.

Thereafter, an ion-implanted layer forming step S3 is performed to form ion-implanted layers 9 and 9a (see FIG. 3C), and the photoresist 8 as a mask member is peeled off.
Thereafter, in this embodiment, the thermal oxidation step is not performed. Thereafter, an oxide film forming step S5, a bonding step S6 (see FIG. 10A), a peeling step S6 (see FIG. 10B), and a polishing step S7 (see FIG. 10C) are performed. Thus, the SOI substrate 14 can be obtained.

The SOI formed as described above
In the substrate 14, the single crystal silicon film 4 as a semiconductor layer is in a state of being separated and arranged in an island shape by the element isolation groove 7. Thereafter, if necessary, between the adjacent single crystal silicon layers 4. By embedding an insulating film such as an oxide film or polycrystalline silicon in the intervening concave region, the entire surface is formed to be flat.

FIG. 11 shows the manufacturing process. Hereinafter, the manufacturing process will be described with reference to FIG.
That is, in the manufacturing process, an SOI substrate 15 as a flattened semiconductor substrate is obtained by performing the oxide film forming step Q1, the polycrystalline silicon forming step Q2, the polishing step Q3, and the oxide film removing step Q4. (FIG. 12
(D)).

First, in the oxide film forming step Q1, an oxide film 16 is formed on the surface by a method such as thermal oxidation or the like (FIG. 12).
(A)), in the subsequent polycrystalline silicon forming step Q2,
On this, a polycrystalline silicon film 17 is deposited and formed by a method such as a CVD method (see FIG. 1B). In this case, the thickness of the polycrystalline silicon film 17 needs to be set to a thickness that fills the element isolation trench 7.

Next, in the polishing step Q3, the substrate surface is polished to polish the polycrystalline silicon film 17, and when the polished surface reaches the surface of the oxide film 16, the polishing rate of the oxide film 16 is low. It functions as a polishing stopper, and when the polishing progresses to this portion, the polishing process is stopped (see FIG. 3C). Thereafter, an oxide film removing step Q
4, the oxide film 16 exposed on the surface is selectively etched away using a hydrofluoric acid-based etchant or the like, thereby forming the surface of the single crystal silicon film 4 in an exposed state. An SOI substrate 15 is obtained.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. It is not limited to the element isolation groove, and may be formed as an appropriate separation groove, for example, formed as an isolation groove for separating a plurality of elements into a unit area, or formed as an isolation groove for separating a chip unit area. it can. Moreover, it is also possible to form as a peeling groove exclusive for peeling as needed.

With respect to those obtained as the semiconductor substrates 1 and 11, the recesses remaining in the portions corresponding to the element isolation grooves 7 may be buried so as to be filled with an oxide film in a later step to form a flat surface. it can. The formation of the oxide film 3 on the single crystal silicon substrate 2 as a support substrate may be performed as needed.

[Brief description of the drawings]

FIG. 1 is a schematic process explanatory view showing a first embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view in each step (part 1).

FIG. 3 is a schematic cross-sectional view in each step (part 2).

FIG. 4 is a view corresponding to FIG. 1, showing a second embodiment of the present invention;

FIG. 5 is a schematic cross-sectional view in each step (part 1).

FIG. 6 is a schematic cross-sectional view in each step (part 2).

FIG. 7 is a view corresponding to FIG. 2, showing a third embodiment of the present invention;

FIG. 8 is a diagram corresponding to FIG. 3;

FIG. 9 is a view corresponding to FIG. 5 in each step showing the fourth embodiment of the present invention.

FIG. 10 is a diagram corresponding to FIG. 6;

FIG. 11 is a process chart for performing a flattening process.

FIG. 12 is a schematic sectional view of each step.

[Explanation of symbols]

1, 10, 12, 14, 15 are SOI substrates (semiconductor substrates), 2 is a single-crystal silicon substrate (support substrate), 3 is an oxide film, 4 is a single-crystal silicon layer (semiconductor layer), 5 is an oxide film,
Reference numeral 6 denotes a single crystal silicon substrate (substrate for a semiconductor layer), 7 denotes an element isolation groove (separation groove), 8 denotes a photoresist (mask member), 9 denotes an ion implantation layer, 11 denotes a trench, 11a denotes a groove, and 13 denotes oxidation. The films, 16 oxide films, and 17 are polycrystalline silicon films.

Claims (7)

[Claims] 1. A semiconductor substrate (1, 1) comprising a support substrate (2) and a semiconductor layer (4) for element formation provided in an insulated state.
0) In the manufacturing method of 0), a separation groove (7) having a depth dimension corresponding to the thickness of the semiconductor layer (4) with respect to a semiconductor layer substrate (6) for forming the semiconductor layer (4). Groove forming step (P1,
S2) an ion implantation layer for selectively performing ion implantation on the inner bottom surface of the separation groove (7) formed in the semiconductor layer substrate (6) to form a separation ion implantation layer (9). A forming step (P3, S3); a bonding step (P5, S6) of bonding the support substrate (2) to the semiconductor layer substrate (6) having the ion-implanted layer (9) formed thereon. The semiconductor layer (4) is placed on the support substrate (2) by heat-treating the semiconductor layer substrate (6) and the support substrate (2) and peeling off the surface including the ion-implanted layer (9). A method for manufacturing a semiconductor substrate, comprising: a separation step (P6, S7) for forming. 2. The method for manufacturing a semiconductor substrate according to claim 1, wherein, in said groove forming step (P1, S2), an element isolation groove (IV) for separating said semiconductor layer (4) for each element formation region. 7) is formed as the separation groove. 3. The method of manufacturing a semiconductor substrate according to claim 1, wherein prior to the step (P3) of forming the ion-implanted layer, the substrate for the semiconductor layer (6) is thermally oxidized to form an oxide film on the surface. A method for manufacturing a semiconductor substrate, comprising an oxide film forming step (P2) for forming (5). 4. The method for manufacturing a semiconductor substrate according to claim 1, which is performed prior to the groove forming step (S2), and the separation groove (7) is formed along a position where the separation groove (7) is formed. 7) A trench forming step (S1) for forming a trench (11) narrower than that of the trench (11) is formed in the trench forming step (S1) and the next groove forming step (S2). 7) is formed such that the inside is sealed when the substrate is bonded to the support substrate (2) in the bonding step (S6). In the ion implantation layer forming step (S3), The depth of the ion-implanted layer (9) formed by ion-implanting from the bottom surface of the separation groove (7) is determined by the groove forming step (S
Forming a trench at a position shallower than the depth of the bottom surface of the trench (11) after the step (2). 5. The method for manufacturing a semiconductor substrate according to claim 4, wherein the ion-implanted layer forming step (S3) is a mask when the separation groove (7) is formed in the groove forming step (S2). A method for manufacturing a semiconductor substrate, wherein a member (8) is reused to selectively perform ion implantation on a bottom surface of the separation groove (7). 6. The method of manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor layer formed on the support substrate (2) after completion of the separation step (P6, S7). A polishing step (P) in which the surface of (4) is polished to form the semiconductor layer (4) in a state of being separated by the separation groove (7).
7, S8). A method for manufacturing a semiconductor substrate, the method comprising: 7. The method of manufacturing a semiconductor substrate according to claim 1, wherein the surface of the semiconductor substrate (2) used as the support substrate (2) prior to the bonding step (P5, S6). An oxide film forming step (P4,
A method for manufacturing a semiconductor substrate, comprising providing S5).