JPH1145862A - Manufacture of semiconductor substrate - Google Patents

Manufacture of semiconductor substrate

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Publication number
JPH1145862A
JPH1145862A JP19850197A JP19850197A JPH1145862A JP H1145862 A JPH1145862 A JP H1145862A JP 19850197 A JP19850197 A JP 19850197A JP 19850197 A JP19850197 A JP 19850197A JP H1145862 A JPH1145862 A JP H1145862A
Authority
JP
Japan
Prior art keywords
substrate
layer
ion implantation
bonded
ion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19850197A
Other languages
Japanese (ja)
Inventor
Masaki Matsui
正樹 松井
Shoichi Yamauchi
庄一 山内
Hisazumi Oshima
大島  久純
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP19850197A priority Critical patent/JPH1145862A/en
Publication of JPH1145862A publication Critical patent/JPH1145862A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PROBLEM TO BE SOLVED: To enable separation, while ion implantation in forming an ion implantation layer for separation is carried out with a low dose. SOLUTION: On a surface portion of a bonding wafer 15 made of a single- crystal silicon substrate, grooves 16 are formed which extend longitudinally and laterally to partition the wafer into regions, each corresponding to one chip, and which have a depth greater than an ion implantation layer 17 and are not open at peripheral edge portions of the bonding wafer 15. Hydrogen gas is ionized and implanted with respect to the bonding wafer 15, thus forming the ion implantation layer 17 for separation at a predetermined depth. Then, the bonding wafer 15 is bonded to a base substrate 12, having an insulating film 13 formed thereon in advance. At this point, sealed hollow portions 18 are formed by the grooves 16. After that, a separation step of separating the bonding wafer 15 on the ion implantation layer 17 is carried out by heat treatment. At this point, air within the hollow portions 18 expands thermally to promote the separation.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ベース基板上に素
子形成用の単結晶半導体層をそのベース基板との絶縁状
態に設けてなる半導体基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate in which a single crystal semiconductor layer for element formation is provided on a base substrate in an insulated state from the base substrate.

【0002】[0002]

【発明が解決しようとする課題】この種の半導体基板と
して、例えばシリコン基板上に絶縁膜を介してシリコン
単結晶層を設けて構成されるSOI(Silicon On Insul
ator)基板がある。このSOI基板を製造するための方
法として、例えば特開平5−211128号公報に示さ
れるような、貼合わせを用いた製造方法が提案されてい
る。
As this type of semiconductor substrate, for example, an SOI (Silicon On Insul) formed by providing a silicon single crystal layer on a silicon substrate via an insulating film.
ator) There is a substrate. As a method for manufacturing the SOI substrate, for example, a manufacturing method using bonding has been proposed as disclosed in Japanese Patent Application Laid-Open No. 5-211128.

【0003】この方法では、図5に示すように、3つの
段階(工程)を経てSOI基板が製造される。即ち、第
1段階では、図5(a)に示すように、シリコン単結晶
基板からなる貼合せ基板1に対し、例えば水素ガスをイ
オン化して所定の注入エネルギーで加速して注入する工
程が行われ、これにて貼合せ基板1の所定深さ位置にイ
オン注入層2が形成される。この場合、貼合せ基板1の
うちイオン注入層2の上部の層が、最終的に得たいシリ
コン単結晶薄膜層1aとなる。
In this method, as shown in FIG. 5, an SOI substrate is manufactured through three stages (processes). That is, in the first stage, as shown in FIG. 5A, for example, a process of ionizing hydrogen gas and accelerating it with a predetermined implantation energy into the bonded substrate 1 made of a silicon single crystal substrate is performed. Thus, the ion implantation layer 2 is formed at a predetermined depth position of the bonded substrate 1. In this case, the layer above the ion-implanted layer 2 in the bonded substrate 1 becomes the silicon single-crystal thin film layer 1a finally desired to be obtained.

【0004】次の第2段階では、図5(b)に示すよう
に、例えばシリコン単結晶基板からなるベース基板3の
上面に、上記貼合せ基板1を、図5(a)とは上下反転
した状態で貼合わせる工程が行われる。このとき、前記
ベース基板3の表面には予め酸化膜からなる絶縁膜4が
形成されている。そして、第3段階では、図5(c)に
示すように、例えば400〜600℃の熱処理によっ
て、前記貼合せ基板1からシリコン単結晶薄膜層1aを
イオン注入層2に沿って剥離させる工程が行われる。
In the next second stage, as shown in FIG. 5 (b), the bonded substrate 1 is turned upside down on the upper surface of a base substrate 3 made of, for example, a silicon single crystal substrate, as shown in FIG. 5 (a). The laminating step is performed in the state of being bonded. At this time, an insulating film 4 made of an oxide film is formed on the surface of the base substrate 3 in advance. Then, in the third step, as shown in FIG. 5C, a step of separating the silicon single crystal thin film layer 1a from the bonded substrate 1 along the ion implantation layer 2 by a heat treatment at 400 to 600 ° C., for example. Done.

【0005】これにて、ベース基板3上に絶縁膜4を介
してシリコン単結晶薄膜層1aが貼合わされた形態とな
り、その後、図5(d)に示すように、剥離面が研磨さ
れることにより、品質の高いシリコン単結晶薄膜層1a
を有するSOI基板5が得られるのである。尚、前記貼
合せ基板1は、厚みを減少させながら再使用することが
可能となる。
As a result, the silicon single crystal thin film layer 1a is bonded to the base substrate 3 with the insulating film 4 interposed therebetween, and then the peeled surface is polished as shown in FIG. The high quality silicon single crystal thin film layer 1a
Is obtained. Note that the bonded substrate 1 can be reused while reducing its thickness.

【0006】ところで、上記剥離工程において前記イオ
ン注入層2での剥離(割れ)を確実に行うためには、イ
オン注入の工程において、水素イオンのドーズ量を、1
×1016atoms/cm2 程度とすることが必要であった。
このため、上記した従来の方法では、イオン注入の工程
に比較的長い時間を要するものとなっていた。
By the way, in order to surely separate (crack) the ion-implanted layer 2 in the above-mentioned separating step, the dose of hydrogen ions must be set to 1 in the ion-implanting step.
It was necessary to be about × 10 16 atoms / cm 2.
Therefore, in the above-described conventional method, a relatively long time is required for the ion implantation process.

【0007】本発明は上記事情に鑑みてなされたもの
で、その目的は、イオン注入層を形成した貼合せ基板を
ベース基板上に貼合せた後そのイオン注入層にて切離す
ようにしたものにあって、イオン注入を低ドーズ量で済
ませながらも剥離を可能とし、ひいては、イオン注入層
形成の工程に要する時間の短縮化を図ることができる半
導体基板の製造方法を提供することにある。
The present invention has been made in view of the above circumstances, and an object of the present invention is to bond a bonded substrate having an ion-implanted layer formed thereon to a base substrate and then cut off the bonded substrate at the ion-implanted layer. In view of the above, an object of the present invention is to provide a method of manufacturing a semiconductor substrate, which enables peeling while performing ion implantation at a low dose, and thereby can reduce the time required for the step of forming an ion-implanted layer.

【0008】[0008]

【課題を解決するための手段】本発明の半導体基板の製
造方法は、ベース基板上に絶縁膜を介して素子形成用の
単結晶半導体層を設けてなる半導体基板を製造するため
の方法にあって、単結晶半導体からなる貼合せ基板の表
面部の所定深さにイオン注入を行うことにより、該貼合
せ基板の表層部に単結晶半導体層となるべき単結晶薄膜
層を確保した状態に剥離用のイオン注入層を形成するイ
オン注入層形成工程と、前記ベース基板に対し単結晶薄
膜層が形成された貼合せ基板をその単結晶薄膜層の表面
にて絶縁膜を介して貼合わせる貼合せ工程と、前記ベー
ス基板上に貼合わされた貼合せ基板を熱処理によりイオ
ン注入層にて切離す剥離工程とを含むと共に、前記ベー
ス基板と貼合せ基板との貼合せ状態において、それらベ
ース基板と貼合せ基板との間に、密閉状態の中空部が前
記単結晶薄膜層及びイオン注入層を部分的に除去した形
態に形成されているところに特徴を有する(請求項1の
発明)。
The method of manufacturing a semiconductor substrate according to the present invention is a method for manufacturing a semiconductor substrate having a single crystal semiconductor layer for forming an element provided on a base substrate via an insulating film. Then, ion implantation is performed at a predetermined depth of the surface portion of the bonded substrate made of a single crystal semiconductor, thereby peeling off in a state where a single crystal thin film layer to be a single crystal semiconductor layer is secured in a surface layer portion of the bonded substrate. Ion-implanted layer forming step of forming an ion-implanted layer for bonding, and laminating a laminated substrate having a single-crystal thin film layer formed on the base substrate via an insulating film on the surface of the single-crystal thin film layer And a peeling step of separating the bonded substrate bonded on the base substrate by an ion implantation layer by heat treatment, and bonding the base substrate and the bonded substrate in a bonded state of the base substrate and the bonded substrate. Matching Between the plate, it has a feature where the hollow portion of the sealed state is formed partially removed form the single-crystal thin film layer and the ion implantation layer (invention of claim 1).

【0009】これによれば、イオン注入層形成工程にお
いて、貼合せ基板の表層部にイオン注入層により仕切ら
れた形態の単結晶薄膜層が形成され、貼合せ工程におい
て、ベース基板に対して貼合せ基板がその単結晶薄膜層
の表面にて貼合わされる。この貼合せ状態では、ベース
基板と貼合せ基板との間に、密閉状態の中空部が単結晶
薄膜層及びイオン注入層を部分的に除去した形態つま
り、貼合せ基板のうちのイオン注入層よりも基部側のバ
ルク部分の一部を露呈させた状態に形成されている。そ
して、この状態から、熱処理により貼合せ基板をイオン
注入層にて切離す剥離工程が行われ、ベース基板上に、
絶縁膜を介して素子形成用の単結晶半導体層を有する半
導体基板が得られる。
According to this, in the step of forming an ion-implanted layer, a single-crystal thin-film layer having a form partitioned by the ion-implanted layer is formed on the surface layer of the bonded substrate. A laminated substrate is bonded on the surface of the single crystal thin film layer. In this lamination state, between the base substrate and the lamination substrate, the sealed hollow portion is a form in which the single crystal thin film layer and the ion implantation layer are partially removed, that is, from the ion implantation layer of the lamination substrate. The base is also formed in a state where a part of the bulk portion on the base side is exposed. Then, from this state, a peeling step of separating the bonded substrate by the ion implantation layer by heat treatment is performed, and on the base substrate,
A semiconductor substrate having a single crystal semiconductor layer for element formation is obtained via the insulating film.

【0010】このとき、ベース基板と貼合せ基板との間
に密閉状態の中空部が形成されているため、上記剥離工
程における熱処理により、中空部内の気体が熱膨脹し、
その圧力が中空部を押し拡げる、言換えるならば、貼合
せ基板のうちのイオン注入層よりも基部側をベース基板
から引剥がす方向の力となって作用するようになる。こ
のため、いわば内部から剥離を助長する力が得られるこ
とになり、その分、イオン注入層における欠陥状態(イ
オンの注入量)が十分でなくとも、イオン注入層での剥
離が容易になされるようになる。このことは、イオン注
入層の注入イオンのドーズ量を少なくしても剥離が容易
に行われることを意味しているのである。
[0010] At this time, since the hermetically sealed hollow portion is formed between the base substrate and the bonded substrate, the gas in the hollow portion thermally expands by the heat treatment in the peeling step,
The pressure expands the hollow portion, in other words, acts as a force in the direction of peeling the base side of the bonded substrate from the base substrate with respect to the ion-implanted layer from the base substrate. For this reason, a force that promotes separation can be obtained from the inside, so that separation can be easily performed in the ion implantation layer even if the defect state (ion implantation amount) in the ion implantation layer is not sufficient. Become like This means that separation can be easily performed even if the dose of implanted ions in the ion implantation layer is reduced.

【0011】従って、本発明の請求項1の半導体基板の
製造方法によれば、イオン注入層を形成した貼合せ基板
をベース基板上に貼合せた後そのイオン注入層にて切離
すようにしたものにあって、イオン注入を低ドーズ量で
済ませながらも剥離を可能とし、ひいては、イオン注入
層形成の工程に要する時間の短縮化を図ることができる
という優れた実用的効果を奏するものである。
Therefore, according to the method of manufacturing a semiconductor substrate according to the first aspect of the present invention, the bonded substrate having the ion-implanted layer formed thereon is bonded to the base substrate and then separated at the ion-implanted layer. The present invention has an excellent practical effect that it enables separation while keeping the ion implantation at a low dose, and thus can reduce the time required for the step of forming an ion-implanted layer. .

【0012】この場合、密閉状態の中空部を形成する方
法として、貼合せ基板の表面部に、イオン注入層の深さ
より深く且つ貼合せ基板の周縁端部に開放しない溝部を
形成した上で、その溝部以外の部分でベース基板に対す
る貼合せを行えば良い。このとき、その溝部の形成は、
イオン注入層形成工程の前に行っても良く(請求項2の
発明)、イオン注入層形成工程の後に行っても良い(請
求項3の発明)。これにより、中空部を簡単に形成する
ことができるようになる。
In this case, as a method of forming a closed hollow portion, a groove portion which is deeper than the depth of the ion-implanted layer and is not opened at the peripheral edge of the bonded substrate is formed on the surface portion of the bonded substrate. Attachment to the base substrate may be performed at a portion other than the groove. At this time, the formation of the groove is
It may be performed before the ion implantation layer forming step (the invention of claim 2) or after the ion implantation layer forming step (the invention of claim 3). Thus, the hollow portion can be easily formed.

【0013】さらにこのとき、前記溝部を、ベース基板
上に設けられる素子形成用の単結晶半導体層を1素子単
位,ウェル単位,回路単位あるいは1チップ毎に区画す
る形態に形成することができる(請求項4の発明)。こ
れによれば、ベース基板上の素子形成用の単結晶半導体
層が、予め1素子単位,ウェル単位,回路単位あるいは
1チップ毎に分離された形態の半導体基板が得られるよ
うになる。
Further, at this time, the groove can be formed in such a form that a single crystal semiconductor layer for element formation provided on the base substrate is divided into one element unit, one well unit, one circuit unit or one chip. The invention of claim 4). According to this, it is possible to obtain a semiconductor substrate in which a single crystal semiconductor layer for element formation on the base substrate is separated in advance for each element, each well, each circuit, or each chip.

【0014】[0014]

【発明の実施の形態】以下、本発明を、シリコン基板上
に絶縁膜を介してシリコン単結晶層を設けたSOI(Si
licon On Insulator)基板の製造に適用した第1の実施
例(請求項1,2,4に対応)について、図1ないし図
3を参照しながら説明する。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to an SOI (Si / Si) having a silicon single crystal layer provided on a silicon substrate via an insulating film.
A first embodiment (corresponding to claims 1, 2 and 4) applied to the manufacture of a (icon on insulator) substrate will be described with reference to FIGS.

【0015】まず、本実施例に係る製造方法により得ら
れる半導体基板(SOI基板)11は、図1(e)に示
すように、例えば単結晶シリコン基板(シリコンウエ
ハ)からなるベース基板12上に、シリコン酸化膜から
なる絶縁膜13を介して、シリコン単結晶からなる素子
形成用の単結晶半導体層14を有して構成される。この
場合、単結晶半導体層14は、ベース基板12の全面に
設けられるのではなく、最終的に1チップ(あるいは1
素子単位,ウェル単位,回路単位)となる領域毎に間隔
をもって分離された形態に設けられる。
First, as shown in FIG. 1E, a semiconductor substrate (SOI substrate) 11 obtained by the manufacturing method according to this embodiment is placed on a base substrate 12 made of, for example, a single crystal silicon substrate (silicon wafer). And a single crystal semiconductor layer 14 for element formation made of silicon single crystal via an insulating film 13 made of a silicon oxide film. In this case, the single-crystal semiconductor layer 14 is not provided on the entire surface of the base substrate 12, but is ultimately one chip (or one chip).
It is provided in such a form that it is separated at intervals for each region (element unit, well unit, circuit unit).

【0016】さて、この半導体基板11の製造方法につ
いて、以下順を追って述べる。図3は、本実施例に係る
半導体基板11の製造の工程を概略的に示している。即
ち、まず、工程P1では、貼合せ基板15(図1,図2
参照)に対する溝部形成工程が実行される。この貼合せ
基板15は、高品質な単結晶シリコン基板(シリコンウ
エハ)からなり、初期の状態で厚さ寸法が例えば600
μm程度とされている。この工程P1では、図1(a)
に示すように、貼合せ基板15の表面部に、例えばフォ
トリソグラフィ技術によるレジストパターンの形成、ド
ライエッチング等の周知の処理により、溝部16が形成
される。
Now, a method of manufacturing the semiconductor substrate 11 will be described in the following order. FIG. 3 schematically illustrates a process of manufacturing the semiconductor substrate 11 according to the present embodiment. That is, first, in the process P1, the bonded substrate 15 (see FIGS. 1 and 2)
) Is performed. The bonded substrate 15 is made of a high-quality single-crystal silicon substrate (silicon wafer) and has a thickness of, for example, 600 in an initial state.
It is about μm. In this step P1, FIG.
As shown in (1), a groove 16 is formed on the surface of the bonded substrate 15 by a known process such as formation of a resist pattern by photolithography and dry etching.

【0017】図2に誇大的に一部のみを示すように、こ
の溝部16(図2では便宜上斜線を付して示す)は、最
終的に得られる単結晶半導体層14に対応して、貼合せ
基板15の表面部を、1チップ(あるいは1素子単位,
ウェル単位,回路単位)に対応した領域毎に区画するよ
うな形態で縦横に延びて形成されている。このとき、溝
部16は、後述するイオン注入層17よりも深い深さ寸
法(例えば3μm程度)に形成され、また、この溝部1
6は、貼合せ基板15の周縁端部にて開放しないように
形成されている。
As shown exaggeratedly in FIG. 2, this groove 16 (shown with diagonal lines in FIG. 2 for convenience) is bonded to the finally obtained single crystal semiconductor layer 14. The surface of the mating substrate 15 is divided into one chip (or one element unit,
(A well unit, a circuit unit) and are formed so as to extend in the vertical and horizontal directions so as to be divided into regions corresponding to regions. At this time, the groove 16 is formed to have a depth dimension (for example, about 3 μm) deeper than the ion implantation layer 17 described later.
6 is formed so as not to be opened at the peripheral edge of the bonded substrate 15.

【0018】次の工程P2では、前記貼合せ基板15に
対するイオン注入層形成工程が実行される。この工程P
2では、図1(b)に示すように、貼合せ基板15に対
し、その表面部に例えば水素ガスをイオン化して所定の
注入エネルギーで加速して注入することが行われ、これ
にて、貼合せ基板15の所定深さ位置(例えば表面から
1μmの位置)に、注入水素イオン濃度の高い領域であ
る剥離用のイオン注入層17が形成される。
In the next step P2, an ion implantation layer forming step for the bonded substrate 15 is performed. This process P
2, as shown in FIG. 1 (b), for example, hydrogen gas is ionized and injected at a predetermined injection energy into the surface portion of the bonded substrate 15. At a predetermined depth position (for example, at a position of 1 μm from the surface) of the bonded substrate 15, an ion implantation layer 17 for separation, which is a region having a high concentration of implanted hydrogen ions, is formed.

【0019】このとき、イオン注入層17は、前記溝部
16の深さよりも浅い位置に形成され、貼合せ基板15
のうち溝部16部分を除く表層部には、シリコン単結晶
からなる薄い単結晶薄膜層15a(後に単結晶半導体層
14となる)が、そのイオン注入層17によって仕切ら
れた形態に形成されることになる。また、溝部16部分
については、溝部16の底部から所定深さ位置にイオン
注入層が存在することになる。
At this time, the ion-implanted layer 17 is formed at a position shallower than the depth of the groove 16 and
The thin single-crystal thin-film layer 15 a made of silicon single crystal (which will later become the single-crystal semiconductor layer 14) is formed in a surface layer portion excluding the groove portion 16 in a form partitioned by the ion-implanted layer 17. become. In the groove 16, the ion-implanted layer exists at a predetermined depth from the bottom of the groove 16.

【0020】尚、後述するように、この際の水素イオン
のドーズ量は、1×1015atoms/cm2 程度とされてい
る。また、図示はしていないが、このイオン注入層形成
工程は、貼合せ基板15の表面にイオン注入時の汚染を
極力防止するための酸化膜が形成された状態で実行さ
れ、その後、例えばHF水溶液による化学的エッチング
等により、その酸化膜が除去されるようになっている。
As will be described later, the dose of hydrogen ions at this time is about 1 × 10 15 atoms / cm 2. Although not shown, this ion implantation layer forming step is performed in a state where an oxide film for preventing contamination during ion implantation is formed on the surface of the bonded substrate 15 as much as possible. The oxide film is removed by chemical etching or the like using an aqueous solution.

【0021】工程P3では、上記ベース基板12に対し
て、貼合せ基板15を貼合わせる貼合せ工程が実行され
る。この工程P3では、図1(c)に示すように、ベー
ス基板12の表面には、予め絶縁膜(酸化膜)13が熱
酸化あるいはPVD,CVD等の堆積法により形成され
ている。このベース基板12に対し、貼合せ基板15が
図1(b)とは上下反転された状態つまり単結晶薄膜層
15aの表面にて接着される。
In step P3, a bonding step of bonding the bonding substrate 15 to the base substrate 12 is performed. In this step P3, as shown in FIG. 1C, an insulating film (oxide film) 13 is previously formed on the surface of the base substrate 12 by thermal oxidation or a deposition method such as PVD or CVD. The bonded substrate 15 is bonded to the base substrate 12 in a state where it is turned upside down from FIG. 1B, that is, on the surface of the single crystal thin film layer 15a.

【0022】周知のように、この貼合せに際しては、前
記ベース基板12及び貼合せ基板15の表面に対し、例
えば硫酸と過酸化水素水の4:1の混合溶液による洗浄
及び純水洗浄を順次行った後、スピン乾燥で吸着水分量
を制御して貼合わせ面を密着させる。これにより、ベー
ス基板12及び貼合せ基板15は、貼合わせ面に形成さ
れたシラノール基、及び表面に吸着した水分子の水素結
合によって接着されるのである。
As is well known, at the time of bonding, the surfaces of the base substrate 12 and the bonded substrate 15 are sequentially washed with a mixed solution of, for example, sulfuric acid and hydrogen peroxide 4: 1 and pure water. After performing, the amount of adsorbed water is controlled by spin drying to bring the bonding surfaces into close contact. As a result, the base substrate 12 and the bonded substrate 15 are bonded by a silanol group formed on the bonded surface and a hydrogen bond of a water molecule adsorbed on the surface.

【0023】これにて、図1(c)に示すように、ベー
ス基板12上に絶縁膜13を介して、単結晶薄膜層15
a、イオン注入層17及び貼合せ基板15の基部(バル
ク部分)が積層された形態に一体化される。そして、貼
合せ基板15は溝部16を有するので、前記溝部16と
ベース基板12の表面との間には、前記単結晶薄膜層1
5a及びイオン注入層17を部分的に除去した形態に中
空部18が形成されるのである。このとき、前記溝部1
6は貼合せ基板15の端部にて閉じているので、形成さ
れる中空部18は密閉状態とされるのである。
As shown in FIG. 1C, the single crystal thin film layer 15 is formed on the base substrate 12 with the insulating film 13 interposed therebetween.
a, the ion implantation layer 17 and the base portion (bulk portion) of the bonded substrate 15 are integrated in a laminated form. Since the bonded substrate 15 has the groove 16, the single crystal thin film layer 1 is provided between the groove 16 and the surface of the base substrate 12.
The hollow portion 18 is formed in a form in which 5a and the ion implantation layer 17 are partially removed. At this time, the groove 1
Since 6 is closed at the end of the bonded substrate 15, the formed hollow portion 18 is in a closed state.

【0024】次の工程P4では、ベース基板12に貼合
わされた貼合せ基板15を前記イオン注入層17にて切
離す剥離工程が実行される。この工程P4は、窒素雰囲
気あるいは酸素雰囲気での例えば400〜600℃の熱
処理により、図1(d)に示すように、貼合せ基板15
内部のイオン注入層17に欠陥が集中してこのイオン注
入層17にて割れが発生することに基づいて行われる。
In the next step P4, a peeling step of separating the bonded substrate 15 bonded to the base substrate 12 by the ion implantation layer 17 is performed. In this step P4, as shown in FIG. 1D, the bonded substrate 15 is heat-treated in a nitrogen atmosphere or an oxygen atmosphere, for example, at 400 to 600 ° C.
This is performed based on the fact that defects are concentrated in the ion implantation layer 17 inside and cracks occur in the ion implantation layer 17.

【0025】この熱処理により、ベース基板12と貼合
せ基板15との貼合わせ面にて脱水縮合反応が生じ、よ
り強固に接着されるようになる。そして、これと共に、
ベース基板12と貼合せ基板15との間に密閉状態に形
成された中空部18内の気体(空気)が熱膨脹し、その
圧力が中空部18を押し拡げる、言換えるならば、貼合
せ基板15の溝部16の底部を図1(c)で上方に押圧
して貼合せ基板15のうちのイオン注入層17よりも基
部側をベース基板12から引剥がす方向の力となって作
用するようになる。
By this heat treatment, a dehydration-condensation reaction occurs on the bonding surface between the base substrate 12 and the bonding substrate 15, so that the bonding is more firmly performed. And with this,
The gas (air) in the hollow portion 18 formed in a sealed state between the base substrate 12 and the bonded substrate 15 thermally expands, and the pressure expands the hollow portion 18, in other words, the bonded substrate 15. 1C, the bottom of the groove 16 is pressed upward in FIG. 1C, and the base of the bonded substrate 15 is peeled from the base substrate 12 with respect to the ion-implanted layer 17 to act as a force. .

【0026】このため、いわば内部から剥離を助長する
力が得られることになり、その分、イオン注入層16に
おけるイオン注入量が十分でなくとも、イオン注入層1
7での剥離が容易になされるようになる。これにて、貼
合せ基板15のイオン注入層17上に設けられていた単
結晶薄膜層15aが剥離されてベース基板12の表面側
にいわば転写された如き形態となり、ベース基板12上
に絶縁膜13を介して、単結晶半導体層14(単結晶薄
膜層15a)を有した半導体基板11が得られるのであ
る。
As a result, a force that promotes peeling can be obtained from the inside, so that even if the ion implantation amount in the ion implantation layer 16 is not sufficient, the ion implantation layer
7 can be easily performed. As a result, the single crystal thin film layer 15a provided on the ion implantation layer 17 of the bonded substrate 15 is peeled off, so that the single crystal thin film layer 15a is transferred to the front side of the base substrate 12, so that the insulating film is formed on the base substrate 12. The semiconductor substrate 11 having the single-crystal semiconductor layer 14 (single-crystal thin-film layer 15a) is obtained through the intermediary of the semiconductor substrate 11.

【0027】引続き、工程P5では、得られた半導体基
板11に対して、例えば1000℃〜1200℃の温度
にて高温アニール処理が実行される。これにて、剥離面
の結合が強化されると共に、欠陥回復等が図られるので
ある。さらに、工程P6にて、図1(e)に示すよう
に、得られた半導体基板11及び単結晶薄膜層15aが
剥離された貼合せ基板15の表面(剥離面)に対する表
面研磨が実行される。これにて、剥離面の微細な凹凸が
除去されるのである。
Subsequently, in step P5, the obtained semiconductor substrate 11 is subjected to a high-temperature annealing treatment at a temperature of, for example, 1000 ° C. to 1200 ° C. As a result, the bonding of the peeled surfaces is strengthened, and defect recovery and the like are achieved. Further, in step P6, as shown in FIG. 1E, surface polishing is performed on the surface (peeled surface) of the bonded substrate 15 from which the obtained semiconductor substrate 11 and single crystal thin film layer 15a have been peeled. . Thus, fine irregularities on the peeled surface are removed.

【0028】尚、この図1(e)に示す状態では、単結
晶半導体層14が1チップ相当領域毎に分離されてお
り、それらの間は凹状態(絶縁膜13が露出した状態)
とされているが、必要に応じて、例えばCVD法を用い
てその凹状部分を絶縁膜(酸化膜)等により埋め込むよ
うにしても良い。また、単結晶薄膜層15aが剥離され
た側の貼合せ基板15は、厚みを減少させながら次の半
導体基板11の製造に繰返し使用される。
In the state shown in FIG. 1E, the single-crystal semiconductor layer 14 is separated into regions corresponding to one chip, and a concave state is formed between them (a state in which the insulating film 13 is exposed).
However, if necessary, the concave portion may be embedded with an insulating film (oxide film) or the like by using, for example, a CVD method. Further, the bonded substrate 15 on the side from which the single crystal thin film layer 15a has been peeled off is repeatedly used for manufacturing the next semiconductor substrate 11 while reducing its thickness.

【0029】このように本実施例によれば、貼合せ基板
15に溝部16を設けた上でベース基板12と貼合わせ
ることによって、中空部18を形成するようにし、剥離
工程の熱処理時にその中空部18内の空気の熱膨脹を、
剥離を助長する力として利用するようにした。従って、
イオン注入層17におけるイオン注入量が十分でなくと
も、イオン注入層17での剥離が容易になされるように
なる。
As described above, according to the present embodiment, the hollow portion 18 is formed by forming the groove 16 in the bonded substrate 15 and then bonding the base substrate 12 to the groove, so that the hollow portion 18 is formed during the heat treatment in the peeling step. The thermal expansion of the air in section 18
It was used as a force to promote peeling. Therefore,
Even if the ion implantation amount in the ion implantation layer 17 is not sufficient, the separation in the ion implantation layer 17 can be easily performed.

【0030】この結果、本実施例によれば、イオン注入
を従来のものと比べて低ドーズ量で済ませながらも剥離
を可能とし、イオン注入層17の形成工程に要する時間
の大幅な短縮化を図ることができるという優れた実用的
効果を得ることができる。ちなみに、本実施例では、水
素イオンのドーズ量を、従来の1×1016atoms/cm2
程度から、1×1015atoms/cm2 程度と、一桁下げる
ことができ、イオン注入に要する時間を従来の半分以下
に短縮化することができたのである。
As a result, according to the present embodiment, the ion implantation can be performed at a lower dose than that of the conventional ion implantation, but the separation can be performed, and the time required for forming the ion implantation layer 17 can be greatly reduced. An excellent practical effect that it can be achieved. Incidentally, in this embodiment, the dose amount of hydrogen ions is set to 1 × 10 16 atoms / cm 2
Thus, the time required for ion implantation can be reduced to less than half that of the conventional case, by an order of magnitude of about 1 × 10 15 atoms / cm 2.

【0031】図4は、本発明の第2の実施例(請求項3
に対応)を示すものである。この実施例が上記第1の実
施例と異なる点は、貼合せ基板15に対する、溝部形成
工程と、イオン注入層形成工程との実行順序を前後逆に
したところにある。即ち、図4(a)に示すように、ま
ず貼合せ基板15に対するイオン注入層形成工程が実行
され、貼合せ基板15の所定深さ位置に剥離用のイオン
注入層17が形成される。
FIG. 4 shows a second embodiment of the present invention.
). This embodiment differs from the first embodiment in that the order of execution of the groove forming step and the ion implantation layer forming step on the bonded substrate 15 is reversed. That is, as shown in FIG. 4A, first, an ion implantation layer forming step is performed on the bonded substrate 15, and an ion-implanted layer 17 for separation is formed at a predetermined depth position of the bonded substrate 15.

【0032】次いで、図4(b)に示すように、溝部形
成工程が実行されて、貼合せ基板15の表面部に、イオ
ン注入層17よりも深く、且つ貼合せ基板15の端部に
て閉塞した溝部16が形成されるのである。その後、上
記第1の実施例と同様に、ベース基板12との貼合せ
(図4(c))、剥離(図4(d))、表面研磨(図4
(e))等の工程が実行され、半導体基板11が得られ
るのである。
Next, as shown in FIG. 4B, a groove forming step is performed, and a groove is formed on the surface of the bonded substrate 15 at a depth deeper than the ion-implanted layer 17 and at the end of the bonded substrate 15. The closed groove 16 is formed. After that, similarly to the first embodiment, bonding to the base substrate 12 (FIG. 4C), peeling (FIG. 4D), and surface polishing (FIG. 4).
Steps such as (e)) are performed, and the semiconductor substrate 11 is obtained.

【0033】このような実施例によれば、上記第1の実
施例と同様に、貼合せ基板15に溝部16を設けた上で
ベース基板12と貼合わせることによって、密閉された
中空部18が形成されるので、中空部18内の空気の熱
膨脹を、剥離を助長する力として利用することができ、
その結果、イオン注入を低ドーズ量で済ませながらも剥
離を可能とし、イオン注入層17の形成工程に要する時
間の大幅な短縮化を図ることができる。また、本実施例
では、剥離された貼合せ基板15には、溝部16の底部
の下方にイオン注入層が残っていないので(図4(d)
参照)、剥離された貼合せ基板15を表面研磨後に再使
用するにあたって、表面部から取除くべき層の厚みを小
さく済ませることができるといった利点も得ることがで
きる。
According to such an embodiment, similarly to the first embodiment, the hermetically sealed hollow portion 18 is formed by providing the groove 16 in the bonding substrate 15 and bonding the groove to the base substrate 12. Since it is formed, the thermal expansion of the air in the hollow portion 18 can be used as a force that promotes separation.
As a result, separation can be performed while ion implantation is performed at a low dose, and the time required for forming the ion-implanted layer 17 can be significantly reduced. Further, in the present embodiment, no ion-implanted layer remains below the bottom of the groove 16 in the peeled bonded substrate 15 (FIG. 4D).
In addition, when the peeled bonded substrate 15 is reused after polishing the surface, there is an advantage that the thickness of the layer to be removed from the surface portion can be reduced.

【0034】その他、本発明は上記した各実施例に限定
されるものではなく、例えばベース基板の材質としては
セラミック基板や石英基板などであっても良い。また、
イオン注入に用いるガスとしては、水素ガス以外にも、
ヘリウム,ネオン等の希ガスや、フッ素ガス,塩素ガス
など種々のものが採用でき、この場合、用いたイオンの
種類等によって適切なドーズ量,剥離温度等が異なって
くる。更には、ドーズ量の数値や各部の厚み寸法等も一
例に過ぎない等、要旨を逸脱しない範囲内で適宜変更し
て実施し得るものである。
In addition, the present invention is not limited to the above-described embodiments. For example, the material of the base substrate may be a ceramic substrate or a quartz substrate. Also,
As a gas used for ion implantation, besides hydrogen gas,
Various gases such as a rare gas such as helium and neon, fluorine gas, and chlorine gas can be employed. In this case, an appropriate dose amount, peeling temperature, and the like differ depending on the type of ions used. Furthermore, the dose amount, the thickness of each part, and the like are merely examples, and the present invention can be implemented with appropriate changes without departing from the scope of the invention.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施例を示すもので、製造工程
における様子を順に示す模式的な縦断面図
FIG. 1 shows a first embodiment of the present invention, and is a schematic longitudinal sectional view showing states in a manufacturing process in order.

【図2】貼合せ基板に形成された溝部の様子を模式的に
示す平面図
FIG. 2 is a plan view schematically showing a state of a groove formed in a bonded substrate.

【図3】半導体基板の製造工程を概略的に示す図FIG. 3 is a diagram schematically showing a manufacturing process of a semiconductor substrate.

【図4】本発明の第2の実施例を示す図1相当図FIG. 4 is a view corresponding to FIG. 1, showing a second embodiment of the present invention;

【図5】従来例を示す図1相当図FIG. 5 is a diagram corresponding to FIG. 1 showing a conventional example.

【符号の説明】[Explanation of symbols]

図面中、11は半導体基板、12はベース基板、13は
絶縁膜、14は単結晶半導体層、15は貼合せ基板、1
5aは単結晶薄膜層、16は溝部、17はイオン注入
層、18は中空部を示す。
In the drawings, 11 is a semiconductor substrate, 12 is a base substrate, 13 is an insulating film, 14 is a single crystal semiconductor layer, 15 is a bonded substrate, 1
5a is a single crystal thin film layer, 16 is a groove, 17 is an ion implanted layer, and 18 is a hollow part.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 ベース基板(12)上に、絶縁膜(1
3)を介して素子形成用の単結晶半導体層(14)を設
けてなる半導体基板(11)を製造するための方法であ
って、 単結晶半導体からなる貼合せ基板(15)の表面部の所
定深さにイオン注入を行うことにより、該貼合せ基板
(15)の表層部に単結晶半導体層(14)となるべき
単結晶薄膜層(15a)を確保した状態に剥離用のイオ
ン注入層(17)を形成するイオン注入層形成工程(P
2)と、 前記ベース基板(12)に対し、前記単結晶薄膜層(1
5a)が形成された貼合せ基板(15)をその単結晶薄
膜層(15a)の表面にて絶縁膜(13)を介して貼合
わせる貼合せ工程(P3)と、 前記ベース基板(12)上に貼合わされた貼合せ基板
(15)を熱処理により前記イオン注入層(17)にて
切離す剥離工程(P4)とを含むと共に、 前記ベース基板(12)と貼合せ基板(15)との貼合
せ状態において、それらベース基板(12)と貼合せ基
板(15)との間に、密閉状態の中空部(18)が前記
単結晶薄膜層(15a)及びイオン注入層(17)を部
分的に除去した形態に形成されていることを特徴とする
半導体基板の製造方法。
An insulating film (1) is formed on a base substrate (12).
3) A method for producing a semiconductor substrate (11) provided with a single crystal semiconductor layer (14) for element formation via 3), wherein a surface portion of a bonded substrate (15) made of a single crystal semiconductor is By performing ion implantation to a predetermined depth, an ion-implanted layer for peeling is obtained in a state where a single-crystal thin-film layer (15a) to be a single-crystal semiconductor layer (14) is secured in a surface layer portion of the bonded substrate (15). Ion implantation layer forming step (P) for forming (17)
2) and the single-crystal thin film layer (1) with respect to the base substrate (12).
A laminating step (P3) of laminating the laminated substrate (15) on which the 5a) is formed on the surface of the single crystal thin film layer (15a) via an insulating film (13), and on the base substrate (12). A peeling step (P4) of separating the bonded substrate (15) bonded to the above at the ion implantation layer (17) by heat treatment, and bonding the base substrate (12) and the bonded substrate (15). In the bonding state, a hermetically sealed hollow portion (18) partially connects the single crystal thin film layer (15a) and the ion implantation layer (17) between the base substrate (12) and the bonding substrate (15). A method for manufacturing a semiconductor substrate, wherein the semiconductor substrate is formed in a removed form.
【請求項2】 前記イオン注入層形成工程(P2)の前
に、前記貼合せ基板(15)の表面部に、前記中空部
(18)となる溝部(16)を、前記イオン注入の深さ
より深く且つ貼合せ基板(15)の周縁端部にて開放し
ないように形成する溝部形成工程(P1)が実行される
ことを特徴とする請求項1記載の半導体基板の製造方
法。
2. Prior to the step of forming an ion-implanted layer (P2), a groove (16) serving as the hollow portion (18) is formed on the surface of the bonded substrate (15) in accordance with the depth of the ion-implantation. 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein a groove forming step (P1) of forming a groove deep and not to be opened at a peripheral edge of the bonded substrate (15) is performed.
【請求項3】 前記イオン注入層形成工程(P2)の後
に、前記貼合せ基板(15)の表面部に、前記中空部
(18)となる溝部(16)を、前記イオン注入の深さ
より深く且つ貼合せ基板(15)の周縁端部にて開放し
ないように形成する溝部形成工程が実行されることを特
徴とする請求項1記載の半導体基板の製造方法。
3. After the step (P2) of forming an ion-implanted layer, a groove (16) serving as the hollow portion (18) is formed deeper than the depth of the ion-implanted in the surface of the bonded substrate (15). 2. The method of manufacturing a semiconductor substrate according to claim 1, wherein a step of forming a groove is formed so that the peripheral edge of the bonded substrate is not opened.
【請求項4】 前記溝部(16)は、前記ベース基板
(12)上に設けられる素子形成用の単結晶半導体層
(14)を1素子の単位,ウェルの単位,回路の単位あ
るいは1チップ毎に区画する形態に形成されることを特
徴とする請求項2又は3記載の半導体基板の製造方法。
4. The groove portion (16) is formed by forming a single crystal semiconductor layer (14) for element formation provided on the base substrate (12) in units of one element, unit of well, unit of circuit, or unit of one chip. 4. The method for manufacturing a semiconductor substrate according to claim 2, wherein the semiconductor substrate is formed in a form of partitioning the substrate.
JP19850197A 1997-07-24 1997-07-24 Manufacture of semiconductor substrate Pending JPH1145862A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19850197A JPH1145862A (en) 1997-07-24 1997-07-24 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19850197A JPH1145862A (en) 1997-07-24 1997-07-24 Manufacture of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPH1145862A true JPH1145862A (en) 1999-02-16

Family

ID=16392190

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH1145862A (en)

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