JP2011086922A - Manufacturing method of soi substrate, and the soi substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress roughness of a surface of a semiconductor layer, when manufacturing an SOI(spin-on-insulator) substrate by bonding a base substrate and a bond substrate together, while effectively utilizing a region where the bonding strength is reduced. <P>SOLUTION: The bond substrate is irradiated with ions to form an embrittled region on the bonding substrate; an opening portion is made in the surface of the bonding substrate or the base substrate; the bonding substrate and the base substrate are bonded together with an insulating layer between; and here bonding is made to progress from one end of four corners of the bond substrate, and the opening part is arranged at a region of the other end facing the one end, thereby forming it into a region where the bonding substrate and the base substrate is not bonded together and whose outer periphery is closed by the bond substrate and the base substrate. By subjecting the substrate to heat treatment, the bonding substrate is separated in the embrittled region, and a semiconductor layer is formed on the base substrate. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a method for manufacturing an SOI (Silicon on Insulator) substrate, an SOI substrate, a method for manufacturing a semiconductor device using the substrate, and the semiconductor device.

In recent years, it has been studied to use an SOI (Silicon on Insulator) substrate having a thin single crystal semiconductor layer on an insulating surface instead of a bulk silicon wafer. Since the parasitic capacitance formed by the drain and the substrate of the transistor can be reduced by using the SOI substrate, the SOI substrate has attracted much attention as improving the performance of the semiconductor integrated circuit.

As one of methods for manufacturing an SOI substrate, a Smart Cut (registered trademark) method is known (for example, see Patent Document 1). An outline of a method for manufacturing an SOI substrate by the smart cut method will be described below. First, hydrogen ions are implanted into a silicon wafer using an ion implantation method to form a microbubble layer at a predetermined depth from the surface. Next, the silicon wafer implanted with hydrogen ions is bonded to another silicon wafer through the silicon oxide film. After that, by performing heat treatment, a part of the silicon wafer into which hydrogen ions are implanted is separated into a thin film shape with the microbubble layer as a boundary, and a single crystal silicon film is formed on another bonded silicon wafer.

Furthermore, a method of forming a single crystal silicon layer on a base substrate made of glass using a smart cut method has been proposed (for example, see Patent Document 2). Since the glass substrate can be easily increased in area and cheaper than a silicon wafer, it is mainly used for manufacturing a liquid crystal display device or the like. By using a glass substrate as a base substrate, it is possible to manufacture a large-area and inexpensive SOI substrate.

Japanese Patent Laid-Open No. 05-211128 JP 2005-252244 A

When a single crystal silicon layer is formed on a glass substrate by using the smart cut method or the like, the surface roughness of the silicon layer is larger than when an SOI substrate is manufactured by bonding silicon wafers together. Tend to be. Such surface roughness induces various defects in later processes, and as a result, causes a decrease in the yield of semiconductor elements and semiconductor devices.

In view of the above problems, in one embodiment of the disclosed invention, a semiconductor layer (eg, a single crystal silicon layer) in which an SOI substrate is manufactured by bonding a base substrate (eg, a glass substrate) and a bond substrate (eg, a single crystal silicon substrate) to each other ) To suppress surface roughness. Another object of one embodiment of the disclosed invention is to provide a semiconductor device with high yield by suppressing the roughness.

When a single crystal silicon layer is formed on a glass substrate using a smart cut method or the like, the bonding between the glass substrate and a silicon substrate having a quadrangular shape cut out from the silicon wafer is performed by, for example, the glass substrate and the silicon substrate. Is applied by applying an external force or its own weight to a part of the peripheral part of the silicon substrate or the central part of the silicon substrate, and bonding is performed from the bonded region to the entire surface of the substrate. In such a case, it has been experimentally confirmed that a region (gap) where the glass substrate and the silicon substrate are not bonded is formed by confining minute air in the terminal region of the bonding of the silicon substrate.

Such a region where bonding is not properly performed is a case where a part of the silicon substrate is separated from a region where hydrogen is added to the glass substrate and the single crystal silicon layer is transferred and the transfer is not performed sufficiently. It becomes a useless area | region (dead space) which cannot be utilized effectively as a crystalline silicon layer.

In view of the above problems, in one embodiment of the disclosed invention, a region where bonding is not appropriately performed when an SOI substrate is manufactured by bonding a base substrate (eg, a glass substrate) and a bond substrate (eg, a single crystal silicon substrate) to each other Another object is to effectively suppress the roughness of the surface of the semiconductor layer by effectively using. Another object of one embodiment of the disclosed invention is to provide a semiconductor device with high yield by suppressing the roughness.

In one embodiment of the disclosed invention, an opening (also referred to as a “concave portion”) is formed in at least one surface of a bond substrate or a base substrate in manufacturing an SOI substrate by bonding. Then, when bonding the bond substrate and the base substrate, the bonding is advanced from the end of the bond substrate, and the opening is disposed in the region of the other end facing the end where the bonding is started. A region in which the substrate and the base substrate are not attached to each other and the outer periphery is closed by the base substrate and the bond substrate is formed.

When a substrate having at least a square is used as the bond substrate, the bonding is advanced from any one of the four corners, and the non-bonded region formed by the opening at the opposite corner is closed. It is desirable to form a region.

In one embodiment of the disclosed invention, a bond substrate is irradiated with ions to form an embrittled region in the bond substrate, an opening is formed in the surface of the bond substrate or the base substrate, and an insulating layer is interposed therebetween. When the base substrate and the base substrate are bonded together, the base substrate and the bond substrate are bonded to each other by moving the bonding from a part of the periphery of the bond substrate and arranging an opening in the vicinity of the region where the bonding ends. A non-matching region and a region whose outer periphery is closed by the base substrate and the bond substrate are formed, and heat treatment is performed to separate the bond substrate in the embrittled region, and a semiconductor layer is formed on the base substrate. This is a method for manufacturing an SOI substrate to be formed.

In addition, the said method can also be paraphrased as follows. That is, the bond substrate is irradiated with ions to form an embrittled region in the bond substrate, an opening is formed on the surface of the bond substrate or the base substrate, and the bond substrate and the base substrate are attached with an insulating layer interposed therebetween. At the time of alignment, the base substrate and the bond substrate are bonded by advancing the bonding from one corner of the bond substrate having a substantially rectangular shape and arranging an opening at the other corner opposite the corner where the bonding is started. In this method, an SOI substrate is formed by forming a region whose outer periphery is closed by heat treatment and separating the bond substrate in the embrittlement region to form a semiconductor layer over the base substrate. Note that the quadrangular shape includes those having four or more corners due to notches or the like, or those having corners with curvature.

Moreover, the said method can also be paraphrased as follows. That is, when the bond substrate is irradiated with ions to form an embrittled region in the bond substrate and the bond substrate and the base substrate are bonded to each other with the insulating layer interposed therebetween, a partial region of the periphery of the bond substrate The gap is formed by forming a void portion sandwiched between the base substrate and the bond substrate by proceeding with the bonding, and arranging an intentionally formed opening in the vicinity of the region where the bonding is completed, and performing a heat treatment. This is a method for manufacturing an SOI substrate, in which a crack is generated in an embrittled region starting from a region where the film is formed, a bond substrate is separated, and a semiconductor layer is formed over a base substrate.

In the above, it is preferable to promote separation of the bond substrate by applying heat treatment to generate stress in the vicinity of the closed region where the bond substrate and the base substrate are not bonded to each other by the opening.

In the above manufacturing method, when an opening is formed on the surface of the bond substrate, the opening may be formed in the bond substrate, or a thermal oxide film, silicon oxide, silicon nitride, or oxynitride formed on the bond substrate. An insulating layer made of silicon, silicon nitride oxide, or a laminated film selected from these may be formed, and the opening may be formed only in the insulating layer. Alternatively, an opening may be formed in the bond substrate and the insulating layer through the insulating layer. Alternatively, an opening may be formed in the bond substrate, and an insulating layer reflecting the shape of the opening may be formed over the bond substrate.

Alternatively, the opening may be provided on the surface of the base substrate. For example, an opening may be formed in the base substrate, or an insulating layer made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or a laminated film selected from these is formed on the base substrate, An opening may be formed only in the insulating layer, or an opening may be formed in the base substrate and the insulating layer through the insulating layer. Alternatively, an opening may be formed in the base substrate, and an insulating layer reflecting the shape of the opening may be formed thereon.

In one embodiment of the disclosed invention, an insulating layer is formed over a plurality of bond substrates, ions are irradiated to the plurality of bond substrates to form embrittled regions in the plurality of bond substrates, and nitrogen is formed over the base substrate. When forming a containing layer, forming a plurality of openings on the surface of the base substrate on which the nitrogen-containing layer is formed, and bonding the plurality of bond substrates and the base substrate with the insulating layer and the nitrogen-containing layer interposed therebetween In addition, the base substrate and the plurality of bonds are bonded by advancing the bonding from one corner of each of the plurality of bond substrates, and disposing one of the plurality of openings in each of the other corners facing the corner. Form a region that is not bonded to the substrate and whose outer periphery is closed by the base substrate and the plurality of bond substrates, and heat-treat them to separate the plurality of bond substrates in the embrittled region Te is a method for manufacturing an SOI substrate forming a plurality of semiconductor layers on the base substrate.

In the above method, a plurality of openings may be formed on the surface of the base substrate, and a nitrogen-containing layer may be formed on the base substrate on which the plurality of openings are formed.

When using a large glass substrate as the base substrate and bonding a plurality of bond substrates to the glass substrate, each bond substrate is formed by forming an opening in the glass substrate which is a bonding termination region of the plurality of bond substrates defined in advance. Since there is no need to form an opening every time, the number of steps can be omitted.

Alternatively, an opening may be formed in both the bond substrate and the glass substrate. The position of the opening formed on both sides can be used as an alignment marker. For example, it can have a role as a marker by performing bonding so that the openings overlap each other.

Note that in this specification and the like, “bond substrate” may include a substrate having an insulating layer formed on an upper surface, and “base substrate” includes a substrate having an insulating layer formed on an upper surface. May be.

In addition, when the bond substrate and the base substrate are bonded to each other, it is desirable to arrange an opening in a region overlapping with a void formed in the bonding termination region or a region near the void. In addition, it is desirable to form the opening portion closer to the center of the void substrate than the position where the void is expected to be formed. This is because by providing the opening in the vicinity of the gap generated without forming the opening, the gap can be induced in the opening and the disappearance of the gap can be induced. In the case where the opening is arranged so as to overlap with a region where the formation of the void is expected, the air generated in the void can be confined in the opening and the internal stress in the opening can be increased. As a result, when the semiconductor layer is separated from the embrittlement region by heat treatment, separation can be easily caused by the pressure of the compressed air confined in the opening.

In consideration of the size and arrangement of the gap formed in the bonding termination region, the diameter of the opening is desirably 50 μm or more and 2 mm or less, and preferably 200 μm or more and 1 mm or less. The area of the opening, 0.001 mm ² or more 4 mm ² or less, preferably 0.03 mm ² or more 0.8 mm ² or less.

On the other hand, considering the suppression of surface roughness, the area of the opening is desirably 1 mm ² or more. More desirably, it is 25 mm ² or more. Thereby, the roughness of the surface of the formed semiconductor layer can be effectively suppressed.

The semiconductor layer is preferably subjected to laser light irradiation treatment. In addition, it is desirable that the heat treatment temperature be 500 ° C. or lower. Alternatively, the heat treatment temperature is set to 500 ° C. or lower, the bond substrate is separated in the embrittled region, and subsequently heat treatment is performed at 500 ° C. to 800 ° C. to reduce the concentration of hydrogen remaining in the semiconductor layer. Good.

By using the above manufacturing method, an SOI substrate in which the number density of defects in the semiconductor layer (in particular, defects having a diameter of 1 μm or more) is 5 pieces / cm ² or less (for example, 1 piece / cm ² or less) is provided. it can. In addition, a semiconductor device can be manufactured and provided using the above SOI substrate.

In general, an “SOI substrate” refers to a semiconductor substrate having a structure in which a silicon semiconductor layer is provided on an insulating surface. In this specification and the like, a structure in which a semiconductor layer made of a material other than silicon is provided on an insulating surface. It is used as a concept including the semiconductor substrate. That is, the semiconductor layer included in the “SOI substrate” is not limited to the silicon semiconductor layer. In this specification and the like, a semiconductor substrate refers not only to a substrate made of only a semiconductor material but also to all substrates containing a semiconductor material. That is, in this specification and the like, the “SOI substrate” is also widely included in the semiconductor substrate.

Note that in this specification and the like, a single crystal refers to a crystal in which the direction of the crystal axis is the same in any part of the sample when attention is paid to a crystal axis. That is, even if crystal defects, dangling bonds, and the like are included, those having the same crystal axis direction as described above are treated as single crystals.

In this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, a display device and an integrated circuit are included in a semiconductor device. In this specification and the like, a display device includes a light-emitting display device, a liquid crystal display device, and a display device using an electrophoretic element. The light-emitting display device includes a light-emitting element, and the liquid crystal display device includes a liquid crystal element. The light-emitting element includes, in its category, an element whose luminance is controlled by current or voltage, and specifically includes an inorganic EL (Electro Luminescence), an organic EL, and the like.

In one embodiment of the disclosed invention, an opening is formed in a part (peripheral part) of the surfaces related to bonding to form a region where gas is confined. Thereby, an SOI substrate in which surface roughness of the semiconductor layer is suppressed can be provided. Alternatively, the yield of a semiconductor device using the same can be improved.

In one embodiment of the disclosed invention, an opening is formed in a part (peripheral portion) of a surface to be bonded, and bonding is performed from an end portion of the bond substrate when the bond substrate and the base substrate are bonded to each other. An opening is arranged in the region of the other end that faces the end that has been advanced and pasted. Accordingly, it is possible to provide an SOI substrate in which surface roughness of the semiconductor layer is suppressed by effectively using a dead space caused by a gap formed by confining minute air in the bonding termination region. Therefore, it is not necessary to separately provide an opening for preventing surface roughness on the peripheral edge of the bond substrate other than the dead space.

In one embodiment of the disclosed invention, the generation position of the opening suppresses or eliminates the generation of a void in which minute air that is formed without forming the opening in the region where bonding is completed is confined. Can do.

FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a plan view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a plan view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a plan view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a plan view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing an SOI substrate. FIG. 10 is a plan view illustrating an example of a method for manufacturing an SOI substrate. It is sectional drawing which shows the example of an opening part. It is a top view which shows the example of the shape of an opening part. It is a figure which shows the mode of isolation | separation of a semiconductor layer. It is a top view which shows the example of the shape of an opening part. It is a figure which shows the mode of stress. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device (transistor). FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device (transistor). 2A and 2B are a plan view and a cross-sectional view of a semiconductor device (transistor). It is a figure which shows the mode of the surface of a silicon layer. It is a figure which shows the mode of the surface of a silicon layer. It is a figure which shows the mode of the surface of a silicon layer. It is a figure which shows the relationship between the diameter of the area | region closed, and the number of defect | deletions. It is a figure which shows the comparison result of the roughness of the surface. It is a figure which shows the comparison result of the roughness of the surface. It is a figure which shows the difference in the number of the defect | deletion by the presence or absence of the area | region closed.

Hereinafter, embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the description of the embodiments described below, and it is obvious to those skilled in the art that modes and details can be variously changed without departing from the spirit of the invention disclosed in this specification and the like. . In addition, structures according to different embodiments can be implemented in appropriate combination. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, an example of a method for manufacturing an SOI substrate will be described with reference to drawings. Specifically, the case of manufacturing an SOI substrate in which a single crystal semiconductor layer is provided over a base substrate will be described.

First, a base substrate 100 and a bond substrate are prepared. Here, the case where the single crystal semiconductor substrate 110 is used as a bond substrate is described (see FIGS. 1A and 1B).

As the base substrate 100, a substrate made of an insulator can be used. Specific examples include various glass substrates, quartz substrates, ceramic substrates, and sapphire substrates used in the electronics industry such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass. In the ceramic substrate, for example, a ceramic substrate having silicon nitride (Si _x N _y ) and Al ₂ O ₃ as main components and a thermal expansion coefficient close to that of silicon can be used. In the above glass substrate, by containing a larger amount of barium oxide (BaO) than boron oxide (B 2 _{O 3),} more practical heat-resistant glass can be obtained. For this reason, when heat resistance is required for the glass substrate, a glass substrate containing more BaO than B ₂ O ₃ may be used. Note that in this embodiment, the case where a glass substrate is used as the base substrate 100 is described. By using an inexpensive glass substrate that can have a large area as the base substrate 100, cost reduction can be achieved. Further, as the base substrate 100, it is desirable to use a substrate having a thermal expansion coefficient different from that of the bond substrate by 10% or more.

Alternatively, a semiconductor substrate such as a single crystal silicon substrate or a single crystal germanium substrate may be used as the base substrate 100. In the case where a semiconductor substrate is used as the base substrate 100, the temperature condition of the heat treatment is relaxed as compared with the case where a glass substrate or the like is used, so that it is easy to obtain a high-quality SOI substrate. Here, a solar cell grade silicon (SOG-Si: Solar Grade Silicon) substrate or the like may be used as the semiconductor substrate. A polycrystalline semiconductor substrate may be used. In the case of using solar cell grade silicon or a polycrystalline semiconductor substrate, the manufacturing cost can be suppressed as compared with the case of using a single crystal silicon substrate or the like.

Note that one embodiment of the disclosed invention suppresses surface roughness of a semiconductor layer caused by a difference in material or the like of a substrate related to bonding, and therefore, when a material or the like of a substrate related to bonding is different. Although effective, even when substrates using the same material or the like are bonded together, a sufficient effect can be obtained in terms of suppressing surface roughness.

The surface of the base substrate 100 is preferably cleaned in advance. Specifically, hydrochloric acid / hydrogen peroxide (HPM), sulfuric acid / hydrogen peroxide (SPM), ammonia / hydrogen peroxide (APM), hydrofluoric acid / hydrogen peroxide (FPM), dilute hydrofluoric acid (DHF), or the like is used for the base substrate 100. And wash. Moreover, you may use an ultrasonic wave together during the said washing | cleaning. Moreover, you may use together with the ultrasonic cleaning using carbonated water, ozone water, or hydrogenated water. By performing such a cleaning process, improvement in flatness of the surface of the base substrate 100, removal of abrasive particles remaining on the surface of the base substrate 100, and the like are realized.

As the single crystal semiconductor substrate 110, for example, a single crystal semiconductor substrate made of a Group 14 element such as a single crystal silicon substrate, a single crystal germanium substrate, or a single crystal silicon germanium substrate can be used. A compound semiconductor substrate such as gallium arsenide or indium phosphide can also be used. As a commercially available silicon substrate, a circular substrate having a diameter of 5 inches (125 mm), a diameter of 6 inches (150 mm), a diameter of 8 inches (200 mm), a diameter of 12 inches (300 mm), and a diameter of 16 inches (400 mm) is typical. is there. Note that the shape of the single crystal semiconductor substrate 110 is not limited to a circle, and for example, the single crystal semiconductor substrate 110 can be processed into a rectangle or the like. The single crystal semiconductor substrate 110 can be manufactured by a CZ method or an FZ (floating zone) method.

From the viewpoint of contaminant removal, single crystal semiconductors using sulfuric acid / hydrogen peroxide (SPM), ammonia / hydrogen peroxide (APM), hydrochloric acid / hydrogen peroxide (HPM), hydrofluoric acid / hydrogen peroxide (FPM), dilute hydrofluoric acid (DHF), etc. It is preferable to clean the surface of the substrate 110 in advance. Further, cleaning may be performed by alternately discharging dilute hydrofluoric acid and ozone water.

Note that although this embodiment describes the case where a single crystal semiconductor substrate is used as a bond substrate, one embodiment of the disclosed invention is not construed as being limited thereto. For example, a polycrystalline semiconductor substrate or the like may be used as the bond substrate.

Next, an embrittlement region 112 is formed at a predetermined depth from the surface of the single crystal semiconductor substrate 110, and then the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other with the insulating layer 114 interposed therebetween (FIG. 1C ), See FIG.

In this embodiment, an opening 140 (also referred to as a “concave portion” or a “groove”) is formed in a region corresponding to the peripheral portion of the single crystal semiconductor substrate 110 on the surface of the insulating layer 114 (see FIG. 1 (C)).

Next, the base substrate 100 and the single crystal semiconductor substrate 110 are overlaid, and stress is applied to a region indicated by a white arrow so that the bonding proceeds from a part of the outer peripheral portion of the single crystal semiconductor substrate 110. A part of the semiconductor substrate 110 is bonded and bonded (FIG. 1D).

At this time, it is desirable to arrange the region in which the opening 140 is formed so as to be farthest from the initial region in which the bonding proceeds. In other words, it is desirable to advance the bonding between the base substrate 100 and the single crystal semiconductor substrate 110 so that a region where an opening is formed is disposed in the vicinity of the region where the bonding is completed.

It has been experimentally confirmed that, in the region where the bonding is completed, a region (gap) where the base substrate 100 and the single crystal semiconductor substrate 110 are not bonded is formed by partially confining minute air. . The region where such voids are formed is a region that does not contribute to the bonding or the bonding strength is reduced, and becomes a dead space.

Therefore, it is closed by the opening by placing an intentionally formed opening in the vicinity of the area where the void is expected to be formed or in the vicinity of the area where the void is expected to be formed. It is desirable to form a region.

In addition, in this way, a non-bonded region that is formed by intentionally disposing an opening on a part of the surface to be bonded, and a closed region (hereinafter referred to as “an opening portion is formed. By forming the “closed region”), it is possible to effectively provide an opportunity for separation, so that surface roughness of the formed single crystal semiconductor layer can be suppressed.

In addition, since a region that does not contribute to bonding or has reduced bonding strength can be used effectively, an opening for suppressing surface roughness of the semiconductor layer is separately formed in a region that can be used as an SOI layer. You do n’t have to.

Conventionally, the gap formed at the terminal end of the bonding seems to be similar to the closed region formed by forming the opening in one embodiment of the present invention. It has been found that even if there are voids formed without providing openings in the substrate, surface roughness of the semiconductor layer cannot be effectively suppressed even if a part of the bond substrate is separated by heat treatment. Therefore, it is an effective configuration in one embodiment of this embodiment to form a closed region formed by the arrangement of the openings.

Here, the “closed area formed by the arrangement of the opening” means that the “outer periphery of the non-bonded area” formed by the boundary between the non-bonded area and the bonded area is closed. Means. In addition, the “closed region formed by the arrangement of the openings” indicates a two-dimensionally closed state and does not need to be three-dimensionally closed. By forming such a “closed region formed by the arrangement of the openings”, it is possible to suppress the roughness of the semiconductor surface after separation.

Note that in this embodiment, the opening 140 is formed in the insulating layer 114; however, one embodiment of the disclosed invention is not limited to this. In one embodiment of the disclosed invention, it is possible to suppress surface roughness of a semiconductor layer by forming a region closed by an opening intentionally formed in a substrate (for example, a region in which a gas is confined). Therefore, as long as the technical idea can be realized, it is not necessary to specifically limit the specific configuration and aspect.

As a method for manufacturing the opening, there are patterning after the insulating layer 114 is formed, marking by laser light irradiation, marking using a glass pen, and the like. In addition, when giving an identification code to a substrate (or a semiconductor device), there are cases where printing is performed using a laser marker. By using this, the closed region is formed, thereby reducing the manufacturing cost. Since a semiconductor layer in which surface roughness is suppressed without increasing can be obtained, it is preferable.

In consideration of the size and arrangement of the gap formed in the termination region of the bonding, the diameter of the opening should be φ50 μm or more and φ2 mm or less, preferably φ200 μm or more and φ1 mm or less in order to effectively use the dead space. Is desirable. The area of the opening, 0.001 mm ² or more 4 mm ² or less, preferably 0.03 mm ² or more 0.8 mm ² or less.

On the other hand, considering the suppression of surface roughness, the area of the opening is desirably 1 mm ² or more. More desirably, it is 25 mm ² or more. Thereby, the roughness of the surface of the formed semiconductor layer can be effectively suppressed.

Note that in this embodiment, the opening is provided in a corner portion of the single crystal semiconductor substrate which is a region corresponding to the peripheral portion of the single crystal semiconductor substrate. Then, the base substrate and the single crystal semiconductor substrate 110 are overlapped with each other, and one end of the base substrate is bonded to advance the bonding between the base substrate 100 and the single crystal semiconductor substrate 110, thereby performing the bonding. At the time of bonding, an opening is arranged in the vicinity of the region where the bonding is completed. Thereby, the surface roughness of the semiconductor layer can be effectively suppressed. Furthermore, by arranging an opening at the end of bonding, it is not necessary to separately form an opening for suppressing surface roughness in addition to a region where a conventional gap is formed, so that the dead space is effectively used. be able to.

The embrittlement region 112 formed at a predetermined depth from the surface of the single crystal semiconductor substrate 110 can be formed by irradiating the single crystal semiconductor substrate 110 with ions such as hydrogen having kinetic energy.

The depth of the region where the embrittlement region 112 is formed can be adjusted by ion kinetic energy, mass and charge, ion incident angle, and the like. In addition, the embrittlement region 112 is formed in a region having a depth substantially equal to the average penetration depth of ions. Therefore, the thickness of the single crystal semiconductor layer separated from the single crystal semiconductor substrate 110 can be adjusted by the depth to which ions are added. For example, the average penetration depth may be adjusted so that the thickness of the single crystal semiconductor layer is 10 nm to 1000 nm, preferably 50 nm to 200 nm.

The ion irradiation treatment can be performed using an ion doping apparatus or an ion implantation apparatus. As a typical example of an ion doping apparatus, there is a non-mass separation type apparatus that irradiates an object to be processed with all ion species generated by plasma excitation of a process gas. In this apparatus, the object to be processed is irradiated without mass separation of ion species in the plasma. On the other hand, the ion implantation apparatus is a mass separation type apparatus. In the ion implantation apparatus, ion species in plasma are mass-separated and an object to be processed is irradiated with ion species having a specific mass.

In this embodiment, an example in which hydrogen is added to the single crystal semiconductor substrate 110 using an ion doping apparatus will be described. A gas containing hydrogen is used as the source gas. For the ions to be irradiated, the ratio of H ₃ ⁺ is preferably increased. _{^{Specifically,}} H _^+, H 2 _^+, the proportion of _H ^{3 +} to the total amount of _H ^{3 +} is made to be 50% or more (more preferably 80% or more). Increasing the proportion of H ₃ ⁺ can improve the efficiency of ion irradiation. Note that H ₃ ⁺ may be implanted by an ion implantation apparatus.

Note that ions to be added are not limited to hydrogen. Ions such as helium may be added. Moreover, the ion to add is not limited to one type, You may add multiple types of ion. For example, in the case of simultaneously irradiating hydrogen and helium using an ion doping apparatus, the number of steps can be reduced as compared with the case of irradiating in separate steps, and the surface roughness of the subsequent single crystal semiconductor layer can be reduced. Can be further suppressed.

The insulating layer 114 can be formed using a single layer or a stacked layer of insulating layers such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, and a silicon nitride oxide film. These films can be formed using a thermal oxidation method, a CVD method, a sputtering method, or the like. The thickness of the insulating layer is desirably about 10 nm to 200 nm.

Note that in this specification and the like, the term “oxynitride” refers to a composition whose oxygen content (number of atoms) is higher than that of nitrogen. For example, silicon oxynitride refers to oxygen at 50 atomic% or more and 70 It includes atoms in a range of not more than atomic%, nitrogen not less than 0.5 atom% and not more than 15 atom%, silicon not less than 25 atom% and not more than 35 atom%, and hydrogen not less than 0.1 atom% and not more than 10 atom%. In addition, a nitrided oxide indicates a composition whose nitrogen content (number of atoms) is higher than that of oxygen. For example, silicon nitride oxide refers to an oxygen content of 5 atomic% to 30 atomic% and nitrogen content. It includes 20 atomic% to 55 atomic%, silicon in a range of 25 atomic% to 35 atomic%, and hydrogen in a range of 10 atomic% to 30 atomic%. However, the above ranges are those measured using Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering (HFS). Further, the total content ratio of the constituent elements does not exceed 100 atomic%.

In the bonding, the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other with the insulating layer 114 interposed therebetween, and then 0.001 N / cm ² at a position indicated by a white arrow on the base substrate 100 or the single crystal semiconductor substrate 110. This is performed by applying a pressure of 100 N / cm ² or less (see FIG. 1D).

FIG. 3A shows the positional relationship between the bonding start region 150 and the opening 140. The bonding is performed so that the opening 140 is arranged at the corner facing the bonding start region 150. When pressure is applied, bonding between the base substrate 100 and the insulating layer 114 occurs at that portion, and spontaneous bonding extends over the entire surface starting from the portion. In this joining, van der Waals force and hydrogen bond act and can be performed at room temperature. By the bonding process, a closed region due to the arrangement of the opening is formed.

Note that it is preferable that the bonding be performed so that the opening 140 formed in the insulating layer 114 is disposed in the bonding termination region or in the vicinity thereof.

Note that before the single crystal semiconductor substrate 110 and the base substrate 100 are bonded to each other, it is preferable to perform surface treatment on the surfaces related to bonding. By performing the surface treatment, the bonding strength at the bonding interface between the single crystal semiconductor substrate 110 and the base substrate 100 can be improved.

Examples of the surface treatment include wet treatment, dry treatment, or a combination of wet treatment and dry treatment. Different wet treatments or different dry treatments may be combined.

Examples of the wet treatment include ozone treatment using ozone water (ozone water cleaning), megasonic cleaning, or two-fluid cleaning (a method of spraying functional water such as pure water or hydrogenated water together with a carrier gas such as nitrogen). It is done. Examples of the dry treatment include ultraviolet treatment, ozone treatment, plasma treatment, bias application plasma treatment, and radical treatment. By subjecting the object to be processed (single crystal semiconductor substrate, insulating layer formed on the single crystal semiconductor substrate, supporting substrate, or insulating layer formed on the supporting substrate) to the surface treatment as described above, There is an effect of improving the hydrophilicity and cleanliness of the body surface. As a result, the bonding strength between the substrates can be improved.

The wet treatment is effective for removing macro dust adhering to the surface of the object to be treated. The dry treatment is effective for removing or decomposing micro dust such as organic substances adhering to the surface of the object to be treated. Here, when a wet process such as cleaning is performed after a dry process such as an ultraviolet treatment is performed on the object to be processed, the surface of the object to be processed is cleaned and hydrophilized, and water on the surface of the object to be processed is further removed. Since generation | occurrence | production of a mark can be suppressed, it is preferable.

Further, it is preferable to perform a surface treatment using oxygen in an active state such as ozone or singlet oxygen as the dry treatment. Organic substances attached to the surface of the object to be processed can be effectively removed or decomposed by oxygen in an active state such as ozone or singlet oxygen. In addition, by combining oxygen in an active state such as ozone or singlet oxygen with treatment with light having a wavelength of less than 200 nm among ultraviolet rays, organic substances attached to the surface of the object to be processed can be more effectively removed. it can. This will be specifically described below.

For example, the surface treatment of the object to be processed is performed by irradiating ultraviolet rays in an atmosphere containing oxygen. In an atmosphere containing oxygen, irradiation with light having a wavelength of less than 200 nm and light having a wavelength of 200 nm or more of ultraviolet rays can generate ozone and singlet oxygen. Further, by irradiating light including a wavelength of less than 180 nm among ultraviolet rays, ozone can be generated and singlet oxygen can be generated.

An example of a reaction that occurs by irradiation with light having a wavelength of less than 200 nm and light having a wavelength of 200 nm or more in an atmosphere containing oxygen is shown.
O ₂ + hν (λ ₁ nm) → O ( ³ P) + O ( ³ P) (1)
O ( ³ P) + O ₂ → O ₃ (2)
O ₃ + hν (λ ₂ nm) → O ( ¹ D) + O ₂ (3)

In the reaction formula (1), irradiation with light (hν) containing a wavelength (λ ₁ nm) of less than 200 nm in an atmosphere containing oxygen (O ₂ ) results in a ground state oxygen atom (O ( ³ P)). Produces. Next, in the reaction formula (2), the oxygen atom (O ( ³ P)) in the ground state reacts with oxygen (O ₂ ) to generate ozone (O ₃ ). Then, in reaction formula (3), irradiation with light including a wavelength (λ ₂ nm) of 200 nm or more is performed in an atmosphere including the generated ozone (O ₃ ), whereby singlet oxygen O ( ¹ D) is generated. In an atmosphere containing oxygen, ozone is generated by irradiating light having a wavelength of less than 200 nm among ultraviolet rays, and singlet oxygen is generated by decomposing ozone by irradiating light having a wavelength of 200 nm or more. To do. The surface treatment as described above can be performed, for example, by irradiation with a low-pressure mercury lamp (λ ₁ = 185 nm, λ ₂ = 254 nm) in an atmosphere containing oxygen.

An example of a reaction that occurs by irradiation with light having a wavelength of less than 180 nm in an atmosphere containing oxygen is shown.
O ₂ + hν (λ ₃ nm) → O ( ¹ D) + O ( ³ P) (4)
O ( ³ P) + O ₂ → O ₃ (5)
O ₃ + hν (λ ₃ nm) → O ( ¹ D) + O ₂ (6)

In the reaction formula (4), singlet oxygen O ( ¹ D) and a ground state in an excited state are irradiated with light including a wavelength (λ ₃ nm) of less than 180 nm in an atmosphere including oxygen (O ₂ ). Of oxygen atoms (O ( ³ P)). Next, in reaction formula (5), oxygen atoms (O ( ³ P)) in the ground state and oxygen (O ₂ ) react to generate ozone (O ₃ ). In reaction formula (6), singlet oxygen and oxygen in an excited state are generated by irradiation with light having a wavelength of less than 180 nm (λ ₃ nm) in an atmosphere including the generated ozone (O ₃ ). The In an atmosphere containing oxygen, ozone is generated by irradiating light having a wavelength of less than 180 nm among ultraviolet rays, and ozone or oxygen is decomposed to generate singlet oxygen. The surface treatment as described above can be performed, for example, by irradiation with a Xe excimer UV lamp in an atmosphere containing oxygen.

Chemical bonds such as organic substances adhering to the surface of the object to be processed are cut by light having a wavelength of less than 200 nm, and organic substances adhering to the surface of the object to be processed or organic substances having broken chemical bonds are oxidatively decomposed by ozone or singlet oxygen. Can be removed. By performing the surface treatment as described above, the hydrophilicity and cleanliness of the surface of the object to be processed can be further improved, and bonding can be performed satisfactorily.

Note that heat treatment for increasing the bonding strength may be performed after the bonding. The temperature of this heat treatment is set to a temperature at which separation in the embrittled region 112 does not occur (for example, room temperature or higher and lower than 400 ° C.). Further, the base substrate 100 and the insulating layer 114 may be bonded while heating in this temperature range. For the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (Rapid Thermal Annealing) apparatus, a microwave heating apparatus, or the like can be used. Note that the above temperature condition is merely an example, and one embodiment of the disclosed invention is not construed as being limited thereto.

Next, for example, the single crystal semiconductor substrate 110 is separated from the embrittlement region 112 by heat treatment at a temperature of 400 ° C. or higher, whereby the single crystal semiconductor layer 116 is formed over the base substrate 100 with the insulating layer 114 interposed therebetween. Provided (see FIGS. 1E and 1F).

By performing the heat treatment, the added element is precipitated in the minute holes formed in the embrittled region 112, and the internal pressure rises. The increase in pressure causes a crack in the embrittled region 112, so that the single crystal semiconductor substrate 110 is separated along the embrittled region 112. Since the insulating layer 114 is bonded to the base substrate 100, the single crystal semiconductor layer 116 separated from the single crystal semiconductor substrate 110 remains on the base substrate 100. Note that since the bonding is not performed in the opening 140, the single crystal semiconductor layer 116 is not formed in a region corresponding to the opening 140 of the base substrate 100. The region serves as a trigger for separation, and surface roughness of the single crystal semiconductor layer 116 can be suppressed.

In addition, it is desirable that the heat treatment temperature in the separation is as low as possible. This is because surface roughness of the single crystal semiconductor layer 116 can be suppressed as the temperature at the time of separation is lower.

Specifically, for example, it is effective that the heat treatment temperature in the separation is 300 ° C. or more and 600 ° C. or less, preferably 400 ° C. or more and 500 ° C. or less.

In addition, when forming the closed area | region formed of the said opening part, it has been confirmed that the heat processing temperature in the case of isolation | separation can be restrained low. As an example, in the case where a closed region is not formed, even if a temperature condition of 500 ° C. or higher is required for the separation, the closed region is formed and the separation is performed at a temperature condition of 500 ° C. or lower. Is possible. This is considered to be caused by the fact that the closed region is a trigger for the separation, whereby the separation at a lower temperature is realized as compared with the case where the region does not exist. Note that the above temperature condition is merely an example, and one embodiment of the disclosed invention is not construed as being limited thereto.

Note that after the separation, heat treatment at 500 ° C. to 800 ° C. may be performed to reduce the concentration of remaining hydrogen. By performing the separation step and the hydrogen concentration reduction step in one heat treatment step, surface roughness of the single crystal semiconductor layer can be suppressed without increasing the number of steps.

Further, by forming the closed region formed by the opening, there is also an advantage that the separation timing (separation temperature) can be made uniform. By making the separation timing uniform, it is possible to suppress fluctuations in substrate characteristics due to surface roughness. In this regard, it has been confirmed that the temperature at the time of separation is generally within the range of ± 1 ° C. in a plurality of samples (4 samples) in which non-bonded regions are formed. Note that the timing of separation is merely an example, and one embodiment of the disclosed invention is not construed as being limited thereto.

Next, the surface of the single crystal semiconductor layer 116 is irradiated with laser light 132, whereby the single crystal semiconductor layer 118 with improved surface flatness and reduced defects is formed (FIG. 2A). 2 (B) and FIG. 3 (A)). Note that FIG. 2B corresponds to a cross section taken along line AB of FIG.

Note that melting of the single crystal semiconductor layer 116 by irradiation with the laser light 132 is preferably partial melting. This is because, when completely melted, microcrystallization occurs due to disordered nucleation after becoming a liquid phase, and crystallinity is lowered. On the other hand, in partial melting, crystal growth can be performed based on a solid phase portion that is not melted, so that the crystal quality can be improved as compared with the case where the single crystal semiconductor layer 116 is completely melted. In addition, uptake of oxygen, nitrogen, or the like from the insulating layer 114 can be suppressed. Note that in the above, partial melting means that the depth at which the single crystal semiconductor layer 116 is melted by laser light irradiation is shallower than the depth of the interface on the insulating layer 114 side (that is, less than the thickness of the single crystal semiconductor layer 116). ) Say that. That is, the upper layer of the single crystal semiconductor layer 116 is melted to be in a liquid phase, but the lower layer is not melted and remains in a solid phase. Further, complete melting means that the single crystal semiconductor layer 116 is melted to the interface with the insulating layer 114 to be in a liquid state.

A pulsed laser is preferably used for the laser light irradiation. This is because high energy can be obtained and it is easy to create a partially molten state. The oscillation frequency is preferably about 1 Hz to 10 MHz, but is not limited to this. As the oscillator of the above-mentioned pulsed laser, Ar laser, Kr laser, excimer (ArF, KrF, XeCl) laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ There are O ₃ laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, gold vapor laser and the like. If continuous melting is possible, a continuous wave laser may be used. As the oscillator of the continuous wave laser, Ar laser, Kr laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, ruby laser, alexandrite laser, Ti: There are sapphire laser, helium cadmium laser and the like.

As a wavelength of the laser beam 132, a wavelength absorbed by the single crystal semiconductor layer 116 needs to be selected. The wavelength may be determined in consideration of the skin depth of the laser light. For example, it can be in the range of 250 nm to 700 nm. The energy density of the laser light 132 can be determined in consideration of the wavelength of the laser light 132, the skin depth of the laser light, the thickness of the single crystal semiconductor layer 116, and the like. The energy density of the laser beam 132 may be, for example, in the range of 300 mJ / cm ² or more and 800 mJ / cm ² or less. The range of the energy density is an example when a XeCl excimer laser (wavelength: 308 nm) is used as a pulsed laser.

Irradiation with the laser beam 132 can be performed in an atmosphere containing oxygen such as an air atmosphere or an inert atmosphere such as a nitrogen atmosphere or an argon atmosphere. In order to irradiate the laser beam 132 in an inert atmosphere, the laser beam 132 may be irradiated in an airtight chamber and the atmosphere in the chamber may be controlled. In the case where a chamber is not used, an inert atmosphere can be formed by spraying an inert gas such as nitrogen gas on the surface to be irradiated with the laser beam 132.

Note that when performed in an inert atmosphere such as nitrogen, the planarity of the single crystal semiconductor layer 118 is higher than that in the air atmosphere. In addition, the inert atmosphere has a higher effect of suppressing the generation of cracks and ridges than the air atmosphere, and the usable energy density range of the laser beam 132 is widened. Note that the irradiation with the laser light 132 may be performed in a reduced-pressure atmosphere. When the laser beam 132 is irradiated in a reduced pressure atmosphere, the same effect as that in the inert atmosphere can be obtained.

Note that in this embodiment, the irradiation treatment with the laser light 132 is performed immediately after the heat treatment for separation of the single crystal semiconductor layer 116; however, one embodiment of the disclosed invention is not construed as being limited thereto. After the heat treatment related to the separation of the single crystal semiconductor layer 116, etching treatment may be performed to remove a region having many defects on the surface of the single crystal semiconductor layer 116, and then the irradiation treatment with the laser light 132 may be performed. After the single crystal semiconductor layer 116 in the vicinity of the formed region is removed by etching, the irradiation treatment with the laser light 132 may be performed, or after the flatness of the surface of the single crystal semiconductor layer 116 is improved, the irradiation treatment with the laser light 132 is performed. May be performed. Note that when the single crystal semiconductor layer 116 in the vicinity of the region where the opening 144 is formed is etched away, the vicinity of the outer periphery of the single crystal semiconductor layer 116 may be removed by etching at the same time. As the etching process, either wet etching or dry etching may be used.

Although not shown in this embodiment mode, a thinning process for reducing the thickness of the single crystal semiconductor layer 118 may be performed after the laser light 132 is irradiated as described above. In order to reduce the thickness of the single crystal semiconductor layer 118, either dry etching or wet etching, or a combination of both may be used.

Through the above steps, an SOI substrate having a favorable semiconductor layer with reduced surface roughness can be obtained (see FIGS. 2B and 3A).

In this embodiment, the surface of the single crystal semiconductor layer 116 is irradiated with laser light 132, whereby the single crystal semiconductor layer 118 with improved surface flatness and reduced defects is obtained. Here, when the surface of the single crystal semiconductor layer 116 before being irradiated with the laser light 132 is rough, the film quality of the single crystal semiconductor layer 118 tends to be deteriorated by irradiating the laser light 132. For example, even when a very small defect (such as a partial film defect) exists in the single crystal semiconductor layer 116, the defect tends to be enlarged by irradiation with the laser beam 132. This is because the semiconductor in the peripheral region of the fine defect (the region where the single crystal semiconductor layer 116 is thin) is melted by irradiation with the laser beam 132, and the semiconductor in the region moves due to surface tension or the like. It is considered to be caused by this.

As described above, when the surface of the single crystal semiconductor layer 116 is rough, defects due to the tendency tend to occur. Therefore, it is important to suppress the surface roughness of the single crystal semiconductor layer 116. In particular, in the case of using laser beam 132 irradiation, the method for forming a closed region by the arrangement of the opening shown in this embodiment is an extremely effective solution.

Note that after the above steps, the island-shaped semiconductor layer 120 may be formed by etching the single crystal semiconductor layer 118 of the SOI substrate. At the time of the etching, it is preferable to remove the single crystal semiconductor layer 118 in a region corresponding to the peripheral portion (near the region where the opening 140 is formed) (FIGS. 2C and 3B). )reference). Note that FIG. 2C corresponds to a cross section taken along line AB of FIG. Here, the region corresponding to the peripheral portion of the single crystal semiconductor layer 118 is removed because the possibility of peeling of the semiconductor layer due to insufficient bonding strength increases. Note that the insufficient bonding strength is caused by a surface shape having a curvature (referred to as edge roll-off) due to the surface polishing treatment at the end of the single crystal semiconductor substrate surface, or the substrate surface This is caused by the unevenness.

Note that although the structure in which the opening is provided at one corner of the single crystal semiconductor layer is described in this embodiment (see FIG. 3A and the like), one embodiment of the disclosed invention is not limited thereto. . What is necessary is just to set suitably the arrangement | positioning, the number, size, etc. of the closed area | region formed by an opening part. For example, an opening may be formed in the vicinity of a region where minute air that is formed in the terminal region of bonding is confined. Further, for example, a plurality of openings may be formed in the vicinity of a region where minute air formed in the terminal region of bonding is confined. Thereby, the movement of the minute air into the opening can be induced, and the generation of the region where the minute air is confined can be suppressed or eliminated.

Further, for example, an opening may be formed in a region that overlaps a region where a minute air that is planned is trapped. The compressive stress in the opening can be increased by pushing the air in the gap generated by the confinement of minute air into the opening. Thereby, generation | occurrence | production of the area | region where minute air is confined can be suppressed or eliminated. The vicinity of the region where the minute air is confined is a region (dead space) where the bonding strength is insufficient and the semiconductor device is not used. Therefore, a wide region of the remaining single crystal semiconductor layer can be secured by forming an opening in a region which is to be removed later (see FIG. 3B).

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, another example of a method for manufacturing an SOI substrate will be described with reference to drawings.

First, a base substrate 100 and a single crystal semiconductor substrate 110 as a bond substrate are prepared (see FIGS. 4A and 4C). The details of the base substrate 100 and the single crystal semiconductor substrate 110 are omitted here because the above embodiment can be referred to.

An opening 142 is formed in a region corresponding to the periphery of the single crystal semiconductor substrate 110 on the surface of the base substrate 100 (see FIG. 4B). For the method for forming the opening, the above embodiment can be referred to.

The single crystal semiconductor substrate 110 is formed with an embrittlement region 112 at a predetermined depth from the surface, and the base substrate 100 and the single crystal semiconductor substrate 110 are attached to each other with the insulating layer 114 interposed therebetween (see FIG. 4E). ).

The embrittlement region 112 can be formed by irradiating the single crystal semiconductor substrate 110 with ions such as hydrogen having kinetic energy. For details, the previous embodiment may be referred to.

In the bonding, the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other with the insulating layer 114 interposed therebetween, and then 0.001 N / cm ² or more and 100 N / cm at one location of the base substrate 100 or the single crystal semiconductor substrate 110. ^This is done by applying a pressure of ² or less. A portion to which pressure is applied is an end portion of the single crystal semiconductor substrate 110 which is farthest from a region where the opening 142 is disposed, as indicated by a white arrow in FIG. FIG. 6A shows the positional relationship between the bonding start region 150 and the opening 142. The bonding is performed so that the opening 142 is arranged at the corner facing the bonding start region 150. When pressure is applied, bonding between the base substrate 100 and the insulating layer 114 occurs from that portion, and spontaneous bonding covers the entire surface starting from that portion. In this joining, van der Waals force and hydrogen bond act and can be performed at room temperature. By the bonding process, a closed region is formed by arranging the opening 142.

Note that before the single crystal semiconductor substrate 110 and the base substrate 100 are bonded to each other, it is preferable to perform surface treatment on the surfaces related to bonding. By performing the surface treatment, the bonding strength at the bonding interface between the single crystal semiconductor substrate 110 and the base substrate 100 can be improved. For the details of the surface treatment, the previous embodiment can be referred to.

Note that heat treatment for increasing the bonding strength may be performed after the bonding. The temperature of this heat treatment is set to a temperature at which separation in the embrittled region 112 does not occur (for example, room temperature or higher and lower than 400 ° C.). Further, the base substrate 100 and the insulating layer 114 may be bonded while heating in this temperature range. For the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (Rapid Thermal Annealing) apparatus, a microwave heating apparatus, or the like can be used.

Next, heat treatment is performed to separate the single crystal semiconductor substrate 110 at the embrittlement region 112, whereby the single crystal semiconductor layer 116 is provided over the base substrate 100 with the insulating layer 114 interposed therebetween (FIG. 4F). (See FIG. 4G).

By performing the heat treatment, the added element is precipitated in the minute holes formed in the embrittled region 112, and the internal pressure rises. The increase in pressure causes a crack in the embrittled region 112, so that the single crystal semiconductor substrate 110 is separated along the embrittled region 112. Since the insulating layer 114 is bonded to the base substrate 100, the single crystal semiconductor layer 116 separated from the single crystal semiconductor substrate 110 remains on the base substrate 100. Note that since the bonding is not performed in the opening 142, the single crystal semiconductor layer 116 is not formed in a region corresponding to the opening 142 of the base substrate 100. Such a region serves as a trigger for separation, and surface roughness of the single crystal semiconductor layer 116 can be suppressed.

Next, the surface of the single crystal semiconductor layer 116 is irradiated with laser light 132, whereby the single crystal semiconductor layer 118 with improved surface flatness and reduced defects is formed (FIG. 5A). 5 (B) and FIG. 6 (A)). Note that FIG. 5B corresponds to a cross section taken along line AB of FIG. For the details of irradiation with the laser beam 132, the above embodiment can be referred to.

Note that in this embodiment, the irradiation treatment with the laser light 132 is performed immediately after the heat treatment for separation of the single crystal semiconductor layer 116; however, one embodiment of the disclosed invention is not construed as being limited thereto. An etching treatment may be performed after the heat treatment related to the separation of the single crystal semiconductor layer 116 so that a region with many defects on the surface of the single crystal semiconductor layer 116 is removed, and then the irradiation treatment with the laser light 132 may be performed. After the single crystal semiconductor layer 116 in the vicinity of the formed region is removed by etching, the irradiation treatment with the laser light 132 may be performed, or after the flatness of the surface of the single crystal semiconductor layer 116 is improved, the irradiation treatment with the laser light 132 is performed. May be performed. Note that when the single crystal semiconductor layer 116 in the vicinity of the region where the opening 144 is formed is etched away, the vicinity of the outer periphery of the single crystal semiconductor layer 116 may be removed by etching at the same time. As the etching process, either wet etching or dry etching may be used.

Although not shown in this embodiment mode, a thinning process for reducing the thickness of the single crystal semiconductor layer 118 may be performed after the laser light 132 is irradiated as described above. In order to reduce the thickness of the single crystal semiconductor layer 118, either dry etching or wet etching, or a combination of both may be used.

Through the above steps, an SOI substrate having a good semiconductor layer with reduced surface roughness can be obtained while effectively utilizing the dead space generated in the vicinity of the bonding end portion of the single crystal semiconductor substrate 110 (FIG. 5). (B), see FIG. 6 (A)).

Note that after the above steps, the island-shaped semiconductor layer 120 may be formed by patterning the single crystal semiconductor layer 118 of the SOI substrate. In the patterning, it is preferable to remove the single crystal semiconductor layer 118 in the vicinity of the region where the opening 142 is formed (see FIGS. 5C and 6B). Note that FIG. 5C corresponds to a cross section taken along line AB of FIG. Here, the region corresponding to the vicinity of the region where the opening 142 of the single crystal semiconductor layer 118 is formed is that there is a region that cannot be used as a semiconductor device due to the formation of the closed region, and the bonding strength is This is because the possibility of peeling of the semiconductor layer increases due to the shortage of. Further, the peripheral portion of the single crystal semiconductor layer is etched for the same reason.

Note that although the structure in which the opening is provided at one corner of the single crystal semiconductor layer is described in this embodiment (see FIG. 6A and the like), one embodiment of the disclosed invention is not limited thereto. . What is necessary is just to set suitably the arrangement | positioning, the number, size, etc. of the closed area | region formed by an opening part. For example, an opening may be formed in the vicinity of a region where minute air that is formed in the terminal region of bonding is confined. Further, for example, a plurality of openings may be formed in the vicinity of a region where minute air formed in the terminal region of bonding is confined. Thereby, the movement of the minute air into the opening can be induced, and the generation of the region where the minute air is confined can be suppressed or eliminated.

Further, for example, an opening may be formed in a region that overlaps a region where a minute air that is planned is trapped. The compressive stress in the opening can be increased by pushing the air in the gap generated by the confinement of minute air into the opening. Thereby, generation | occurrence | production of the area | region where minute air is confined can be suppressed or eliminated. The vicinity of the region where the minute air is confined is a region (dead space) where the bonding strength is insufficient and the semiconductor device is not used. Therefore, a wide region of the remaining single crystal semiconductor layer can be secured by forming an opening in a region which is to be removed later (see FIG. 6B).

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, another example of a method for manufacturing an SOI substrate will be described with reference to drawings.

First, a base substrate 100 and a single crystal semiconductor substrate 110 as a bond substrate are prepared (see FIGS. 7A and 7C). The details of the base substrate 100 and the single crystal semiconductor substrate 110 are omitted here because the above embodiment can be referred to.

A nitrogen-containing layer 102 (for example, a layer including an insulating film containing nitrogen such as a silicon nitride film (SiN _x ) or a silicon nitride oxide film (SiN _x O _y ) (x> y)) is formed on the surface of the base substrate 100. It is formed (see FIG. 7B).

The nitrogen-containing layer 102 formed in this embodiment serves as a layer (a bonding layer) for attaching a single crystal semiconductor layer later. The nitrogen-containing layer 102 also functions as a barrier layer for preventing impurities such as sodium (Na) contained in the base substrate from diffusing into the single crystal semiconductor layer.

As described above, since the nitrogen-containing layer 102 is used as the bonding layer in this embodiment, it is preferable to form the nitrogen-containing layer 102 so that the surface thereof has predetermined flatness. Specifically, the average surface roughness (Ra) of the surface is 0.5 nm or less, the root mean square roughness (Rms) is 0.60 nm or less, more preferably the average surface roughness is 0.35 nm or less, and the root mean square roughness. The nitrogen-containing layer 102 is formed so that the thickness is 0.45 nm or less. The film thickness is in the range of 10 nm to 200 nm, preferably 50 nm to 100 nm. In this manner, when the flatness of the surface is increased, bonding failure of the single crystal semiconductor layer can be prevented.

An oxide film 115 is formed on the surface of the single crystal semiconductor substrate 110 (see FIG. 7D). From the viewpoint of removing contaminants, before the oxide film 115 is formed, sulfuric acid / hydrogen peroxide (SPM), ammonia / hydrogen peroxide (APM), hydrochloric acid / hydrogen peroxide (HPM), hydrofluoric acid / hydrogen peroxide (FPM), dilute hydrofluoric acid ( The surface of the single crystal semiconductor substrate 110 is preferably cleaned using DHF) or the like. The cleaning may be performed by alternately discharging dilute hydrofluoric acid and ozone water.

The oxide film 115 can be formed using a single layer or a stacked layer of, for example, a silicon oxide film, a silicon oxynitride film, or the like. Examples of a method for forming the oxide film 115 include a thermal oxidation method, a CVD method, and a sputtering method. In the case where the oxide film 115 is formed using a CVD method, an organic silane such as tetraethoxysilane (abbreviation: TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ) is used in order to achieve good bonding. It is preferable to form a silicon oxide film.

In this embodiment, the single crystal semiconductor substrate 110 is subjected to thermal oxidation treatment to form an oxide film 115 (here, a SiO _x film). The thermal oxidation treatment is preferably performed by adding halogen in an oxidizing atmosphere.

For example, by performing thermal oxidation treatment on the single crystal semiconductor substrate 110 in an oxidizing atmosphere to which chlorine (Cl) is added, the chlorine-oxidized oxide film 115 can be formed. In this case, the oxide film 115 is a film containing chlorine atoms.

Chlorine atoms contained in the oxide film 115 cause distortion in the oxide film 115. As a result, the absorption ratio of the oxide film 115 to water is improved, and the water diffusion rate is increased. That is, when water is present on the surface of the oxide film 115, the water present on the surface can be quickly absorbed and diffused into the oxide film 115, so that poor bonding due to the presence of water can be reduced. .

Further, since a chloride of heavy metal (eg, Fe, Cr, Ni, Mo, etc.) that is an exogenous impurity during oxidation can be formed and removed outside the single crystal semiconductor substrate 110, the single crystal semiconductor substrate 110 is contaminated. Can be reduced. Further, after bonding to the base substrate, impurities such as Na from the base substrate can be fixed to prevent the single crystal semiconductor substrate 110 from being contaminated.

Note that the halogen atoms contained in the oxide film 115 are not limited to chlorine atoms. The oxide film 115 may contain fluorine atoms. As a method of oxidizing the surface of the single crystal semiconductor substrate 110 with fluorine, a method of performing thermal oxidation treatment in an oxidizing atmosphere after being immersed in an HF solution, or a method of performing thermal oxidation treatment by adding NF ₃ to the oxidizing atmosphere and so on.

Next, the single crystal semiconductor substrate 110 is irradiated with ions accelerated by an electric field, so that an embrittled region 112 having a damaged crystal structure is formed at a predetermined depth in the single crystal semiconductor substrate 110 (FIG. 7D). reference). For details, the previous embodiment may be referred to. Note that in the case where the embrittlement region 112 is formed using an ion doping apparatus, heavy metal may be added at the same time, but these ions can be irradiated by irradiating ions through the oxide film 115 containing a halogen atom. Contamination of the single crystal semiconductor substrate 110 with heavy metal can be prevented.

Next, an opening 140 is formed in a region corresponding to the peripheral portion of the single crystal semiconductor substrate 110 on the surface of the oxide film 115, and a region to be a region closed later by the base substrate 100 and the single crystal semiconductor substrate 110 is formed. (See FIG. 7E). Such a region becomes a trigger at the time of separation, and surface roughness of the single crystal semiconductor layer can be suppressed.

Note that in this embodiment, the closed region is formed by forming the opening 140 in the oxide film 115; however, one embodiment of the disclosed invention is not limited to this. For the method for forming the closed region, the above embodiment can be referred to.

Next, the surface of the base substrate 100 and the surface of the single crystal semiconductor substrate 110 are opposed to each other, and the surface of the nitrogen-containing layer 102 and the surface of the oxide film 115 are bonded (see FIG. 7F).

Here, after the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other through the nitrogen-containing layer 102 and the oxide film 115, 0.001 N / cm ² or more is provided at one location of the base substrate 100 or the single crystal semiconductor substrate 110. A pressure of 100 N / cm ² or less is applied. A portion to which pressure is applied is an end portion of the single crystal semiconductor substrate 110 which is farthest from a region where the opening 140 is disposed, as indicated by a white arrow in FIG. FIG. 9A shows the positional relationship between the bonding start region 150 and the opening 140. The bonding is performed so that the opening 140 is arranged at the corner facing the bonding start region 150. Then, the nitrogen-containing layer 102 and the oxide film 115 are joined from the portion where the pressure is applied, and the spontaneous joining reaches the entire surface starting from the portion. In this joining, van der Waals force and hydrogen bond act and can be performed at room temperature. By the bonding process, a closed region is formed by arranging the opening 140.

Note that the surface treatment of the oxide film 115 formed over the single crystal semiconductor substrate 110 and the nitrogen-containing layer 102 formed over the base substrate 100 is performed before the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other. It is preferable to carry out. The previous embodiment can be referred to for details of the surface treatment. Here, a bias application plasma treatment is performed on at least one of the nitrogen-containing layer 102 and the oxide film 115 before bonding to activate the vicinity of the surface. By performing plasma treatment using any one or a combination of O ₂ , N ₂ , and Ar, it is possible to add OH groups in the vicinity of the surface, or to easily absorb H ₂ O, so that the state is suitable for bonding. can do.

In addition, after the nitrogen-containing layer 102 and the oxide film 115 are bonded, it is preferable to perform heat treatment for increasing the bonding strength. The temperature of this heat treatment is set to a temperature at which separation in the embrittled region 112 does not occur (for example, room temperature or higher and lower than 400 ° C.). Further, the nitrogen-containing layer 102 and the oxide film 115 may be bonded while heating in this temperature range. For the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA apparatus, a microwave heating apparatus, or the like can be used.

Next, heat treatment is performed to separate the single crystal semiconductor substrate 110 at the embrittlement region 112, whereby the single crystal semiconductor layer 116 is formed over the base substrate 100 with the nitrogen-containing layer 102 and the oxide film 115 interposed therebetween ( (See FIGS. 7G and 8A). For the details of the heat treatment, the above embodiment can be referred to. Here, since bonding is not performed in the opening 140, the single crystal semiconductor layer 116 is not formed in a region corresponding to the opening 140 of the base substrate 100. Such a region serves as a trigger for separation, and surface roughness of the single crystal semiconductor layer 116 can be suppressed.

Next, the surface of the single crystal semiconductor layer 116 is irradiated with laser light 132, whereby the single crystal semiconductor layer 118 with improved surface flatness and reduced defects is formed (FIG. 8B). 8 (C) and FIG. 9 (A)). Note that FIG. 8C corresponds to a cross section taken along line AB of FIG. For details, the previous embodiment can be referred to.

Note that in this embodiment, the irradiation treatment with the laser light 132 is performed immediately after the heat treatment for separation of the single crystal semiconductor layer 116; however, one embodiment of the disclosed invention is not construed as being limited thereto. An etching treatment may be performed after the heat treatment related to the separation of the single crystal semiconductor layer 116 so that a region with many defects on the surface of the single crystal semiconductor layer 116 is removed, and then the irradiation treatment with the laser light 132 may be performed. After the single crystal semiconductor layer 116 in the vicinity of the formed region is removed by etching, the irradiation treatment with the laser light 132 may be performed, or after the flatness of the surface of the single crystal semiconductor layer 116 is improved, the irradiation treatment with the laser light 132 is performed. May be performed. Note that when the single crystal semiconductor layer 116 in the vicinity of the region where the opening 142 is formed is removed by etching, the vicinity of the outer periphery of the single crystal semiconductor layer 116 may be simultaneously removed by etching. As the etching process, either wet etching or dry etching may be used.

Although not shown in this embodiment mode, a thinning step for reducing the thickness of the single crystal semiconductor layer 118 may be performed after the laser light 132 is irradiated as described above. In order to reduce the thickness of the single crystal semiconductor layer 118, either dry etching or wet etching, or a combination of both may be used.

Through the above steps, an SOI substrate having a good semiconductor layer with reduced surface roughness can be obtained while effectively utilizing the dead space generated in the vicinity of the bonding end portion of the single crystal semiconductor substrate 110 (FIG. 8). (C), see FIG. 9A).

Note that after the above steps, the island-shaped semiconductor layer 120 may be formed by patterning the single crystal semiconductor layer 118 of the SOI substrate. In the patterning, the single crystal semiconductor layer 118 in the vicinity of the region where the opening 140 is formed is preferably removed (see FIGS. 8D and 9B). Note that FIG. 8D corresponds to a cross section taken along line AB of FIG. 9B. Here, the region corresponding to the vicinity of the region where the opening 140 is formed in the single crystal semiconductor layer 118 is removed because there is a region that cannot be used as a semiconductor device due to the formation of the closed region, and the bonding strength This is because the possibility of peeling of the semiconductor layer increases due to the shortage of. Further, the peripheral portion of the single crystal semiconductor layer is etched for the same reason.

Note that although the structure in which the opening is provided at one corner of the single crystal semiconductor layer is described in this embodiment (see FIG. 9A and the like), one embodiment of the disclosed invention is not limited thereto. . What is necessary is just to set suitably the arrangement | positioning, the number, size, etc. of the closed area | region formed by an opening part. For example, an opening may be formed in the vicinity of a region where minute air that is formed in the terminal region of bonding is confined. Further, for example, a plurality of openings may be formed in the vicinity of a region where minute air formed in the terminal region of bonding is confined. Thereby, the movement of the minute air into the opening can be induced, and the generation of the region where the minute air is confined can be suppressed or eliminated.

Further, for example, an opening may be formed in a region that overlaps a region where a minute air that is planned is trapped. The compressive stress in the opening can be increased by pushing the air in the gap generated by the confinement of minute air into the opening. Thereby, generation | occurrence | production of the area | region where minute air is confined can be suppressed or eliminated. The vicinity of the region where the minute air is confined is a region (dead space) where the bonding strength is insufficient and the semiconductor device is not used. Therefore, a wide region of the remaining single crystal semiconductor layer can be secured by forming an opening in a region to be removed later (see FIG. 9B).

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, another example of a method for manufacturing an SOI substrate will be described with reference to drawings.

First, a base substrate 100 and a single crystal semiconductor substrate 110 as a bond substrate are prepared (see FIGS. 10A and 10D). For the details of the base substrate 100 and the single crystal semiconductor substrate 110, the above embodiment can be referred to.

An opening 142 is formed in a region corresponding to the peripheral portion of the single crystal semiconductor substrate 110 on the surface of the base substrate 100 (see FIG. 10B). For the method for forming the opening, the above embodiment can be referred to.

Thereafter, a nitrogen-containing layer 102 (for example, a layer including an insulating film containing nitrogen such as a silicon nitride film (SiN _x ) or a silicon nitride oxide film (SiN _x O _y ) (x> y)) is formed on the surface of the base substrate 100. ) (See FIG. 10C). Since the opening 142 is formed in the base substrate 100, the opening 144 is formed in the nitrogen-containing layer 102. The opening 144 is a trigger for separation, and surface roughness of the single crystal semiconductor layer 116 can be suppressed.

Note that the nitrogen-containing layer 102 formed in this embodiment is a layer (a bonding layer) for attaching a single crystal semiconductor layer later. The nitrogen-containing layer 102 also functions as a barrier layer for preventing impurities such as sodium (Na) contained in the base substrate from diffusing into the single crystal semiconductor layer. For the details of the nitrogen-containing layer 102, the above embodiment may be referred to.

An oxide film 115 is formed on the surface of the single crystal semiconductor substrate 110 (see FIG. 10E). For the details of the oxide film 115, the above embodiment can be referred to.

Next, the single crystal semiconductor substrate 110 is irradiated with ions accelerated by an electric field, whereby an embrittled region 112 having a damaged crystal structure is formed at a predetermined depth of the single crystal semiconductor substrate 110 (FIG. 10F). reference). For details, the previous embodiment may be referred to. Note that in the case where the embrittlement region 112 is formed using an ion doping apparatus, heavy metal may be added at the same time, but these ions can be irradiated by irradiating ions through the oxide film 115 containing a halogen atom. Contamination of the single crystal semiconductor substrate 110 with heavy metal can be prevented.

Next, the surface of the base substrate 100 and the surface of the single crystal semiconductor substrate 110 are opposed to each other, and the surface of the nitrogen-containing layer 102 and the surface of the oxide film 115 are bonded (see FIG. 10G).

Here, after the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other through the nitrogen-containing layer 102 and the oxide film 115, 0.001 N / cm ² or more is provided at one location of the base substrate 100 or the single crystal semiconductor substrate 110. A pressure of 100 N / cm ² or less is applied. A portion to which pressure is applied is an end portion of the single crystal semiconductor substrate 110 which is farthest from a region where the opening portion 144 is disposed, as indicated by a white arrow in FIG. FIG. 12A shows the positional relationship between the bonding start region 150 and the opening 144. The bonding is performed so that the opening 144 is arranged at the corner facing the bonding start region 150. Then, the nitrogen-containing layer 102 and the oxide film 115 are joined from the portion where the pressure is applied, and the spontaneous joining reaches the entire surface starting from the portion. In this joining, van der Waals force and hydrogen bond act and can be performed at room temperature. By the bonding process, a closed region is formed by arranging the opening 144.

Note that the surface treatment of the oxide film 115 formed over the single crystal semiconductor substrate 110 and the nitrogen-containing layer 102 formed over the base substrate 100 is performed before the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other. It is preferable to carry out. The previous embodiment can be referred to for details of the surface treatment.

In addition, after the nitrogen-containing layer 102 and the oxide film 115 are bonded, it is preferable to perform heat treatment for increasing the bonding strength. The temperature of this heat treatment is set to a temperature at which separation in the embrittled region 112 does not occur (for example, room temperature or higher and lower than 400 ° C.). Further, the nitrogen-containing layer 102 and the oxide film 115 may be bonded while heating in this temperature range. For the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA apparatus, a microwave heating apparatus, or the like can be used.

Next, heat treatment is performed to separate the single crystal semiconductor substrate 110 at the embrittlement region 112, whereby the single crystal semiconductor layer 116 is formed over the base substrate 100 with the nitrogen-containing layer 102 and the oxide film 115 interposed therebetween ( (Refer FIG. 10 (H) and FIG. 11 (A)). For the details of the heat treatment, the above embodiment can be referred to. Here, since bonding is not performed in the opening 144, the single crystal semiconductor layer 116 is not formed in a region corresponding to the opening 144 of the base substrate 100. Such a region serves as a trigger for separation, and surface roughness of the single crystal semiconductor layer 116 can be suppressed.

Next, the surface of the single crystal semiconductor layer 116 is irradiated with laser light 132, whereby the single crystal semiconductor layer 118 with improved surface flatness and reduced defects is formed (FIG. 11B). 11 (C) and FIG. 12 (A)). Note that FIG. 11C corresponds to a cross section taken along line AB of FIG. For details, the previous embodiment can be referred to.

Note that in this embodiment, the irradiation treatment with the laser light 132 is performed immediately after the heat treatment for separation of the single crystal semiconductor layer 116; however, one embodiment of the disclosed invention is not construed as being limited thereto. After the heat treatment related to the separation of the single crystal semiconductor layer 116, etching treatment may be performed to remove a region having many defects on the surface of the single crystal semiconductor layer 116, and then the irradiation treatment with the laser light 132 may be performed. After the single crystal semiconductor layer 116 in the vicinity of the formed region is removed by etching, the irradiation treatment with the laser light 132 may be performed, or after the flatness of the surface of the single crystal semiconductor layer 116 is improved, the irradiation treatment with the laser light 132 is performed. May be performed. Note that when the single crystal semiconductor layer 116 in the vicinity of the region where the opening 144 is formed is etched away, the vicinity of the outer periphery of the single crystal semiconductor layer 116 may be removed by etching at the same time. As the etching process, either wet etching or dry etching may be used.

Although not shown in this embodiment mode, a thinning step for reducing the thickness of the single crystal semiconductor layer 118 may be performed after the laser light 132 is irradiated as described above. In order to reduce the thickness of the single crystal semiconductor layer 118, either dry etching or wet etching, or a combination of both may be used.

Through the above steps, an SOI substrate having a good semiconductor layer with reduced surface roughness can be obtained while effectively utilizing the dead space generated in the vicinity of the bonding end portion of the single crystal semiconductor substrate 110 (FIG. 11). (C) and FIG. 12 (A)).

Note that after the above steps, the island-shaped semiconductor layer 120 may be formed by patterning the single crystal semiconductor layer 118 of the SOI substrate. In the patterning, the single crystal semiconductor layer 118 in the vicinity of the region where the opening 144 is formed is preferably removed (see FIGS. 11D and 12B). Note that FIG. 11D corresponds to a cross section taken along line AB of FIG. Here, the region corresponding to the vicinity of the region where the opening 144 is formed in the single crystal semiconductor layer 118 is removed because there is a region that cannot be used as a semiconductor device due to the formation of the closed region, and the bonding strength This is because the possibility of peeling of the semiconductor layer increases due to the shortage of. Further, the peripheral portion of the single crystal semiconductor layer is etched for the same reason.

Note that although the structure in which the opening is provided at one corner portion of the single crystal semiconductor layer is described in this embodiment (see FIG. 12A and the like), one embodiment of the disclosed invention is not limited thereto. . What is necessary is just to set suitably arrangement | positioning, the number, etc. of the closed area | region formed by an opening part. For example, an opening may be formed in the vicinity of a region where minute air that is formed in the terminal region of bonding is confined. Further, for example, a plurality of openings may be formed in the vicinity of a region where minute air formed in the terminal region of bonding is confined. Thereby, the movement of the minute air into the opening can be induced, and the generation of the region where the minute air is confined can be suppressed or eliminated.

Further, for example, an opening may be formed in a region that overlaps a region where a minute air that is planned is trapped. The compressive stress in the opening can be increased by pushing the air in the gap generated by the confinement of minute air into the opening. Thereby, generation | occurrence | production of the area | region where minute air is confined can be suppressed or eliminated. The vicinity of the region where the minute air is confined is a region (dead space) where the bonding strength is insufficient and the semiconductor device is not used. Therefore, a wide region of the remaining single crystal semiconductor layer can be secured by forming an opening in a region which is to be removed later (see FIG. 12B).

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, another example of a method for manufacturing an SOI substrate will be described with reference to drawings.

First, a base substrate 100 and a single crystal semiconductor substrate 110 as a bond substrate are prepared (see FIGS. 13A and 13B). The details of the base substrate 100 and the single crystal semiconductor substrate 110 are omitted here because the above embodiment can be referred to.

The surface of the base substrate 100 is preferably cleaned in advance. Since the previous embodiment can be referred to for the cleaning method, it is omitted here. Note that a nitrogen-containing layer (for example, a layer including an insulating film containing nitrogen such as a silicon nitride film (SiN _x ) or a silicon nitride oxide film (SiN _x O _y ) (x> y)) is formed on the surface of the base substrate 100. May be formed.

An embrittlement region 112 is formed at a predetermined depth from the surface of the single crystal semiconductor substrate 110, and the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other with the insulating layer 114 interposed therebetween (FIGS. 13C and 13C). D)). The insulating layer 114 may be formed before the embrittlement region 112 is formed or may be formed after the embrittlement region 112 is formed.

The embrittlement region 112 can be formed by irradiating the single crystal semiconductor substrate 110 with ions such as hydrogen having kinetic energy. For details, the previous embodiment may be referred to.

Next, an opening 140 that penetrates the insulating layer 114 is formed in a region corresponding to the peripheral portion of the single crystal semiconductor substrate 110, and a region that is to be closed later is formed by the base substrate 100 and the single crystal semiconductor substrate 110. (See FIGS. 13C and 13D). Such a region becomes a trigger at the time of separation, and surface roughness of the single crystal semiconductor layer can be suppressed.

Note that in this embodiment, the opening 140 is formed with an opening 140 having a depth shallower than the thickness of the single crystal semiconductor layer 116 after the insulating layer 114 is formed; The embodiment is not construed as being limited thereto. For example, an opening deeper than the embrittlement region 112 may be formed. Alternatively, the opening may be formed by forming the insulating layer 114 after forming the opening in the single crystal semiconductor substrate 110.

Next, the surface of the base substrate 100 and the surface of the single crystal semiconductor substrate 110 are opposed to each other, and the surface of the base substrate 100 and the surface of the insulating layer 114 are bonded (see FIG. 13D).

Here, after the base substrate 100 and the single crystal semiconductor substrate 110 is bonded through at least the insulating layer 114, in one place of the base substrate 100 or a single crystal semiconductor substrate 110 0.001 N / cm ² or more 100 N / cm ² or less Apply pressure. A portion to which pressure is applied is an end portion of the single crystal semiconductor substrate 110 farthest from a region where the opening 140 is disposed, as indicated by a white arrow in FIG. FIG. 3A shows the positional relationship between the bonding start region 150 and the opening 140. The bonding is performed so that the opening 140 is arranged at the corner facing the bonding start region 150. Then, the base substrate 100 and the insulating layer 114 are joined from the portion to which the pressure is applied, and the spontaneous joining reaches the entire surface starting from the portion. In this joining, van der Waals force and hydrogen bond act and can be performed at room temperature. By the bonding process, a closed region is formed by arranging the opening 140.

Note that before the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other, surface treatment of the base substrate 100 and the insulating layer 114 formed over the single crystal semiconductor substrate 110 is preferably performed. The previous embodiment can be referred to for details of the surface treatment.

In addition, after the base substrate 100 and the insulating layer 114 are bonded, heat treatment for increasing the bonding strength is preferably performed. The temperature of this heat treatment is set to a temperature at which separation in the embrittled region 112 does not occur (for example, room temperature or higher and lower than 400 ° C.). Further, the base substrate 100 and the insulating layer 114 may be bonded while heating in this temperature range. For the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA (Rapid Thermal Annealing) apparatus, a microwave heating apparatus, or the like can be used.

Next, heat treatment is performed to separate the single crystal semiconductor substrate 110 at the embrittlement region 112, whereby the single crystal semiconductor layer 116 is formed over the base substrate 100 with at least the insulating layer 114 interposed therebetween (FIG. 13E ) And FIG. 13 (F)). For the details of the heat treatment, the above embodiment can be referred to. Here, since bonding is not performed in the opening 140, the single crystal semiconductor layer 116 is not formed in a region corresponding to the opening 140 of the base substrate 100. Such a region serves as a trigger for separation, and surface roughness of the single crystal semiconductor layer 116 can be suppressed.

Next, the surface of the single crystal semiconductor layer 116 is irradiated with laser light, whereby a single crystal semiconductor layer with improved surface flatness and reduced defects is formed. The previous embodiment can be referred to for the laser light irradiation step and the subsequent steps. In particular, Embodiment 1 may be considered.

In this embodiment, a convex portion is formed on the surface of the single crystal semiconductor substrate 180 after the single crystal semiconductor layer 116 is separated at a position corresponding to the opening 140 formed in the single crystal semiconductor substrate 110. The height of the convex portion can be made lower than that in Embodiment Mode 1 (see FIG. 13E). As a result, since the step of planarizing the surface of the single crystal semiconductor substrate 180 is easier than that in Embodiment 1, the step of reusing the single crystal semiconductor substrate 180 can be facilitated.

FIG. 14 illustrates an example of a method for manufacturing an SOI substrate, which is different from that in FIG. 13, with reference to the drawings.

A difference from FIG. 13 is that after the embrittlement region 112 is formed in the single crystal semiconductor substrate 110 on which the insulating layer 114 is formed, the opening 140 is formed and the peripheral portion 146 of the single crystal semiconductor substrate 110 is etched at the same time. (See FIG. 14C). At this time, the etching process is preferably performed so that an opening deeper than the embrittled region 112 is formed.

For details of steps other than the step of removing the peripheral portion 146 together with the opening 140, FIG. 13 and other embodiments can be referred to.

FIG. 15 is a diagram illustrating a difference depending on whether or not the peripheral portion of the single crystal semiconductor substrate 110 is removed. 15A and 15B show the case where the peripheral portion of the single crystal semiconductor substrate 110 is not removed by etching, and FIGS. 15C and 15D show the base substrate when the peripheral portion is removed by etching. And FIG. 14D are diagrams illustrating a process of bonding the single crystal semiconductor substrate to each other and then separating the substrate and corresponding to FIGS. 14D and 14E. In FIG. 15, the shape of the peripheral portion is shown more emphasized than in FIG.

As shown in FIG. 15A, the peripheral portion 126 of the single crystal semiconductor substrate 110 is formed with a chamfered portion provided at the outer periphery of the edge roll-off and the edge roll-off. When the single crystal semiconductor layer 116 is provided over the base substrate 100 by separating the substrate 110 at the embrittlement region 112, a region 128 where bonding is not sufficiently performed may be generated at the end portion (FIG. 15). (See (B)). Such a region 128 has insufficient bonding strength; therefore, in the process of separating the single crystal semiconductor layer 116 from the single crystal semiconductor substrate 110 or the subsequent manufacturing process of the transistor, There is a risk of film peeling or particles at the end. In addition, the edge roll-off region or the embrittled region at the end and the single crystal film on the embrittled region are peeled off during heat treatment to become particles, and the surface of the base substrate, the surface of the nitrogen-containing layer 102 on the base substrate, or the single crystal film. There is a risk of adhering to the surface of the crystalline semiconductor layer 116.

On the other hand, as illustrated in FIG. 15C, when the peripheral portion 126 including the region where the edge roll-off is formed on the surface of the single crystal semiconductor substrate 110 or the uneven region generated at the end portion is removed, the single crystal semiconductor substrate 110 Even when the single crystal semiconductor layer 116 is separated, bonding to the base substrate 100 side is sufficiently performed in the peripheral region 129 of the single crystal semiconductor layer 116, so that the end portion of the single crystal semiconductor layer 116 is Film peeling and generation of particles can be suppressed.

An SOI substrate having a good semiconductor layer with reduced surface roughness while effectively utilizing the dead space generated in the vicinity of the bonding end portion of the single crystal semiconductor substrate 110 by the manufacturing process of the SOI substrate in this embodiment. Obtainable.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, another example of a method for manufacturing an SOI substrate will be described with reference to drawings. In this embodiment, an example in which a plurality of bond substrates is attached to a base substrate will be described.

First, a base substrate 100 and a single crystal semiconductor substrate 110 as a bond substrate are prepared (see FIGS. 16A and 16D). The details of the base substrate 100 and the single crystal semiconductor substrate 110 are omitted here because the above embodiment can be referred to. Note that in FIG. 16D, only one single crystal semiconductor substrate 110 is illustrated; however, a plurality of single crystal semiconductor substrates 110 are prepared in this embodiment.

A plurality of openings 142 are formed in a region corresponding to the peripheral portion of the single crystal semiconductor substrate 110 on the surface of the base substrate 100 (see FIG. 16B). For the method for forming the opening, the above embodiment can be referred to.

Thereafter, a nitrogen-containing layer 102 (for example, a layer including an insulating film containing nitrogen such as a silicon nitride film (SiN _x ) or a silicon nitride oxide film (SiN _x O _y ) (x> y)) is formed on the surface of the base substrate 100. ) (See FIG. 16C). Since the opening 142 is formed in the base substrate 100, the opening 144 is formed in the nitrogen-containing layer 102. The opening 144 is a trigger for separation, and surface roughness of the single crystal semiconductor layer 116 can be suppressed. Note that the base substrate 100 and the single crystal semiconductor substrate 110 may be bonded to each other without forming the nitrogen-containing layer 102 as described in the above embodiment, for example, Embodiment 2. Here, the nitrogen-containing layer 102 is formed after forming a plurality of openings on the base substrate. However, after forming the nitrogen-containing layer 102 on the base substrate 100, a plurality of openings are formed on the surface of the base substrate 100. A part may be formed. Alternatively, an opening may be formed in each of the plurality of single crystal semiconductor substrates 110.

Note that the nitrogen-containing layer 102 formed in this embodiment is a layer (a bonding layer) for attaching a single crystal semiconductor layer later. The nitrogen-containing layer 102 also functions as a barrier layer for preventing impurities such as sodium (Na) contained in the base substrate from diffusing into the single crystal semiconductor layer. For the details of the nitrogen-containing layer 102, the above embodiment may be referred to.

An oxide film 115 is formed on the surface of the single crystal semiconductor substrate 110 (see FIG. 16E). For the details of the oxide film 115, the above embodiment can be referred to.

Next, the single crystal semiconductor substrate 110 is irradiated with ions accelerated by an electric field, so that an embrittled region 112 having a damaged crystal structure is formed at a predetermined depth in the single crystal semiconductor substrate 110 (FIG. 16F). reference). For details, the previous embodiment may be referred to. Note that in the case where the embrittlement region 112 is formed using an ion doping apparatus, heavy metal may be added at the same time, but these ions can be irradiated by irradiating ions through the oxide film 115 containing a halogen atom. Contamination of the single crystal semiconductor substrate 110 with heavy metal can be prevented.

Next, the surface of the base substrate 100 and the surface of the single crystal semiconductor substrate 110 are opposed to each other, and the surface of the nitrogen-containing layer 102 and the surface of the oxide film 115 are bonded (see FIG. 16G). 16G and subsequent drawings, the base substrate 100, the nitrogen-containing layer 102, and the opening 144 correspond to (FIG. 16C). Of course, the drawing is a schematic diagram. Needless to say, the scale of the single crystal semiconductor substrate 110 relative to the entire base substrate 100 may differ from the actual scale.

Here, after the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other through the nitrogen-containing layer 102 and the oxide film 115, 0.001 N / cm ² or more is provided at one location of the base substrate 100 or the single crystal semiconductor substrate 110. A pressure of 100 N / cm ² or less is applied. A portion to which pressure is applied is an end portion of the single crystal semiconductor substrate 110 farthest from a region where the opening portion 144 is disposed, as indicated by a white arrow in FIG. FIG. 18A is a plan view showing the positional relationship between the bonding start region 150 and the opening 144. The bonding is performed so that the opening 144 is arranged at the corner facing the bonding start region 150. Then, the nitrogen-containing layer 102 and the oxide film 115 are joined from the portion where the pressure is applied, and the spontaneous joining reaches the entire surface starting from the portion. In this joining, van der Waals force and hydrogen bond act and can be performed at room temperature. By the bonding process, a closed region is formed by arranging the opening 144.

Note that the surface treatment of the oxide film 115 formed over the single crystal semiconductor substrate 110 and the nitrogen-containing layer 102 formed over the base substrate 100 is performed before the base substrate 100 and the single crystal semiconductor substrate 110 are bonded to each other. It is preferable to carry out. The previous embodiment can be referred to for details of the surface treatment.

In addition, after the nitrogen-containing layer 102 and the oxide film 115 are bonded, it is preferable to perform heat treatment for increasing the bonding strength. The temperature of this heat treatment is set to a temperature at which separation in the embrittled region 112 does not occur (for example, room temperature or higher and lower than 400 ° C.). Further, the nitrogen-containing layer 102 and the oxide film 115 may be bonded while heating in this temperature range. For the heat treatment, a diffusion furnace, a heating furnace such as a resistance heating furnace, an RTA apparatus, a microwave heating apparatus, or the like can be used.

Next, heat treatment is performed to separate the single crystal semiconductor substrate 110 at the embrittlement region 112, whereby the single crystal semiconductor layer 116 is formed over the base substrate 100 with the nitrogen-containing layer 102 and the oxide film 115 interposed therebetween ( (See FIGS. 16H and 17A). For the details of the heat treatment, the above embodiment can be referred to. Here, since bonding is not performed in the opening 144, the single crystal semiconductor layer 116 is not formed in a region corresponding to the opening 144 of the base substrate 100. Such a region serves as a trigger for separation, and surface roughness of the single crystal semiconductor layer 116 can be suppressed.

Next, the surface of the single crystal semiconductor layer 116 is irradiated with laser light 132, whereby the single crystal semiconductor layer 118 with improved surface flatness and reduced defects is formed (FIG. 17B). 17 (C) and FIG. 18 (A)). Note that FIG. 17C corresponds to a cross section taken along line AB of FIG. For details, the previous embodiment can be referred to.

Note that in this embodiment, the irradiation treatment with the laser light 132 is performed immediately after the heat treatment related to the separation of the plurality of single crystal semiconductor layers 116; however, one embodiment of the disclosed invention is limited to this. Not. An etching treatment may be performed after the heat treatment related to the separation of the plurality of single crystal semiconductor layers 116 to remove a region having many defects on the surface of the plurality of single crystal semiconductor layers 116, and then the irradiation treatment with the laser beam 132 may be performed. The single crystal semiconductor layer 116 in the vicinity of the region where the opening 144 is formed may be removed by etching, and then irradiation treatment with the laser light 132 may be performed, or after the planarity of the surfaces of the plurality of single crystal semiconductor layers 116 is improved. An irradiation treatment with the laser beam 132 may be performed. Note that when the single crystal semiconductor layer 116 in the vicinity of the region where the opening 144 is formed is etched away, the vicinity of the outer periphery of the single crystal semiconductor layer 116 may be removed by etching at the same time. As the etching process, either wet etching or dry etching may be used.

Although not shown in this embodiment mode, a thinning step for reducing the thickness of the plurality of single crystal semiconductor layers 118 may be performed after the laser light 132 is irradiated as described above. In order to reduce the thickness of the plurality of single crystal semiconductor layers 118, either dry etching or wet etching or a combination of both may be used.

Through the above steps, it is possible to obtain an SOI substrate having a good semiconductor layer with reduced surface roughness while effectively using a dead space generated in the vicinity of each bonding end portion of the plurality of single crystal semiconductor substrates 110. (See FIGS. 17C and 18A).

Note that after the above steps, the island-shaped semiconductor layer 120 may be formed by patterning the single crystal semiconductor layer 118 of the SOI substrate. In the patterning, the single crystal semiconductor layer 118 in the vicinity of the region where the opening 144 is formed is preferably removed (see FIGS. 17D and 18B). Note that FIG. 17D corresponds to a cross section taken along line AB of FIG. Here, the region corresponding to the vicinity of the region where the opening 144 is formed in each of the plurality of single crystal semiconductor layers 118 is removed because there is a region that cannot be used as a semiconductor device due to the formation of the closed region. This is because the possibility of peeling of the semiconductor layer due to insufficient bonding strength increases. Further, the peripheral portion of the single crystal semiconductor layer is etched for the same reason.

Note that in this embodiment, a structure in which an opening provided in one corner of each of the plurality of single crystal semiconductor layers is provided in each corner of the base substrate 100 (see FIGS. 18A and 18B). However, one embodiment of the disclosed invention is not limited thereto. What is necessary is just to set suitably the arrangement | positioning, the number, size, etc. of the closed area | region formed by an opening part. For example, an opening may be formed in each corner of the adjacent single crystal semiconductor substrate 110 facing each other. In addition, openings are formed in the base substrate at equal intervals, and end portions of a plurality of single crystal semiconductor substrates, for example, (relative to each single crystal semiconductor substrate as shown in FIGS. 18C and 18D). The openings may be arranged so as to be at the same position (here, the upper right corner), and the bonding may be performed so that the bonding proceeds from the end of the single crystal semiconductor substrate facing the opening. As for the arrangement position of the opening at the end of the semiconductor substrate, for example, the opening may be formed in the vicinity of the region where the minute air that is formed in the termination region of bonding is confined. The movement of minute air into the opening can be induced, and the generation of a region where the minute air is confined can be suppressed or eliminated.

Further, for example, an opening may be formed in a region that overlaps a region where a minute air that is planned is trapped. The compressive stress in the opening can be increased by pushing the air in the gap generated by the confinement of minute air into the opening. Thereby, generation | occurrence | production of the area | region where minute air is confined can be suppressed or eliminated. The vicinity of the region where the minute air is confined is a region (dead space) where the bonding strength is insufficient and the semiconductor device is not used. Therefore, by forming an opening in a region which is to be removed later, a wide region of the remaining single crystal semiconductor layer can be secured (see FIGS. 18B and 18D).

In the case where a plurality of single crystal semiconductor substrates are attached to a base substrate, an opening can be formed in the base substrate at a time, so that a process for forming the opening can be simplified.

In this embodiment mode, a plurality of openings formed in the base substrate can be used as alignment markers. For example, an opening can be formed in both the single crystal semiconductor substrate and the base substrate, and bonding can be performed so that the openings overlap with each other, thereby providing a role as an alignment marker.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 7)
In this embodiment mode, a detailed example of a closed region and a separation mechanism of a single crystal semiconductor substrate will be described with reference to FIGS.

FIG. 19 shows an example of a cross section of the substrate in the case of forming an opening (concave portion) for forming a closed region. Note that although the case where an opening is formed on the base substrate 1300 side is described in this embodiment, one embodiment of the disclosed invention is not limited thereto. Similarly, an opening can be formed on the bond substrate side. In this embodiment, the case where an opening is directly formed in a substrate is described; however, one embodiment of the disclosed invention is not limited thereto. For example, the opening may be formed by processing the insulating layer on the substrate surface. Alternatively, a part of the opening may be formed in the substrate surface through the insulating layer.

Examples of the method for forming the opening 1302 include an etching process, a laser light irradiation process, and a scratch forming process using a mechanical means (such as a sharp blade). Needless to say, the opening 1302 can be formed by other methods. Note that the size (depth, etc.) of the opening 1302 can be appropriately set according to the required size of the “closed region”.

Since one embodiment of the invention disclosed in this embodiment is based on the formation of a “closed region formed by the arrangement of openings”, any method can be used as long as this can be realized. It doesn't matter. FIG. 19A shows an example in which an opening having a curvature is formed at the end. FIG. 19B illustrates an example in which a so-called overhang-shaped opening in which the surface side of the base substrate 1300 protrudes is formed. FIG. 19C illustrates an example in which an opening having a tapered shape is formed.

FIG. 20 shows an example of a plan view of a substrate on which an opening for forming a closed region is formed. Note that although the case where an opening is formed on the base substrate 1400 side is described in this embodiment, one embodiment of the disclosed invention is not limited thereto. Similarly, an opening can be formed on the bond substrate side. In this embodiment, the case where an opening is directly formed in a substrate is described; however, one embodiment of the disclosed invention is not limited thereto. For example, the opening may be formed by processing the insulating layer on the substrate surface.

FIG. 20A is a plan view in the case where a circular opening 1402 is formed in the base substrate 1400. The above may be referred to for the method for forming the opening 1402. The size of the opening 1402 (the area in the plan view, etc.) can be appropriately set according to the required size of the “closed region”.

FIG. 20B shows a plan view when the opening 1404 is formed in a triangular shape. The above may be referred to for the method for forming the opening 1404. The size of the opening 1404 (the area in the plan view, etc.) can be appropriately set according to the required size of the “closed region”. Note that although an example in which the triangular opening 1404 is formed is shown here, the number of corners is not particularly limited.

FIG. 20C is a plan view in the case where a rectangular opening 1406 is formed. The above may be referred to for the method for forming the opening 1406. In addition, the size of the concave portion (the area in the plan view) can be appropriately set according to the required size of the “closed region”. Note that although an example in which the rectangular opening 1406 is formed is shown here, the shape of the opening is not limited thereto.

In this embodiment, the above three types of planar shapes are described; however, one embodiment of the disclosed invention is not limited thereto. For example, any planar shape may be used as long as it can realize a “closed region” such as a star shape, a cross shape, an L shape, or the like.

FIG. 21 shows how the semiconductor layers are separated when a closed region is formed.

FIG. 21 illustrates a case where a closed region 1502 is formed by forming an opening as illustrated in FIG. 19A in the base substrate 1500. Note that here, as the structure on the bond substrate side, a structure in which the single crystal semiconductor substrate 1510 includes an embrittled region 1512 and an insulating layer 1514 is formed on the surface is employed. That is, the configuration described in FIG. 21 is similar to the configuration shown in FIGS. Needless to say, one embodiment of the disclosed invention is not necessarily limited to the structure illustrated in FIG. 4 to FIG. 6 or FIG.

FIG. 21A illustrates a state immediately after the base substrate 1500 and the single crystal semiconductor substrate 1510 are bonded to each other. In this state, no great stress is applied to the substrate or the film.

FIG. 21B illustrates the state of stress generated by heat treatment performed after the base substrate 1500 and the single crystal semiconductor substrate 1510 are bonded to each other. As can be seen from FIG. 21B, a large stress is generated on the single crystal semiconductor substrate side in the vicinity of the boundary of the closed region 1502 due to a difference in thermal expansion coefficient between the base substrate 1500 and the single crystal semiconductor substrate 1510. The important point here is to form a closed region by forming an opening. When a large stress is generated at the end of the opening, a crack is likely to occur in a direction relatively perpendicular to the single crystal semiconductor substrate 1510, and separation is likely to proceed. In addition, it is understood that stress is generated on the single crystal semiconductor substrate side even when the gas in the closed region 1502 expands even though the amount is small.

By the generation of such stress, separation of the single crystal semiconductor layer 1516 proceeds with the closed region as a trigger. FIG. 21C illustrates the separation of the single crystal semiconductor layer 1516 from the closed region 1502.

FIG. 22 is a plan view of the relationship between the closed region formed by the arrangement of the opening and the gap formed in the bonding termination region when bonding is performed without forming the opening. Show. FIG. 22 is an enlarged view of a region where the bonding is completed when bonding is progressed from one corner of the single crystal semiconductor substrate 110 when the single crystal semiconductor substrate 110 is bonded to the base substrate 100 as a bond substrate. Indicates.

FIG. 22A shows an example in which the opening 142 is formed in the vicinity of the gap 160. By forming the opening 142 in the vicinity of the gap 160, the gap 160 can be guided into the opening 142 and the generation of the gap can be suppressed. The opening is preferably provided in a region 170 (dead space) where the bonding strength is reduced.

FIG. 22B shows an example in which the opening 142 is formed in a region overlapping with the gap 160. By forming the opening 142 in the overlapping region, the air in the gap 160 can be confined in the opening 142 and the internal stress in the opening 142 can be increased. Thereby, it can be made easy to produce peeling which suppressed surface roughness at lower temperature. Further effects can be obtained by bonding the base substrate and the semiconductor substrate under reduced pressure.

Note that in the case of forming a region that is not pasted by the formation of the opening and is not closed, the stress generated by heat treatment or the like is relieved, so compared with the case of forming the closed region. The effect tends to decrease. In order to make the best use of the effect to form a good semiconductor layer, it is preferable to form a closed region that is not bonded by forming an opening.

Next, the result of confirming the state of stress generated in the substrate using computer simulation is shown (see FIG. 23). Here, a state where the temperature of the entire element considered in the calculation is uniformly 27 ° C. is assumed to be an unstrained and stress-free state, and the temperature of the entire element considered in the calculation is uniformly 500 ° C. The state of stress and deformation was calculated. For the calculation, ANSYS, which is a finite element method analysis software, was used.

As a calculation model, a base substrate having a recess having a depth of 2 μm and a bond substrate (here, a single crystal semiconductor substrate) bonded to each other were used. As a comparative example, the same calculation was performed for a base substrate (flat base substrate) that does not have the concave portion and a bond substrate bonded together. Note that here, parameters of a glass substrate were used as a base substrate, and parameters of a silicon substrate were used as a bond substrate (single crystal semiconductor substrate). Hereinafter, all stresses mean principal stresses.

FIG. 23A shows the state of stress after the heat treatment in the case where the closed region is not formed by not forming the concave portion, and FIG. 23B shows the state of the stress by forming the concave portion. The state of the stress after the heat treatment when the formed region is formed is shown respectively. In the case of forming a closed region, the calculation was performed with the pressure in the region being 3 atm. Moreover, the direction and magnitude of the arrow in the figure indicate the direction and magnitude of the stress related to that point.

FIG. 23A shows that when a closed region is not formed, stress is generated along the interface. Further, FIG. 23B shows that when a closed region is formed, a large stress is generated near the boundary of the closed region. More specifically, when a closed region is formed, strong tensile stress in the oblique direction with respect to the interface is observed near the point where the silicon substrate and the glass substrate are in contact with each other.

In the case where a closed region is not formed, stress acts only along the interface, so that the influence of stress during separation is small. On the other hand, when a closed region is formed due to the formation of the recess, stress acts in an oblique direction with respect to the interface, so that the stress is considered to have a great influence on the separation.

As described above, from the result of computer simulation, it was confirmed that when the closed region is formed, the stress greatly affects the separation of the semiconductor layer. Applying such stress to the separation mechanism is effective for the production of a suitable semiconductor layer.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 8)
In this embodiment mode, details of a method for manufacturing the semiconductor device in the above embodiment mode will be described with reference to FIGS. Here, a method for manufacturing a semiconductor device including a plurality of transistors is described as an example of the semiconductor device. Various semiconductor devices can be formed by using a combination of the transistors described below.

24A is a cross-sectional view illustrating part of a semiconductor substrate manufactured by the method described in Embodiment 1 or the like (see, for example, FIG. 2B). Note that in this embodiment, the case where a semiconductor device is manufactured using the semiconductor substrate manufactured in Embodiment 1 is described; however, it goes without saying that a semiconductor substrate manufactured in another embodiment may be used. Yes.

In the semiconductor layer 700 (corresponding to the single crystal semiconductor layer 118 in FIG. 2B), p-type impurities such as boron, aluminum, and gallium, phosphorus, arsenic, and the like are used to control the threshold voltage of the TFT. An n-type impurity may be added. The region to which the impurity is added and the kind of the impurity to be added can be changed as appropriate. For example, a p-type impurity is added to the formation region of the n-channel TFT, and an n-type impurity is added to the formation region of the p-channel TFT. When the above-described impurities are added, the dose may be set to about 1 × 10 ¹⁵ / cm ² or more and about 1 × 10 ¹⁷ / cm ² or less.

After that, the semiconductor layer 700 is separated into island shapes, so that a semiconductor layer 702 and a semiconductor layer 704 are formed (see FIG. 24B). Note that at this time, it is preferable that the single crystal semiconductor layer 118 in a region corresponding to the peripheral portion (in the vicinity of a region not bonded) be removed (see, for example, FIG. 2C).

Next, a gate insulating film 706 is formed so as to cover the semiconductor layers 702 and 704 (see FIG. 24C). Here, a silicon oxide film is formed as a single layer by a plasma CVD method. In addition to silicon oxide, a film including silicon oxynitride, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like may be formed as the gate insulating film 706 by forming with a single layer structure or a stacked structure.

As a manufacturing method other than the plasma CVD method, a sputtering method or a method using oxidation or nitridation by high-density plasma treatment can be given. The high-density plasma treatment is performed using a mixed gas of a rare gas such as helium, argon, krypton, or xenon and a gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. In this case, high-density plasma can be generated at a low electron temperature by exciting the plasma by introducing a microwave. By oxidizing or nitriding the surface of the semiconductor layer with oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by such high-density plasma, 1 nm or more An insulating film having a thickness of 20 nm or less, preferably 2 nm or more and 10 nm or less is formed so as to be in contact with the semiconductor layer.

Since the oxidation or nitridation of the semiconductor layer by the high-density plasma treatment described above is a solid-phase reaction, the interface state density between the gate insulating film 706, the semiconductor layer 702, and the semiconductor layer 704 can be extremely low. Further, by directly oxidizing or nitriding the semiconductor layer by high-density plasma treatment, variation in the thickness of the formed insulating film can be suppressed. In addition, since the semiconductor layer is a single crystal, a gate insulating film with good uniformity and low interface state density can be obtained even when the surface of the semiconductor layer is oxidized by solid phase reaction using high-density plasma treatment. Can be formed. In this manner, by using the insulating film formed by high-density plasma treatment for part or all of the gate insulating film of the transistor, variation in characteristics can be suppressed.

Alternatively, the gate insulating film 706 may be formed by thermally oxidizing the semiconductor layer 702 and the semiconductor layer 704. Thus, when thermal oxidation is used, it is necessary to use a glass substrate having a certain degree of heat resistance.

Note that a gate insulating film 706 containing hydrogen is formed, and then heat treatment is performed at a temperature of 350 ° C. to 450 ° C., whereby hydrogen contained in the gate insulating film 706 is introduced into the semiconductor layer 702 and the semiconductor layer 704. You may make it diffuse. In this case, as the gate insulating film 706, silicon nitride or silicon nitride oxide using a plasma CVD method can be used. The process temperature is preferably 350 ° C. or lower. In this manner, by supplying hydrogen to the semiconductor layer 702 and the semiconductor layer 704, the interface between the gate insulating film 706 and the semiconductor layer 702 in the semiconductor layer 702, the interface between the gate insulating film 706 and the semiconductor layer 704, and Defects at the interface can be effectively reduced.

Next, after a conductive film is formed over the gate insulating film 706, the conductive film is processed (patterned) into a predetermined shape, whereby the electrode 708 is formed above the semiconductor layer 702 and the electrode 710 is formed above the semiconductor layer 704. (See FIG. 24D). A CVD method, a sputtering method, or the like can be used for forming the conductive film. The conductive film is formed using a material such as tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or niobium (Nb). can do. Alternatively, an alloy material containing the above metal as a main component or a compound containing the above metal may be used. Alternatively, a semiconductor material such as polycrystalline silicon doped with an impurity element imparting conductivity to a semiconductor may be used.

In this embodiment, the electrode 708 and the electrode 710 are formed using a single-layer conductive film; however, the semiconductor device according to one embodiment of the disclosed invention is not limited to this structure. The electrode 708 and the electrode 710 may be formed of a plurality of stacked conductive films. In the case of a two-layer structure, for example, a molybdenum film, a titanium film, a titanium nitride film, or the like may be used as a lower layer, and an aluminum film or the like may be used as an upper layer. In the case of a three-layer structure, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film, a stacked structure of a titanium film, an aluminum film, and a titanium film, or the like may be employed.

Note that a mask used for forming the electrodes 708 and 710 may be formed using a material such as silicon oxide or silicon nitride oxide. In this case, a process of forming a mask by patterning a silicon oxide film, a silicon nitride oxide film, or the like is added. However, in the mask using these materials, the film thickness at the time of etching is reduced compared to the mask using a resist material. Therefore, the electrodes 708 and 710 having more accurate shapes can be formed. Alternatively, the electrode 708 and the electrode 710 may be selectively formed by a droplet discharge method without using a mask. Here, the droplet discharge method means a method of forming a predetermined pattern by discharging or ejecting a droplet containing a predetermined composition, and includes an ink jet method or the like in its category.

In addition, using ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to coil-type electrode, amount of power applied to substrate-side electrode, substrate-side electrode temperature, etc.) The electrode 708 and the electrode 710 can also be formed so as to have a desired taper shape. The taper shape can also be controlled by the shape of the mask. As an etching gas, a chlorine-based gas such as chlorine, boron chloride, silicon chloride, or carbon tetrachloride, a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, or oxygen is appropriately used. Can do.

Next, an impurity element imparting one conductivity type is added to the semiconductor layers 702 and 704 using the electrodes 708 and 710 as masks (see FIG. 25A). In this embodiment, an impurity element imparting n-type conductivity (eg, phosphorus or arsenic) is added to the semiconductor layer 702, and an impurity element imparting p-type conductivity (eg, boron) is added to the semiconductor layer 704. Note that when the impurity element imparting n-type conductivity is added to the semiconductor layer 702, the semiconductor layer 704 to which the p-type impurity is added is covered with a mask or the like, and the addition of the impurity element imparting n-type is selectively performed. To be done. In addition, when an impurity element imparting p-type conductivity is added to the semiconductor layer 704, the semiconductor layer 702 to which an n-type impurity is added is covered with a mask or the like, and the impurity element imparting p-type conductivity is selectively added. To be done. Alternatively, after adding one of an impurity element imparting p-type conductivity or an impurity element imparting n-type to the semiconductor layer 702 and the semiconductor layer 704, an impurity imparting p-type at a higher concentration only to one semiconductor layer The other of the element or the impurity element imparting n-type conductivity may be added. By the addition of the impurities, an impurity region 712 is formed in the semiconductor layer 702 and an impurity region 714 is formed in the semiconductor layer 704.

Next, a sidewall 716 is formed on the side surface of the electrode 708 and a sidewall 718 is formed on the side surface of the electrode 710 (see FIG. 25B). The sidewalls 716 and 718 are formed by, for example, newly forming an insulating film so as to cover the gate insulating film 706, the electrode 708, and the electrode 710, and partially etching the insulating film by anisotropic etching. can do. Note that the gate insulating film 706 may be partially etched by the anisotropic etching described above. As the insulating film for forming the sidewall 716 and the sidewall 718, a film containing silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, an organic material, or the like using a plasma CVD method, a sputtering method, or the like. May be formed in a single layer structure or a laminated structure. In this embodiment, a silicon oxide film with a thickness of 100 nm is formed by a plasma CVD method. As the etching gas, a mixed gas of CHF ₃ and helium can be used. Note that the step of forming the sidewall 716 and the sidewall 718 is not limited to these steps.

Next, an impurity element imparting one conductivity type is added to the semiconductor layers 702 and 704 using the gate insulating film 706, the electrodes 708 and 710, the sidewalls 716 and 718 as masks (FIG. 25C). reference). Note that an impurity element having the same conductivity type as the impurity element added in the previous step is added to the semiconductor layer 702 and the semiconductor layer 704 at a higher concentration. Here, when the impurity element imparting n-type conductivity is added to the semiconductor layer 702, the semiconductor layer 704 to which the p-type impurity is added is covered with a mask or the like, and the addition of the impurity element imparting n-type is selectively performed. To be done. In addition, when an impurity element imparting p-type conductivity is added to the semiconductor layer 704, the semiconductor layer 702 to which an n-type impurity is added is covered with a mask or the like, and the impurity element imparting p-type conductivity is selectively added. To be done.

By the addition of the impurity element, a pair of high-concentration impurity regions 720, a pair of low-concentration impurity regions 722, and a channel formation region 724 are formed in the semiconductor layer 702. In addition, a pair of high-concentration impurity regions 726, a pair of low-concentration impurity regions 728, and a channel formation region 730 are formed in the semiconductor layer 704 by addition of the impurity element. The high concentration impurity region 720 and the high concentration impurity region 726 function as a source or a drain, and the low concentration impurity region 722 and the low concentration impurity region 728 function as an LDD (Lightly Doped Drain) region.

Note that the sidewall 716 formed over the semiconductor layer 702 and the sidewall 718 formed over the semiconductor layer 704 have the same length in the direction in which carriers move (a direction parallel to a so-called channel length). However, they may be formed differently. For example, the sidewall 718 on the semiconductor layer 704 to be a p-channel transistor is formed to have a longer length in the direction in which carriers move than the sidewall 716 on the semiconductor layer 702 to be an n-channel transistor. good. In a p-channel transistor, by increasing the length of the sidewall 718, the short channel effect due to boron diffusion can be suppressed, so that high-concentration boron can be added to the source and drain. . As a result, the resistance of the source and drain can be sufficiently reduced.

In order to further reduce the resistance of the source and drain, a silicide region in which a part of the semiconductor layer 702 and the semiconductor layer 704 is silicided may be formed. Silicidation is performed by bringing a metal into contact with the semiconductor layer and reacting silicon in the semiconductor layer with the metal by heat treatment (eg, GRTA method, LRTA method, etc.). Cobalt silicide or nickel silicide may be formed as the silicide region. When the semiconductor layer 702 or the semiconductor layer 704 is thin, the silicide reaction may be advanced to the bottom of the semiconductor layer 702 or the semiconductor layer 704. Metal materials that can be used for silicidation include titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), hafnium (Hf), and tantalum (Ta). ), Vanadium (V), neodymium (Nd), chromium (Cr), platinum (Pt), palladium (Pd), and the like. Further, the silicide region can also be formed by laser light irradiation or the like.

Through the above steps, an n-channel transistor 732 and a p-channel transistor 734 are formed. Note that although a conductive film functioning as a source electrode or a drain electrode is not formed in the stage illustrated in FIG. 25C, the conductive film functioning as the source electrode or the drain electrode may be referred to as a transistor. .

Next, an insulating film 736 is formed so as to cover the n-channel transistor 732 and the p-channel transistor 734 (see FIG. 25D). Although the insulating film 736 is not necessarily provided, the formation of the insulating film 736 can prevent impurities such as an alkali metal and an alkaline earth metal from entering the n-channel transistor 732 and the p-channel transistor 734. Specifically, the insulating film 736 is preferably formed using a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, or aluminum oxide. In this embodiment, a silicon nitride oxide film with a thickness of about 600 nm is used as the insulating film 736. In this case, the above-described hydrogenation step may be performed after the silicon nitride oxide film is formed. Note that although the insulating film 736 has a single-layer structure in this embodiment, it is needless to say that a stacked structure may be used. For example, in the case of a two-layer structure, a stacked structure of a silicon oxynitride film and a silicon nitride oxide film can be used.

Next, an insulating film 738 is formed over the insulating film 736 so as to cover the n-channel transistor 732 and the p-channel transistor 734. The insulating film 738 is preferably formed using a heat-resistant organic material such as polyimide, acrylic, benzocyclobutene, polyamide, or epoxy. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, PSG (phosphorus glass), BPSG (phosphorus boron glass) Alumina or the like can also be used. Here, the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may have one selected from fluorine, an alkyl group, and an aromatic hydrocarbon in addition to hydrogen as a substituent. Note that the insulating film 738 may be formed by stacking a plurality of insulating films formed using these materials.

For the formation of the insulating film 738, CVD method, sputtering method, SOG method, spin coating, dipping, spray coating, droplet discharge method (ink jet method, screen printing, offset printing, etc.), doctor knife, A roll coater, curtain coater, knife coater, or the like can be used.

Next, contact holes are formed in the insulating film 736 and the insulating film 738 so that the semiconductor layer 702 and part of the semiconductor layer 704 are exposed. Then, a conductive film 740 and a conductive film 742 which are in contact with the semiconductor layer 702 through the contact holes, and a conductive film 744 and a conductive film 746 which are in contact with the semiconductor layer 704 are formed (see FIG. 26A). The conductive film 740, the conductive film 742, the conductive film 744, and the conductive film 746 function as a source electrode or a drain electrode of the transistor. In the present embodiment, a mixed gas of CHF ₃ and He is used as a gas used for etching when the contact hole is opened. However, the present invention is not limited to this.

The conductive film 740, the conductive film 742, the conductive film 744, and the conductive film 746 can be formed by a CVD method, a sputtering method, or the like. Materials include aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or the like can be used. Alternatively, an alloy containing the above material as its main component or a compound containing the above material may be used. The conductive film 740, the conductive film 742, the conductive film 744, and the conductive film 746 may have a single-layer structure or a stacked structure.

As an example of an alloy containing aluminum as a main component, an alloy containing aluminum as a main component and containing nickel can be given. Further, examples include aluminum as a main component and one or both of nickel and carbon or silicon. Aluminum and aluminum silicon (Al—Si) have low resistance and are inexpensive, and thus are suitable as materials for forming the conductive films 740, 742, 744, and 746. In particular, aluminum silicon is preferable because generation of hillocks due to resist baking during patterning can be suppressed. Further, instead of silicon, a material in which about 0.5% Cu is mixed in aluminum may be used.

In the case where the conductive film 740, the conductive film 742, the conductive film 744, and the conductive film 746 have a stacked structure, for example, a stacked structure of a barrier film, an aluminum silicon film, and a barrier film, a barrier film, an aluminum silicon film, and a titanium nitride film A laminated structure of barrier films may be employed. Note that a barrier film is a film formed using titanium, titanium nitride, molybdenum, molybdenum nitride, or the like. When a conductive film is formed so that an aluminum silicon film is sandwiched between barrier films, generation of hillocks of aluminum or aluminum silicon can be further prevented. In addition, when a barrier film is formed using titanium which is a highly reducing element, even if a thin oxide film is formed over the semiconductor layer 702 and the semiconductor layer 704, titanium contained in the barrier film forms the oxide film. By reduction, the contact between the conductive films 740 and 742 and the semiconductor layer 702 and the contact between the conductive films 744 and 746 and the semiconductor layer 704 can be favorable. Alternatively, a plurality of barrier films may be stacked. In that case, for example, the conductive films 740 to 746 can have a five-layer structure or a stacked structure of more layers such as titanium, titanium nitride, aluminum silicon, titanium, and titanium nitride from the lower layer.

Alternatively, tungsten silicide formed by a chemical vapor deposition method using WF ₆ gas and SiH ₄ gas may be used for the conductive films 740, 742, 744, and 746. Alternatively, tungsten formed by hydrogen reduction of WF ₆ may be used for the conductive films 740, 742, 744, and 746.

Note that the conductive films 740 and 742 are connected to the high-concentration impurity regions 720 of the n-channel transistor 732. The conductive films 744 and 746 are connected to the high concentration impurity region 726 of the p-channel transistor 734.

FIG. 26B is a plan view of the n-channel transistor 732 and the p-channel transistor 734 illustrated in FIG. Here, a cross section taken along line AB in FIG. 26B corresponds to FIG. Note that in FIG. 26B, the insulating film 736, the insulating film 738, the conductive film 740, the conductive film 742, the conductive film 744, the conductive film 746, and the like are omitted for simplicity.

Note that in this embodiment, the case where the n-channel transistor 732 and the p-channel transistor 734 each have one electrode functioning as a gate electrode (when the electrode 708 and the electrode 710 are included) is illustrated. However, one embodiment of the disclosed invention is not limited to the structure. The transistor may have a multi-gate structure in which a plurality of electrodes functioning as gate electrodes are provided and the plurality of electrodes are electrically connected.

In this embodiment mode, an SOI substrate having a good semiconductor layer in which surface roughness is suppressed by effectively using a dead space formed in a region where bonding is terminated or a region near the region is used. The yield of the apparatus can be improved. In addition, a reduction in the area that can be used as an SOI substrate can be suppressed. Note that the structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

In this example, experimental results obtained by observing the surface state of the SOI layer depending on whether or not an opening is formed are shown. Hereinafter, the results will be described with reference to the drawings.

As a sample, a glass substrate provided with a silicon layer separated from a single crystal silicon substrate (before laser light irradiation) was prepared. Specifically, a sample (sample A) that was bonded without forming an opening, a sample (sample B) that formed a closed region by scratching (opening) a glass substrate with a glass pen, Three types of samples (sample C) were prepared in which a closed area was formed by scratching (opening) the glass substrate by laser irradiation. The details of the sample manufacturing method are the same as those in the second embodiment. Here, after the silicon layer is separated, the surface of the silicon layer is subjected to etching treatment, and then laser light is irradiated. Sample A can be produced by not forming an opening.

27, 28, and 29 show the state of the surface of the silicon layer immediately after the 5-inch single crystal silicon substrate is separated and a silicon layer is formed on the glass substrate. 27 shows the state of the sample A, FIG. 28 shows the state of the sample B, and FIG. 29 shows the state of the sample C. FIGS. 27B, 28B, and 29B are partially enlarged photographs (micrographs) of FIGS. 27A, 28A, and 29A, respectively.

In Sample B and Sample C, a closed region formed by the opening was formed in the lower right part of the figure (corner: a part surrounded by a broken circle in the figure) (FIG. 28A). FIG. 29 (A)). In each of FIGS. 27A, 28A, and 29A, the glass substrate and the single crystal silicon substrate are partially bonded in the lower right corner region of the drawing, and the upper left direction is reached. The pasting was advanced to complete the pasting. In any of Sample A, Sample B, and Sample C, it was confirmed that a region in which minute air was confined was formed as indicated by a black dot in the bonding termination region at the upper left of the drawing.

27B, 28B, and 29B, the sample (sample B and sample C) in which the closed region is formed by forming the opening (sample B, sample C) does not form the opening ( It can be seen that the surface roughness of the silicon layer is suppressed compared to sample A).

Next, FIG. 30A and FIG. 30B show the relationship between the diameter of the closed region formed by the arrangement of the opening and the number of defects (detection number) in the silicon layer. Here, the number of detections refers to the number of defects having a diameter of 1 μm or more detected by a pattern inspection machine. The pattern inspection machine is an apparatus applying an optical microscope and image analysis.

FIG. 30 shows that the number of detected defects is reduced as the diameter of the closed region provided by forming the opening is increased. Further, when compared with a case where no opening is formed (when the diameter of the non-bonded region due to the formation of the opening is 0 mm), the closed region due to the formation of the opening is small (for example, the diameter of the closed region). Even when the value is 1 mm), the number of detections is significantly reduced. From this, it can be seen that forming the closed region by forming the opening is extremely effective for suppressing the defect of the silicon layer.

FIG. 31 and FIG. 32 show the results of comparing the roughness of the surface of the sample that does not form the closed region due to the formation of the opening and the roughness of the surface of the sample that forms the closed region due to the formation of the opening. Show. FIG. 31 (A) shows the arithmetic average roughness (Ra), FIG. 31 (B) shows the maximum height difference (P−V), and FIG. 32 shows the root mean square roughness (RMS).

From FIG. 31A, there is a sample in which Ra is larger than 7.0 nm among samples that do not form a closed region due to the formation of the opening, whereas a sample in which the closed region is formed due to the formation of the opening. Then, it can be seen that Ra is 6.0 nm or less. In addition, as shown in FIG. 31B, a sample that does not form a closed region due to the formation of the opening has a PV of greater than 150 nm, whereas a closed region due to the formation of the opening is formed. It can be seen that P-V is 150 nm or less in the obtained sample. Further, from FIG. 32, there is a sample in which the RMS is larger than 10 nm in the sample that does not form the closed region due to the formation of the opening, whereas the RMS in the sample in which the closed region is formed due to the formation of the opening. It turns out that it is 10 nm or less.

As described above, the effectiveness of one embodiment of the disclosed invention has been confirmed by this example. Specifically, in this example, the number density of defects in the semiconductor layer, 5 pieces / cm ² or less, was achieved. Note that in one embodiment of the disclosed invention, the number of defects in a semiconductor layer can be sufficiently suppressed, so that an increase in the number of defects and an increase in size of defects are suppressed even when laser light is irradiated later. It is possible. Thus, one embodiment of the disclosed invention is very effective when used in combination with laser light irradiation. In this embodiment, an example in which a closed region is formed by forming an opening at the bonding start position has been described. A region that has been a dead space in the past by forming the closed region in a region where bonding is completed (a region in which minute air formed without forming an opening is confined or in the vicinity of the region) It is possible to suppress the surface roughness while effectively utilizing.

In this example, the effect of the modification was confirmed. Hereinafter, the results will be described with reference to the drawings.

Samples that did not form a closed region due to the formation of the opening (1 sample) and samples that formed a closed region by scratching the glass substrate by laser irradiation (2 samples) were prepared. . The details of the sample manufacturing method are the same as those in the second embodiment. Note that the sample is irradiated with laser light without etching the surface of the silicon layer after the silicon layer is separated.

FIG. 33 shows the number of defects in the silicon layer for the sample. Here, the number of detections refers to the number of defects having a diameter of 1 μm or more detected by a pattern inspection machine. The pattern inspection machine is an apparatus applying an optical microscope and image analysis.

FIG. 33 shows that the number of defects detected is significantly reduced in the sample in which the closed region is formed by the formation of the opening. From this, it can be seen that the formation of the closed region by the formation of the opening is extremely effective for suppressing defects in the silicon layer.

In this embodiment, since the laser beam is irradiated on the surface of the silicon layer without performing the etching process, the silicon layer is compared with the case where the laser beam is irradiated after the etching process is performed on the surface of the silicon layer. The laser beam is irradiated in a thick state. For this reason, it is possible to further reduce the number of defects. Specifically, in this example, the number density of defects in the semiconductor layer, 1 / cm ² or less, was achieved. Thus, one embodiment of the disclosed invention is very effective when used in combination with laser light irradiation.

100 base substrate 102 nitrogen-containing layer 110 single crystal semiconductor substrate 112 embrittled region 114 insulating layer 115 oxide film 116 single crystal semiconductor layer 118 single crystal semiconductor layer 120 semiconductor layer 126 peripheral portion 128 region 129 region 132 laser light 140 opening 142 opening Portion 144 Opening 146 Peripheral portion 150 Bonding start region 160 Void 170 Region 180 Single crystal semiconductor substrate 700 Semiconductor layer 702 Semiconductor layer 704 Semiconductor layer 706 Gate insulating film 708 Electrode 710 Electrode 712 Impurity region 714 Impurity region 716 Side wall 718 Side wall 720 High concentration impurity region 722 Low concentration impurity region 724 Channel formation region 726 High concentration impurity region 728 Low concentration impurity region 730 Channel formation region 732 n channel transistor 734 p channel type Transistor 736 insulating film 738 insulating film 740 conductive film 742 conductive film 744 conductive film 746 conductive film 1300 base substrate 1302 opening 1400 base substrate 1402 opening 1404 opening 1406 opening 1500 base substrate 1502 region 1510 single crystal semiconductor substrate 1512 embrittlement Region 1514 Insulating layer 1516 Single crystal semiconductor layer 1600 Base substrate 1602 Region 1610 Single crystal semiconductor substrate 1612 Embrittlement region 1614 Insulating layer 1616 Single crystal semiconductor layer

Claims (14)

Irradiating the bond substrate with ions to form an embrittled region in the bond substrate,
Forming an opening in the surface of the bond substrate or base substrate;
When the bond substrate and the base substrate are bonded together with an insulating layer interposed therebetween, the bonding is advanced from one end of the four corners of the bond substrate, and the opening is formed in the other end region facing the one end. A region where the base substrate and the bond substrate are not bonded to each other by disposing a portion, and an outer periphery is closed by the base substrate and the bond substrate;
A method for manufacturing an SOI substrate, comprising performing heat treatment to separate the bond substrate in the embrittled region and form a semiconductor layer over the base substrate. Irradiating ions to a substantially rectangular bond substrate to form an embrittled region in the bond substrate,
Forming an opening in the surface of the bond substrate or base substrate;
When the bond substrate and the base substrate are bonded to each other with an insulating layer interposed therebetween, the bonding proceeds from one corner of the bond substrate, and the opening is formed at the other corner facing the corner. Forming a region where the base substrate and the bond substrate are not bonded to each other, and an outer periphery is closed by the base substrate and the bond substrate,
A method for manufacturing an SOI substrate, comprising performing heat treatment to separate the bond substrate in the embrittled region and form a semiconductor layer over the base substrate. Forming an insulating layer on the bond substrate;
Irradiating the bond substrate with ions to form an embrittled region in the bond substrate,
Forming a nitrogen-containing layer on the base substrate;
Forming an opening in the surface of the base substrate on which the nitrogen-containing layer is formed;
When the bond substrate and the base substrate are bonded to each other with the insulating layer and the nitrogen-containing layer interposed therebetween, the bonding proceeds from one corner of the bond substrate, and the other facing the corner By forming the opening at the corner, the base substrate and the bond substrate are not bonded to each other, and the outer periphery is closed by the base substrate and the bond substrate,
A method for manufacturing an SOI substrate, comprising performing heat treatment to separate the bond substrate in the embrittled region and form a semiconductor layer over the base substrate. Forming an insulating layer on the bond substrate;
Irradiating the bond substrate with ions to form an embrittled region in the bond substrate,
Forming an opening on the surface of the base substrate,
Forming a nitrogen-containing layer on the base substrate in which the opening is formed;
When the bond substrate and the base substrate are bonded to each other with the insulating layer and the nitrogen-containing layer interposed therebetween, the bonding proceeds from one corner of the bond substrate, and the other facing the corner By forming the opening at the corner, the base substrate and the bond substrate are not bonded to each other, and the outer periphery is closed by the base substrate and the bond substrate,
A method for manufacturing an SOI substrate, comprising performing heat treatment to separate the bond substrate in the embrittled region and form a semiconductor layer over the base substrate. Forming an insulating layer on a plurality of bond substrates;
Irradiating the plurality of bond substrates with ions to form embrittled regions in the plurality of bond substrates,
Forming a nitrogen-containing layer on the base substrate;
Forming a plurality of openings on the surface of the base substrate on which the nitrogen-containing layer is formed;
When the plurality of bond substrates and the base substrate are bonded to each other with the insulating layer and the nitrogen-containing layer interposed therebetween, the bonding proceeds from one corner of each of the plurality of bond substrates, and the corners The base substrate and the plurality of bond substrates are not bonded to each other by disposing one of the plurality of openings at other corners facing the portion, and the base substrate and the plurality Each of which has an outer periphery closed by the bond substrate,
A method for manufacturing an SOI substrate, comprising performing heat treatment to separate the plurality of bond substrates in the embrittled region and to form a plurality of semiconductor layers over the base substrate. Forming an insulating layer on a plurality of bond substrates;
Irradiating the plurality of bond substrates with ions to form embrittled regions in the plurality of bond substrates,
A plurality of openings are formed on the surface of the base substrate,
Forming a nitrogen-containing layer on the base substrate in which the plurality of openings are formed;
When the plurality of bond substrates and the base substrate are bonded to each other with the insulating layer and the nitrogen-containing layer interposed therebetween, the bonding proceeds from one corner of each of the plurality of bond substrates, and the corners The base substrate and the plurality of bond substrates are not bonded to each other by disposing one of the plurality of openings at other corners facing the portion, and the base substrate and the plurality Each of which has an outer periphery closed by the bond substrate,
A method for manufacturing an SOI substrate, comprising performing heat treatment to separate the plurality of bond substrates in the embrittled region and to form a plurality of semiconductor layers over the base substrate. In any one of Claims 1 thru | or 6,
A method for manufacturing an SOI substrate, in which by performing the heat treatment, stress is generated in the vicinity of the non-bonded region and the closed region in the bond substrate to promote separation of the bond substrate. In any one of Claims 1 thru | or 7,
A method for manufacturing an SOI substrate, wherein an area of the non-bonded region and the closed region is 1.0 mm ² or more. In any one of Claims 1 thru | or 8,
A method for manufacturing an SOI substrate, in which the semiconductor layer is irradiated with laser light. In any one of Claims 1 thru | or 9,
A method for manufacturing an SOI substrate, wherein the temperature of the heat treatment is 500 ° C. or lower. In any one of Claims 1 thru | or 9,
A method for manufacturing an SOI substrate, wherein the heat treatment is performed at a temperature of 500 ° C. or less, the bond substrate is separated in the embrittled region, and subsequently, a heat treatment is performed at a temperature of 500 ° C. to 800 ° C. In any one of Claims 1 thru | or 11,
The method for manufacturing an SOI substrate, wherein the base substrate is a glass substrate. In any one of Claims 1 thru | or 11,
The method for manufacturing an SOI substrate, wherein the base substrate has a thermal expansion coefficient different from that of the bond substrate by 10% or more. An SOI substrate in which the number density of defects in the semiconductor layer is set to 1 piece / cm ² or less by using the manufacturing method according to claim 1.