JP5669439B2 - Method for manufacturing semiconductor substrate - Google Patents

Description

The present invention relates to a semiconductor thin film substrate and a method for manufacturing a semiconductor device using the semiconductor thin film substrate.

When a photoelectric conversion element (for example, an optical sensor) is formed on a glass substrate, polycrystalline silicon may be used as a semiconductor layer that performs photoelectric conversion (for example, see Patent Document 1). Since polycrystalline silicon can be formed by a low-temperature process, it has an advantage that it can be easily formed on a substrate having low heat resistance such as a glass substrate.

Japanese Patent Laid-Open No. 10-79522

However, among the photoelectric conversion elements, those using polycrystalline silicon as the photoelectric conversion layer tend to have a larger dark current than those using single crystal silicon as the photoelectric conversion layer. Another problem is that carriers are trapped due to the presence of defects and the current during light irradiation is reduced. For this reason, when using polycrystalline silicon, it was difficult to produce a photoelectric conversion element having sufficient photosensitivity.

In order to manufacture a photoelectric conversion element having sufficient photosensitivity, for example, there is a method of forming a photoelectric conversion element using a thick semiconductor layer. However, when a device not suitable for a thick film is also formed on the same substrate, it is necessary to make a device suitable for a thick film and a device suitable for a thin film. Therefore, the device manufacturing process increases, and problems such as an increase in cost and time, a decrease in productivity, and a yield may be caused.

In view of the above problems, an object of one embodiment of the present invention is to provide a semiconductor thin film substrate including semiconductor layers having different thicknesses from one semiconductor layer.

Another object is to provide a semiconductor device having a photoelectric conversion element with good characteristics to which the semiconductor thin film substrate is applied.

In one embodiment of the present invention, semiconductor layers having different thicknesses are formed from one semiconductor layer. In addition, a semiconductor device including a photoelectric conversion element with high photosensitivity is formed. More details are as follows.

In one embodiment of the present invention, a semiconductor layer is formed over a substrate, the semiconductor layer is processed to form a first island-shaped semiconductor layer and a second island-shaped semiconductor layer, and the first island-shaped semiconductor layer is formed In this method, the first island-shaped semiconductor layer is melted by laser irradiation to form a third island-shaped semiconductor layer having a thickness larger than that of the second island-shaped semiconductor layer.

Another embodiment of the present invention is to irradiate a semiconductor substrate with accelerated ions to form an embrittled region in the semiconductor substrate, bond the semiconductor substrate and the substrate through an insulating layer, and perform heat treatment in the embrittled region. The semiconductor substrate is separated, a semiconductor layer is formed on the substrate, the semiconductor layer is processed to form a first island-shaped semiconductor layer and a second island-shaped semiconductor layer, and a laser is applied to the first island-shaped semiconductor layer. In this method, the first island-shaped semiconductor layer is melted by irradiation to form a third island-shaped semiconductor layer having a thickness larger than that of the second island-shaped semiconductor layer.

By irradiating the first island-shaped semiconductor layer with laser, the first island-shaped semiconductor layer is melted and aggregated on the insulating layer to form a curved surface at the upper end portion. The aggregated third island-shaped semiconductor layer can have a thickness two to four times that of the second island-shaped semiconductor layer.

The second island-shaped semiconductor layer preferably has a thickness of 140 nm or less.

The planar shape of the first island-shaped semiconductor layer when the substrate is viewed from above is such that the ratio of the length of the short side to the long side is 1: x (x is a number greater than 1), and The length of the short side is preferably 10 μm or less.

The first island-shaped semiconductor layer and the second island-shaped semiconductor layer can be a single crystal semiconductor, a polycrystalline semiconductor, an amorphous semiconductor, or the like.

For the insulating layer, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide can be used.

Another embodiment of the present invention is to prepare a substrate having a semiconductor layer with an insulating layer interposed therebetween, process the semiconductor layer, and form a first island-shaped semiconductor layer and a second island-shaped semiconductor layer. The first island-shaped semiconductor layer is melted by irradiating the island-shaped semiconductor layer with a laser to form a third island-shaped semiconductor layer having a thickness larger than that of the second island-shaped semiconductor layer. A semiconductor region that performs photoelectric conversion by selectively adding a first impurity element and a second impurity element to the island-shaped semiconductor layer, a semiconductor region that exhibits the first conductivity type, and a semiconductor region that exhibits the second conductivity type And forming a first electrode electrically connected to the semiconductor region exhibiting the first conductivity type and a second electrode electrically connected to the semiconductor region exhibiting the second conductivity type. A conversion element is formed, and the first impurity element or the first impurity element is selectively formed on the second island-shaped semiconductor layer; An impurity element is added to form a channel formation region, a source region, and a drain region, a gate insulating film is formed over the second island-shaped semiconductor layer, a gate electrode is formed over the gate insulating film, and the source region A method for manufacturing a semiconductor device in which a transistor is formed by forming a source electrode electrically connected to a drain electrode and a drain electrode electrically connected to a drain region.

By irradiating the first island-shaped semiconductor layer with laser, the first island-shaped semiconductor layer aggregates on the insulating layer and forms a curved surface at the upper end portion. The aggregated third island-shaped semiconductor layer can have a thickness two to four times that of the second island-shaped semiconductor layer.

The second island-shaped semiconductor layer preferably has a thickness of 140 nm or less.

The planar shape of the first island-shaped semiconductor layer when the substrate is viewed from above is such that the ratio of the length of the short side to the long side is 1: x (x is a number greater than 1), and The length of the short side is preferably 10 μm or less.

As the first island-shaped semiconductor layer and the second island-shaped semiconductor layer, layers such as a single crystal semiconductor, a polycrystalline semiconductor, and an amorphous semiconductor can be used.

As the insulating layer, a layer containing a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide can be used.

According to one embodiment of the present invention, semiconductor layers having different thicknesses are formed from one semiconductor layer by irradiating the island-shaped semiconductor layers having different areas with laser light. For this reason, the semiconductor thin film substrate which has a semiconductor layer from which film thickness differs can be provided.

In one embodiment of the present invention, a photoelectric conversion element is formed using a thick semiconductor layer. For this reason, the semiconductor device which has a photoelectric conversion element with high photosensitivity can be provided.

It is sectional drawing which shows an example of the manufacturing method of the semiconductor thin film substrate used for a semiconductor device. 2A and 2B are a cross-sectional view and a perspective view illustrating an example of a semiconductor device. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. It is sectional drawing which shows an example of the manufacturing method of the semiconductor thin film substrate used for a semiconductor device. It is sectional drawing which shows an example of the manufacturing method of the semiconductor thin film substrate used for a semiconductor device.

Hereinafter, embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the description of the embodiments described below, and it is obvious to those skilled in the art that modes and details can be variously changed without departing from the spirit of the invention disclosed in this specification and the like. . In addition, structures according to different embodiments can be implemented in appropriate combination. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

Note that the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

(Embodiment 1)
In this embodiment, an example of a method for manufacturing a semiconductor thin film substrate will be described with reference to FIGS.

First, the substrate 105 including the semiconductor layer 118 is formed over the substrate 100 with the insulating layer 114 interposed therebetween (see FIG. 1A).

As the substrate 100, a light-transmitting glass substrate used in a liquid crystal display device or the like can be used. A glass substrate having a strain point of 580 ° C. or higher (preferably 600 ° C. or higher) is preferably used. The glass substrate is preferably an alkali-free glass substrate. For the alkali-free glass substrate, for example, a glass material such as aluminosilicate glass, aluminoborosilicate glass, or barium borosilicate glass can be used.

As the substrate 100, for example, a single crystal semiconductor substrate made of a Group 14 element such as silicon, germanium, silicon germanium, or silicon carbide can be used. A compound semiconductor substrate such as gallium arsenide or indium phosphide can also be used.

When a semiconductor substrate is used as the substrate 100, the size of the substrate 100 is not limited. For example, a semiconductor substrate having a diameter of 8 inches (200 mm), 12 inches (300 mm), 18 inches (450 mm), or the like is used. Can do. Further, a circular semiconductor substrate may be processed into a rectangular shape.

In addition to the single crystal semiconductor substrate and the glass substrate, the substrate 100 can be a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate, or a substrate made of a conductor such as metal or stainless steel. In this embodiment, the case where a glass substrate is used as the substrate 100 will be described.

The insulating layer 114 can be formed by a thermal oxidation method, a CVD method, a sputtering method, or the like. The insulating layer 114 can be formed with a single layer structure or a stacked layer structure using a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide.

As the semiconductor layer 118, for example, a single crystal semiconductor layer made of a Group 14 element such as silicon, germanium, or silicon germanium can be used. In the case where the single crystal semiconductor layer is used for the semiconductor layer 118, an impurity element such as a donor element or an acceptor element for controlling the resistance value may be added. Alternatively, a compound semiconductor layer such as gallium arsenide or indium phosphide can be used. In addition to a single crystal semiconductor layer, a polycrystalline semiconductor layer, an amorphous semiconductor layer, or the like can be used. Note that in this embodiment, the case where a single crystal silicon layer is used as the semiconductor layer 118 is described.

Next, a mask 400 and a mask 401 are formed over the semiconductor layer 118, and the semiconductor layer 118 is selectively etched using the mask 400 and the mask 401, whereby the first island-shaped semiconductor layer 120 and the second island-shaped semiconductor layer 121 are formed. (See FIG. 1B).

The mask 400 and the mask 401 can be formed by photolithography using a resist material. The etching process can be either a wet etching process or a dry etching process.

Further, the planar shape of the first island-shaped semiconductor layer 120 when the substrate is viewed from above has a ratio of the length of the short side to the long side of 1: x (x is a number greater than 1) and is short. The side length is preferably 10 μm or less. Further, when the length of the short side of the first island-shaped semiconductor layer 120 is, for example, 1 μm or more and 10 μm or less, the first island-shaped semiconductor layer 120 is melted and aggregated by laser irradiation to increase the film thickness. . In addition, the planar shape of the second island-shaped semiconductor layer 121 when the substrate is viewed from above has a ratio of the length of the short side to the long side of 1: x (x is a number greater than 1) and is short. The length of the side can be 10 μm or more, for example, preferably 20 μm or more.

In this embodiment, two island-like semiconductor layers having different areas, that is, the first island-like semiconductor layer 120 and the second island-like semiconductor layer 121 are formed from the semiconductor layer 118; Is not limited thereto, and three or more island-like semiconductor layers having different areas may be formed.

Next, at least the first island-shaped semiconductor layer 120 is irradiated with laser light 130 (see FIG. 1C). The first island-shaped semiconductor layer 120 is melted by being irradiated with the laser beam 130, and surface tension is generated by melting. The first island-shaped semiconductor layer 120 can be agglomerated on the insulating layer 114 due to the surface tension, and the upper surface end portion can be a mold having a curved surface. Further, the first island-shaped semiconductor layer 120 is aggregated, so that the first island-shaped semiconductor layer 200 having a thickness larger than that of the first island-shaped semiconductor layer 120 can be obtained. The first island-shaped semiconductor layer 200 can be thicker than the second island-shaped semiconductor layer 121 (see FIGS. 1D and 1E). Note that FIG. 1E is a perspective view of FIG.

Further, the film thickness of the first island-shaped semiconductor layer 200 and the length of the short side of the first island-shaped semiconductor layer 200 are the film thickness of the first island-shaped semiconductor layer 120 and the first island-shaped semiconductor layer 120. And the wettability between the first island-shaped semiconductor layer 120 and the insulating layer 114, and the like. These parameters are determined by the patterning method of the first island-shaped semiconductor layer 120, the wettability between the first island-shaped semiconductor layer 120 and the insulating layer 114, the surface tension, the type of laser, and the scanning method. For example, the first island-shaped semiconductor layer 120 having a film thickness of 140 nm and a short side length of 3.3 μm is formed over the insulating layer 114 formed of silicon oxide and having low wettability, and is irradiated with the laser light 130. Thus, the first island-shaped semiconductor layer 200 having a film thickness of 550 nm and a short side length of 2.5 μm can be formed. Note that the first island-shaped semiconductor layer 200 having a larger thickness can be formed by variously changing the thickness of the first island-shaped semiconductor layer 120, the energy of laser irradiation, and the like.

The first island-shaped semiconductor layer 200 can have a film thickness that is two to four times that of the second island-shaped semiconductor layer 121, for example. Note that since the first island-shaped semiconductor layer 120 aggregates on the insulating layer 114 and the film thickness increases, the volume of the first island-shaped semiconductor layer 120 and the volume of the first island-shaped semiconductor layer 200 do not change. .

In this embodiment mode, it has been described that the irradiation with the laser beam 130 is performed on the first island-shaped semiconductor layer 120; however, the present invention is not limited to this. The first island-shaped semiconductor layer 120 and the second island-shaped semiconductor layer 121 may be irradiated with the laser beam 130. When the short side of the second island-shaped semiconductor layer 121 is formed to be longer than the short side of the first island-shaped semiconductor layer 120, even if the second island-shaped semiconductor layer 121 is irradiated with the laser beam 130, The second island-shaped semiconductor layer 121 is not aggregated like the first island-shaped semiconductor layer 120.

Moreover, when irradiating the laser beam 130 using a pulse laser, the number of times the island-like semiconductor layer is melted by irradiating the pulse laser beam can be selected by the number of pulses of the irradiated pulse laser beam. It can be performed 1 to 100 times. Moreover, 3 times or more and 20 times or less are preferable. Note that by performing three or more times, the first island-shaped semiconductor layer 120 can be melted and aggregated to increase the film thickness.

In addition, a pulsed laser capable of obtaining high energy is preferably used for irradiation with the laser light 130. The oscillation frequency is preferably 1 Hz or more and 10 MHz or less, but need not be limited to this. As an oscillator of the above-mentioned pulsed laser, Ar laser, Kr laser, excimer (ArF, KrF, XeCl) laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ There are O ₃ laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, gold vapor laser and the like. If continuous melting is possible, a continuous wave laser may be used. As the oscillator of the continuous wave laser, Ar laser, Kr laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, ruby laser, alexandrite laser, Ti: There are sapphire laser, helium cadmium laser and the like.

Further, as the wavelength of the laser beam 130, it is necessary to select at least a wavelength that is absorbed by the first island-shaped semiconductor layer 120. The wavelength may be determined in consideration of the skin depth of the laser light. For example, it can be in the range of 250 nm to 700 nm. The energy density of the laser beam 130 can be determined in consideration of the wavelength of the laser beam 130, the skin depth of the laser beam, the film thickness of the first island-shaped semiconductor layer 120, and the like. The energy density of the laser beam 130 may be in the range of 300 mJ / cm ² or more and 800 mJ / cm ² or less, for example. The range of the energy density is an example when a XeCl excimer laser (wavelength: 308 nm) is used as a pulsed laser.

The irradiation with the laser beam 130 can be performed in an atmosphere containing oxygen such as an air atmosphere or an inert atmosphere such as a nitrogen atmosphere or an argon atmosphere. In order to irradiate the laser beam 130 in an inert atmosphere, the laser beam 130 may be irradiated in an airtight chamber and the atmosphere in the chamber may be controlled. In the case where a chamber is not used, an inert atmosphere can be formed by spraying an inert gas such as nitrogen gas on the surface to be irradiated with the laser light 130.

Note that although the case where a single crystal silicon layer is used as the semiconductor layer 118 is described in this embodiment, one embodiment of the present invention is not limited thereto. For example, when an amorphous silicon layer is used as the semiconductor layer 118, at least the first island-shaped semiconductor layer 120 is irradiated with laser light after the first island-shaped semiconductor layer and the second island-shaped semiconductor layer are formed. Thus, the first island-shaped semiconductor layer 200 which is a crystalline silicon layer can be obtained.

Through the above steps, an island-shaped semiconductor layer having a different area is formed over the substrate 100 from the substrate 105 including the semiconductor layer 118 with the insulating layer 114 interposed therebetween, and laser irradiation is performed, so that the first thickness is different. A semiconductor thin film substrate 600 having the island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 can be formed. By using this embodiment mode, a manufacturing process for a thick semiconductor layer and a thin semiconductor layer does not need to be separately formed; therefore, the manufacturing process can be reduced, and cost and time can be reduced. Further, by forming a thick semiconductor layer and a thin semiconductor layer on the same substrate, for example, a device suitable for a thick film and a device suitable for a thin film can be manufactured.

(Embodiment 2)
In this embodiment, an example of a method for manufacturing a semiconductor device using the semiconductor thin film substrate described in the above embodiment will be described with reference to FIGS. Specifically, a method for manufacturing the photoelectric conversion element 180, the n-type transistor 380, and the p-type transistor 385 illustrated in FIGS. 2A and 2B will be described. Here, FIG. 2B corresponds to a cross-sectional view taken along a line AB in FIG. 2A and a cross-sectional view taken along a line CD in FIG.

As shown in FIGS. 2A and 2B, a photoelectric conversion element 180, an n-type transistor 380, and a p-type transistor 385 are provided over a substrate 100 with an insulating layer 114 interposed therebetween.

The photoelectric conversion element 180 includes a semiconductor region 164 that performs photoelectric conversion, a semiconductor region 158 that exhibits a second conductivity type (here, p-type), and a semiconductor region 162 that exhibits a first conductivity type (here, n-type). The semiconductor layer 152, the insulating layer 154 and the interlayer insulating layer 166 formed so as to cover the semiconductor layer 152, the electrode 172 electrically connected to the semiconductor region 158 showing the second conductivity type, and the first conductivity type And an electrode 174 electrically connected to the semiconductor region 162 shown. Here, the semiconductor region 158 having the second conductivity type and the semiconductor region 162 having the first conductivity type are both adjacent to the semiconductor region 164 that performs photoelectric conversion and are separated by the semiconductor region 164 that performs photoelectric conversion. It has been. Note that the first conductivity type and the second conductivity type may be interchanged.

The n-type transistor 380 includes a semiconductor layer 352 including a channel formation region 322, a source region 323, a drain region 324, an LDD region 500, and an LDD region 510, an insulating layer 154 functioning as a gate insulating layer over the semiconductor layer 352, A gate electrode 375 over the insulating layer 154, an interlayer insulating layer 166 formed so as to cover the gate electrode 375, an electrode 376 electrically connected to the source region 323, and an electrode 377 electrically connected to the drain region 324 And are provided. Note that here, the structure in which the transistor 380 includes the LDD region 500 and the LDD region 510 is described; however, the present invention is not limited to this, and a structure without the LDD region may be employed. Although an example in which the LDD region does not overlap with the gate electrode when viewed from above is shown here, the LDD region may have a structure overlapping with the gate electrode. Note that LDD is a low concentration impurity region and is an abbreviation for Lightly Doped Drain.

The p-type transistor 385 includes a semiconductor layer 361 having a channel formation region 332, a source region 333, and a drain region 334, an insulating layer 154 that functions as a gate insulating layer over the semiconductor layer 361, and a gate electrode 374 over the insulating layer 154. An interlayer insulating layer 166 formed so as to cover the electrode, an electrode 378 electrically connected to the source region 333, and an electrode 379 electrically connected to the drain region 334 are provided. Note that although the p-type transistor 385 has a structure without an LDD region here, one embodiment of the present invention is not limited thereto, and a structure having an LDD region may be employed.

Here, the thickness of the semiconductor layer 152 included in the photoelectric conversion element 180 is larger than the thickness of the semiconductor layer 352 included in the n-type transistor 380 and the semiconductor layer 361 included in the p-type transistor 385.

Next, a method for manufacturing the semiconductor device is described with reference to FIGS.

First, the substrate 105 including the semiconductor layer 118 is formed over the substrate 100 with the insulating layer 114 interposed therebetween (see FIG. 3A). Note that since the substrate 105 can be formed in a manner similar to that of Embodiment 1 (see FIG. 1A), detailed description thereof is omitted.

Next, a first island-shaped semiconductor layer 120 and a second island-shaped semiconductor layer 121 are formed by forming a mask over the semiconductor layer 118 and selectively etching the mask. After that, at least the first island-shaped semiconductor layer 120 is irradiated with laser light 130 (see FIG. 3B), whereby the first island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 are formed (see FIG. 3B). (See FIG. 3C).

Since the first island-shaped semiconductor layer 120 and the second island-shaped semiconductor layer 121 can be manufactured by a method similar to that in Embodiment 1 (see FIG. 1B), detailed description is omitted. Further, the irradiation method of the laser light 130 and the formation method of the first island-shaped semiconductor layer 200 can be performed in the same manner as in Embodiment Mode 1 (see FIGS. 1C to 1E); The detailed explanation is omitted.

Next, a mask is formed over the first island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 and selectively etched, so that the third island-shaped semiconductor layer 210 and the fourth island-shaped semiconductor layer are formed. A semiconductor layer 220 is formed (see FIG. 3D). Note that the third island-shaped semiconductor layer 210 and the fourth island-shaped semiconductor layer 220 can be formed by a method similar to that in Embodiment 1 (see FIG. 1B); Is omitted.

Next, an insulating layer 154 is formed so as to cover the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220 (see FIG. 3E). Here, a silicon oxide layer is formed as a single layer by a plasma CVD method. The insulating layer 154 can be formed using a single-layer structure or a stacked-layer structure including silicon oxynitride, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, and the like in addition to silicon oxide. Note that the insulating layer 154 functions as a gate insulating layer.

As a manufacturing method other than the plasma CVD method, a sputtering method or a method using oxidation or nitridation by high-density plasma treatment can be given. The high-density plasma treatment is performed using a mixed gas of a rare gas such as helium, argon, krypton, or xenon and a gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. In this case, high-density plasma can be generated at a low electron temperature by exciting the plasma by introducing a microwave. By oxidizing or nitriding the surface of the semiconductor layer with oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by such high-density plasma, 1 nm or more An insulating layer of 20 nm or less, preferably 2 nm or more and 10 nm or less is formed so as to be in contact with the semiconductor layer.

Since the oxidation or nitridation of the semiconductor layer by the high-density plasma treatment described above is a solid-phase reaction, the insulating layer 154, the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor The interface state density with the layer 220 can be extremely low. The thickness of the insulating layer formed by directly oxidizing or nitriding the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220 by high-density plasma treatment Variations in thickness can be suppressed. In the case where the semiconductor layer 118 is a single crystal, the insulating layer 154 has good uniformity and low interface state density even when the surface of the semiconductor layer is oxidized by solid-phase reaction using high-density plasma treatment. Can be formed. Note that the insulating layer 154 formed by high-density plasma treatment can suppress variation in characteristics.

Alternatively, the insulating layer 154 may be formed by thermally oxidizing the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220. When using thermal oxidation, it is necessary to use a substrate having a certain degree of heat resistance.

Next, a conductive layer is formed over the insulating layer 154, and the conductive layer is processed, so that the gate electrode 375 and the gate electrode 374 are formed over the third island-shaped semiconductor layer and the fourth island-shaped semiconductor layer. (See FIG. 4A).

A CVD method, a sputtering method, or the like can be used for forming the conductive layer. The conductive layer is formed using a material such as tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or niobium (Nb). can do. Alternatively, an alloy material containing the above metal as a main component or a compound containing the above metal may be used. Alternatively, a semiconductor material such as polycrystalline silicon doped with an impurity element imparting conductivity to a semiconductor may be used.

In this embodiment mode, the gate electrode 375 and the gate electrode 374 are formed using a single conductive layer; however, the present invention is not limited to this. The gate electrode 375 and the gate electrode 374 may be formed using a plurality of stacked conductive layers. In the case of a two-layer structure, for example, a layer such as molybdenum, titanium, or titanium nitride may be used as a lower layer, and a layer such as aluminum may be used as an upper layer. In the case of a three-layer structure, a stacked structure of molybdenum, aluminum, and molybdenum, a stacked structure of titanium, aluminum, and titanium may be employed.

A mask used for processing the conductive layer can be manufactured in a manner similar to that of the mask 400 described in Embodiment 1, but may be formed using a material such as silicon oxide or silicon nitride oxide. In this case, a step of forming a mask by patterning a layer of silicon oxide, silicon nitride oxide, or the like is added. However, in the mask using these materials, the film thickness during etching is reduced as compared with the mask using a resist material. Therefore, the gate electrode 375 and the gate electrode 374 having more accurate shapes can be formed. Alternatively, the gate electrode 375 and the gate electrode 374 may be selectively formed by a droplet discharge method without using a mask. Here, the droplet discharge method means a method of forming a predetermined pattern by discharging or ejecting a droplet containing a predetermined composition, and includes an ink jet method or the like in its category.

The conductive layer is processed using, for example, an ICP (Inductively Coupled Plasma) etching method, and etching conditions (amount of power applied to the coil-type electrode, power applied to the substrate-side electrode) The gate electrode 375 and the gate electrode 374 can be formed so as to have a desired tapered shape by appropriately adjusting the amount, the electrode temperature on the substrate side, and the like. The taper shape can also be controlled by the shape of the mask. As an etching gas, a chlorine-based gas such as chlorine, boron chloride, silicon chloride, or carbon tetrachloride, a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, or oxygen is appropriately used. Can do.

Next, a mask 405 and a mask 406 are formed so as to cover the first island-shaped semiconductor layer 200 and the fourth island-shaped semiconductor layer 220, and the first conductivity type is formed in part of the third island-shaped semiconductor layer 210. An impurity element imparting is added. By adding the impurity element imparting the first conductivity type, a semiconductor region 328 and a semiconductor region 329 having the first conductivity type are formed in the third island-shaped semiconductor layer 210 (FIG. 4 ( B)). Since the gate electrode 375 functions as a mask, an impurity element imparting the first conductivity type is not added to the lower portion of the gate electrode 375.

As the addition of the impurity element imparting the first conductivity type, for example, phosphorus or arsenic can be added. In this embodiment, phosphorus is used as the impurity element imparting the first conductivity type, and the first conductivity type is described as n-type.

After the impurity element imparting the first conductivity type is added, the mask 405 and the mask 406 are removed.

Next, a mask 407 and a mask 408 are formed so as to cover part of the first island-shaped semiconductor layer 200 and the third island-shaped semiconductor layer 210, and an impurity element imparting the second conductivity type is added. By adding the impurity element imparting the second conductivity type, a semiconductor region 158 having the second conductivity type is formed in part of the first island-shaped semiconductor layer 200, and the fourth island-shape is formed. A source region 333 and a drain region 334 having a second conductivity type are formed in the semiconductor layer 220 (see FIG. 4C). Since the gate electrode 374 functions as a mask, an impurity element imparting the second conductivity type is not added to the lower portion of the gate electrode 374.

As the addition of the impurity element imparting the second conductivity type, for example, boron can be added. In this embodiment mode, description is made on the assumption that boron is used as the impurity element imparting the second conductivity type, and the second conductivity type is p-type.

After the impurity element imparting the second conductivity type is added, the mask 407 and the mask 408 are removed.

Next, a mask 409, a mask 410, and a mask 411 are formed so as to cover a part of the first island-shaped semiconductor layer 200, a part of the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220. An impurity element which is formed and imparts the first conductivity type is added. However, here, it is added at a higher concentration than the impurity element imparting the first conductivity type added earlier. By adding the impurity element imparting the first conductivity type, a semiconductor region 162 having the first conductivity type is formed in part of the first island-shaped semiconductor layer 200, and the third island-shape is formed. A source region 323 and a drain region 324 having the first conductivity type are formed in the semiconductor layer 210. In the third island-shaped semiconductor layer 210, an LDD region 500 and an LDD region 510 are formed in a source region 323 and a drain region 324 covered with a mask 410, and a channel formation region 322 is formed therebetween (FIG. 4 (D)).

In addition, the length of the semiconductor region 164 to which the impurity is not added which is formed by the mask 407 and the mask 409 can be 0.1 μm to 20 μm. For example, 3 μm to 10 μm is preferable. However, if the processing accuracy of the mask 407 and the mask 409 permits, it can be formed to 0.1 μm or less.

After the addition of the impurity element imparting the first conductivity type, the mask 409, the mask 410, and the mask 411 are removed.

Next, an interlayer insulating layer 166 is formed so as to cover the insulating layer 154, the gate electrode 375, and the gate electrode 374 (see FIG. 5A). For the interlayer insulating layer 166, for example, an insulating layer made of an inorganic material such as silicon oxide or BPSG (Boron Phosphorus Silicon Glass), or a layer of organic resin such as polyimide or acrylic can be used. The interlayer insulating layer 166 can be formed with a single-layer structure or a stacked structure.

Next, contact holes are formed in the insulating layer 154 and the interlayer insulating layer 166 so that parts of the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220 are exposed. Form. A contact hole 170 and a contact hole 168 are formed in the first island-shaped semiconductor layer 200, a contact hole 368 and a contact hole 370 are formed in the third island-shaped semiconductor layer 210, and a fourth island-shaped semiconductor layer 220 is formed. A contact hole 371 and a contact hole 372 are formed (see FIG. 5B).

Next, conductive layers in contact with the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220 are formed through the contact holes, and the conductive layers are selectively formed. Are etched to form an electrode 174 and an electrode 172 on the first island-shaped semiconductor layer 200, an electrode 376 and an electrode 377 are formed on the third island-shaped semiconductor layer 210, and a fourth island-shaped semiconductor is formed. An electrode 378 and an electrode 379 are formed on the layer 220 (see FIG. 5C). The conductive layer can be formed of a conductive layer having a three-layer structure in which a low-resistance metal layer such as aluminum or an aluminum alloy is sandwiched between barrier metal layers. As the barrier metal layer, molybdenum, chromium, titanium, or the like can be used.

As described above, the photoelectric conversion element 180 including the semiconductor region 162 having the first conductivity type, the semiconductor region 158 having the second conductivity type, and the semiconductor region 164 can be manufactured from the first island-shaped semiconductor layer 200. From the third island-shaped semiconductor layer 210, an n-type transistor 380 including a source region 323, a drain region 324, an LDD region 500, an LDD region 510, and a channel formation region 322 showing the first conductivity type can be manufactured. A p-type transistor 385 including a source region 333, a drain region 334, and a channel formation region 332 each having a second conductivity type can be manufactured from the fourth island-shaped semiconductor layer 220.

In this embodiment mode, the step of adding impurities to the photoelectric conversion element and the transistor is performed at the same time. However, increasing the dose added to the photoelectric conversion element increases the damage to the first island-shaped semiconductor layer 200, so that carrier traps are generated due to defects. On the other hand, by reducing the dose, the damage to the first island-shaped semiconductor layer 200 is small, and no current due to defects is generated, so that the dark current tends to be kept low. Therefore, it is preferable that the dose added to the photoelectric conversion element is small. However, it is better to increase the dose and lower the resistance of the transistor. Thus, the impurity addition process of the photoelectric conversion element and the transistor may be divided according to required characteristics.

In this embodiment mode, when manufacturing the photoelectric conversion element 180, the n-type transistor 380, and the p-type transistor 385, the method for manufacturing a semiconductor thin film substrate described in Embodiment Mode 1 is used. Through the manufacturing process of the semiconductor thin film substrate, a thick semiconductor layer and a thin semiconductor layer can be easily manufactured from one semiconductor layer 118. Therefore, individual characteristics can be maximized by manufacturing a photoelectric conversion element using a thick semiconductor layer and manufacturing a transistor using a thin semiconductor layer.

Specifically, photoelectric conversion efficiency is improved by manufacturing a photoelectric conversion element using a thick semiconductor layer. Thereby, when it uses as an optical sensor, the sensitivity as an optical sensor improves. In addition, since the sensitivity of the photosensor is improved, the photosensor can be miniaturized. In addition, the response of the optical sensor is improved. For example, when used for a touch panel, the response speed of the touch panel is improved and the operability is improved. In addition, the use of a single crystal semiconductor layer improves photoelectric conversion efficiency.

In addition, when a transistor is manufactured using a thin semiconductor layer, leakage current when the transistor is off can be reduced. Further, the short channel effect can be suppressed in a short channel device having a short channel length. In addition, a fully depleted operation is possible. Also, the drain breakdown voltage is improved. In addition, by using a single crystal semiconductor layer, electrical characteristics of the transistor can be improved.

As described above, in the semiconductor device in which the thick semiconductor layer and the thin semiconductor layer are formed, the photoelectric conversion element 180 is formed using the thick semiconductor layer, and the n-type transistor 380 and the p-type transistor are formed using the thin semiconductor layer. By forming the type transistor 385, the photoelectric conversion efficiency of the photoelectric conversion element 180 is improved while the photoelectric conversion element 180, the n-type transistor 380, and the p-type transistor 385 are formed with the same film thickness. Leakage current when the type transistor 380 and the p-type transistor 385 are off can be reduced.

Note that in the case where a light-transmitting substrate such as glass is used as the substrate 100, a structure in which light is incident from the substrate 100 side can be employed. In this case, the degree of freedom in element layout is improved as compared with the case where light is incident from the electrode (or wiring) side. As described above, since the substrate 100 has light transmittance, there is an advantage that integration is facilitated as compared with a case where the substrate 100 does not have light transmittance.

Note that this embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
In this embodiment, the case where a semiconductor device is manufactured using another example of a method for manufacturing a semiconductor thin film substrate will be described.

First, a method for manufacturing a semiconductor thin film substrate will be described with reference to FIGS.

First, the substrate 100 is prepared (see FIG. 6A). Since the substrate described in Embodiment Mode 1 can be applied to the substrate 100, detailed description is omitted.

Next, the semiconductor substrate 110 is prepared (see FIG. 6B-1). As the semiconductor substrate 110, for example, a single crystal semiconductor substrate made of a Group 14 element such as silicon, germanium, or silicon germanium can be used. A compound semiconductor substrate such as gallium arsenide or indium phosphide can also be used. Note that in this embodiment, the semiconductor substrate 110 is described using a single crystal silicon substrate.

The size of the semiconductor substrate 110 is not limited. For example, a semiconductor substrate having a diameter of 8 inches (200 mm), 12 inches (300 mm), or 18 inches (450 mm) can be used. Further, a circular semiconductor substrate may be processed into a rectangular shape. Further, the semiconductor substrate 110 can be manufactured using a CZ method (Czochralski) or an FZ (floating zone) method.

Next, the insulating layer 114 is formed over the semiconductor substrate 110 (see FIG. 6B-2).

The insulating layer 114 can be formed using a material such as silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide, for example. These films can be formed using a thermal oxidation method, a CVD method, a sputtering method, or the like. In the case where the insulating layer 114 is formed by a CVD method, a silicon oxide layer formed using an organic silane such as tetraethoxysilane (abbreviation: TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ) is insulated. The layer 114 is preferably used from the viewpoint of productivity.

In this embodiment, the insulating layer 114 (here, a silicon oxide layer) is formed by performing thermal oxidation treatment on the semiconductor substrate 110. The thermal oxidation treatment is preferably performed by adding halogen in an oxidizing atmosphere. For example, the semiconductor substrate 110 is subjected to thermal oxidation treatment in an oxidizing atmosphere to which chlorine (Cl) is added, so that the insulating layer 114 that is oxidized with HCl is formed. Therefore, the insulating layer 114 is a layer containing chlorine atoms.

Chlorine atoms contained in the insulating layer 114 cause distortion in the insulating layer 114. As a result, the water absorption rate of the insulating layer 114 is improved, and the water diffusion rate is increased. That is, when water is present on the surface of the insulating layer 114, water present on the surface can be quickly absorbed and diffused into the insulating layer 114, so that poor bonding due to the presence of water can be reduced. .

In addition, by including chlorine atoms in the insulating layer 114, it is possible to prevent the semiconductor substrate 110 from being contaminated by collecting heavy metals (for example, Fe, Cr, Ni, Mo, and the like) that are extrinsic impurities. Further, after bonding to the substrate 100, impurities such as sodium (Na) from the substrate 100 can be fixed to prevent the semiconductor substrate 110 from being contaminated.

Note that the halogen atoms contained in the insulating layer 114 are not limited to chlorine atoms. The insulating layer 114 may contain fluorine atoms. For example, a method of oxidizing the surface of the semiconductor substrate 110 with fluorine can be used. Fluorine oxidation includes a method of performing thermal oxidation treatment in an oxidizing atmosphere after being immersed in an HF solution, and a method of performing thermal oxidation treatment by adding NF ₃ to the oxidizing atmosphere.

Note that although the insulating layer 114 has a single-layer structure in this embodiment, a stacked structure may be employed. Further, when there is no need to provide the insulating layer 114, for example, when there is no particular problem in the bonding, the insulating layer 114 may not be provided.

Next, the semiconductor substrate 110 is irradiated with ions, whereby the embrittled region 112 is formed (see FIG. 6B-3). More specifically, for example, an ion beam made of ions accelerated by an electric field is irradiated to form the embrittled region 112 in a region having a predetermined depth from the surface of the semiconductor substrate 110. The depth at which the embrittlement region 112 is formed is controlled by the acceleration energy of the ion beam and the incident angle of the ion beam. That is, the embrittlement region 112 is formed in a region having a depth that is approximately the same as the average penetration depth of ions. Here, the depth at which the embrittled region 112 is formed is desirably uniform over the entire surface of the semiconductor substrate 110. Note that the surface of the semiconductor substrate 110 is preferably cleaned before ion irradiation.

Further, the thickness of the semiconductor layer separated from the semiconductor substrate 110 is determined by the depth at which the embrittled region 112 is formed. The depth at which the embrittled region 112 is formed is 50 nm or more and 1 μm or less, preferably 50 nm or more and 300 nm or less from the surface of the semiconductor substrate 110.

When the semiconductor substrate 110 is irradiated with ions, an ion implantation apparatus or an ion doping apparatus can be used. The ion implantation apparatus excites a source gas to generate ion species, mass-separates the generated ion species, and irradiates an object with an ion species having a predetermined mass. The ion doping apparatus excites a process gas to generate ion species, and irradiates the object to be processed without mass separation of the generated ion species. Note that an ion doping apparatus including a mass separation apparatus can perform ion irradiation with mass separation in the same manner as the ion implantation apparatus.

The step of forming the embrittlement region 112 when using the ion doping apparatus can be performed under the following conditions, for example.
・ Acceleration voltage: 10 kV to 100 kV (preferably 30 kV to 80 kV)
・ Dose amount 1 × 10 ¹⁶ / cm ² or more and 4 × 10 ¹⁶ / cm ² or less ・ Beam current density ² μA / cm ² or more (preferably 5 μA / cm ² or more, more preferably 10 μA / cm ² or more)

In the case of using an ion doping apparatus, a gas containing hydrogen can be used as a source gas. By using the gas, H ⁺ , H ₂ ⁺ , and H ₃ ⁺ can be generated as ionic species. When hydrogen gas is used as a source gas, it is preferable to irradiate a large amount of H ₃ ⁺ . Specifically, it is preferable that 70% or more of H ₃ ⁺ ions are included in the ion beam with respect to the total amount of H ⁺ , H ₂ ⁺ , and H ₃ ⁺ . Moreover, it is more preferable that the ratio of H ₃ ⁺ ions is 80% or more. By increasing the ratio of H ₃ ^{+ in} this way, hydrogen can be contained in the embrittlement region 112 at a concentration of 1 × 10 ²⁰ atoms / cm ³ or more. This facilitates separation in the embrittled region 112. Further, by irradiating a large amount of H ₃ ⁺ ions, the embrittled region 112 can be formed in a shorter time than in the case of irradiation with H ⁺ and H ₂ ⁺ . In addition, by using H ₃ ⁺ , the average penetration depth of ions can be reduced, so that the embrittled region 112 can be formed in a shallow region.

When using an ion implantation apparatus, it is preferable to irradiate H ₃ ⁺ ions by mass separation. Of course, H ⁺ or H ₂ ⁺ may be irradiated. However, when an ion implantation apparatus is used, since ion species are selected and irradiated, the efficiency of ion irradiation may be reduced as compared with the case where an ion doping apparatus is used.

As a source gas in the ion irradiation process, in addition to a gas containing hydrogen, a rare gas such as helium or argon, a halogen gas typified by fluorine gas or chlorine gas, or a halogen compound gas such as fluorine compound gas (for example, BF ₃ ) One or more kinds of gases selected from the above can be used. When helium is used as the source gas, an ion beam having a high ratio of He ⁺ ions can be generated by not performing mass separation. By using such an ion beam, the embrittled region 112 can be formed efficiently.

Further, the embrittlement region 112 can be formed by performing ion irradiation in a plurality of times. In this case, ion irradiation may be performed with different source gases, or the same source gas may be used. For example, after ion irradiation is performed using a rare gas as a source gas, ion irradiation can be performed using a gas containing hydrogen as a source gas. Alternatively, ion irradiation can be performed first using a halogen gas or a halogen compound gas, and then ion irradiation can be performed using a gas containing hydrogen.

Next, the substrate 100 and the semiconductor substrate 110 are attached to each other (see FIG. 6C). Specifically, the substrate 100 and the semiconductor substrate 110 are attached to each other with the insulating layer 114 interposed therebetween. By bringing the surface of the substrate 100 and the surface of the insulating layer 114 into contact with each other and then applying a pressure treatment, the substrate 100 and the insulating layer 114 are bonded to each other, and the spontaneous bonding extends over the entire surface starting from the portion. As a bonding mechanism, a mechanism involving Van der Waals force, a mechanism involving hydrogen bonding, and the like are considered.

Note that before the semiconductor substrate 110 and the substrate 100 are bonded to each other, surface treatment is performed on at least one of the insulating layer 114 and the substrate 100 formed over the semiconductor substrate 110, thereby increasing hydrophilic groups and improving flatness. Is realized. As a result, the bonding strength between the semiconductor substrate 110 and the substrate 100 can be increased.

Examples of the surface treatment include wet etching treatment, dry etching treatment, or a combination of wet etching treatment and dry etching treatment. Further, different wet etching processes can be combined, or different dry etching processes can be combined.

Examples of wet etching processes include ozone treatment using ozone water (ozone water cleaning), megasonic cleaning, or two-fluid cleaning (a method of spraying functional water such as pure water or hydrogenated water together with a carrier gas such as nitrogen). Can be mentioned. Examples of the dry etching treatment include ultraviolet treatment, ozone treatment, plasma treatment, bias application plasma treatment, radical treatment, and the like. By subjecting the object to be processed (semiconductor substrate, insulating layer formed on the semiconductor substrate, substrate or insulating layer formed on the substrate) to the surface treatment as described above, the hydrophilicity of the surface of the object to be processed and There is an effect of improving cleanliness. As a result, the bonding strength between the substrates can be improved.

The wet etching process is effective for removing macro dust adhering to the surface of the object to be processed. The dry etching process is effective for removing or decomposing micro dust such as organic substances adhering to the surface of the object to be processed. Here, the surface of the object to be treated is cleaned and hydrophilized by performing a dry etching process such as an ultraviolet ray treatment on the object to be treated, and then performing a wet etching process such as washing, thereby further improving the water on the surface of the object to be treated. Since generation | occurrence | production of a mark can be suppressed, it is preferable.

Alternatively, surface treatment using oxygen in an active state such as singlet oxygen is preferably performed. Organic substances attached to the surface of the object to be processed can be effectively removed or decomposed by oxygen in an active state such as ozone or singlet oxygen. In addition, by combining oxygen in an active state such as ozone or singlet oxygen with treatment with light having a wavelength of less than 200 nm among ultraviolet rays, organic substances attached to the surface of the object to be processed can be more effectively removed. it can. This will be specifically described below.

For example, the surface treatment of the object to be processed is performed by irradiating ultraviolet rays in an atmosphere containing oxygen. In an atmosphere containing oxygen, irradiation with light having a wavelength of less than 200 nm and light having a wavelength of 200 nm or more of ultraviolet rays can generate ozone and singlet oxygen. Further, by irradiating light including a wavelength of less than 180 nm among ultraviolet rays, ozone can be generated and singlet oxygen can be generated.

An example of a reaction that occurs by irradiation with light having a wavelength of less than 200 nm and light having a wavelength of 200 nm or more in an atmosphere containing oxygen is shown.
O ₂ + hν (λ ₁ nm) → O ( ³ P) + O ( ³ P) (1)
O ( ³ P) + O ₂ → O ₃ (2)
O ₃ + hν (λ ₂ nm) → O ( ¹ D) + O ₂ (3)

In the reaction formula (1), irradiation with light (hν) containing a wavelength (λ ₁ nm) of less than 200 nm in an atmosphere containing oxygen (O ₂ ) results in a ground state oxygen atom (O ( ³ P)). Produces. Next, in the reaction formula (2), the oxygen atom (O ( ³ P)) in the ground state reacts with oxygen (O ₂ ) to generate ozone (O ₃ ). Then, in reaction formula (3), irradiation with light including a wavelength (λ ₂ nm) of 200 nm or more is performed in an atmosphere including the generated ozone (O ₃ ), whereby singlet oxygen O ( ¹ D) is generated. In an atmosphere containing oxygen, ozone is generated by irradiating light having a wavelength of less than 200 nm among ultraviolet rays, and singlet oxygen is generated by decomposing ozone by irradiating light having a wavelength of 200 nm or more. To do. The surface treatment as described above can be performed, for example, by irradiation with a low-pressure mercury lamp (λ ₁ = 185 nm, λ ₂ = 254 nm) in an atmosphere containing oxygen.

An example of a reaction that occurs by irradiation with light having a wavelength of less than 180 nm in an atmosphere containing oxygen is shown.
O ₂ + hν (λ ₃ nm) → O ( ¹ D) + O ( ³ P) (4)
O ( ³ P) + O ₂ → O ₃ (5)
O ₃ + hν (λ ₃ nm) → O ( ¹ D) + O ₂ (6)

In the reaction formula (4), singlet oxygen O ( ¹ D) and a ground state in an excited state are irradiated with light including a wavelength (λ ₃ nm) of less than 180 nm in an atmosphere including oxygen (O ₂ ). Of oxygen atoms (O ( ³ P)). Next, in reaction formula (5), oxygen atoms (O ( ³ P)) in the ground state and oxygen (O ₂ ) react to generate ozone (O ₃ ). In reaction formula (6), singlet oxygen and oxygen in an excited state are generated by irradiation with light having a wavelength of less than 180 nm (λ ₃ nm) in an atmosphere including the generated ozone (O ₃ ). The In an atmosphere containing oxygen, ozone is generated by irradiating light having a wavelength of less than 180 nm among ultraviolet rays, and ozone or oxygen is decomposed to generate singlet oxygen. The surface treatment as described above can be performed, for example, by irradiation with a Xe excimer UV lamp in an atmosphere containing oxygen.

Chemical bonds such as organic substances adhering to the surface of the object to be processed are cut by light having a wavelength of less than 200 nm, and organic substances adhering to the surface of the object to be processed or organic substances having broken chemical bonds are oxidized and decomposed by ozone or singlet oxygen. Can be removed. By performing the surface treatment as described above, the hydrophilicity and cleanliness of the surface of the object to be processed can be further improved, and bonding can be performed satisfactorily.

After the semiconductor substrate 110 and the substrate 100 are bonded to each other, heat treatment is performed on the bonded substrate 100 and the semiconductor substrate 110 so that the bonding is strong. The heating temperature at this time needs to be a temperature at which separation in the embrittled region 112 does not proceed. For example, it is less than 400 ° C., preferably 300 ° C. or less. The heat treatment time is not particularly limited, and an appropriate condition may be set from the relationship between the treatment time and the bonding strength. For example, heat treatment can be performed at 200 ° C. for 2 hours. Note that it is also possible to locally heat only the region by irradiating the region to be bonded with microwaves or the like. When there is no problem in the bonding strength, the heat treatment may be omitted.

Next, the semiconductor substrate 110 is separated into the semiconductor layer 116 and the semiconductor substrate 117 in the embrittlement region 112 (see FIG. 6D). The semiconductor substrate 110 is preferably separated by heat treatment. The temperature of the heat treatment can be based on the heat resistant temperature of the substrate 100. For example, when a glass substrate is used as the substrate 100, the temperature of the heat treatment is preferably 400 ° C. or higher and 750 ° C. or lower. However, this does not apply as long as the heat resistance of the glass substrate permits. In this embodiment, heat treatment is performed at 600 ° C. for 2 hours.

By performing the heat treatment as described above, a volume change of minute holes formed in the embrittled region 112 occurs, and a crack occurs in the embrittled region 112. As a result, the semiconductor substrate 110 is separated along the embrittled region 112. As a result, the semiconductor layer 116 separated from the semiconductor substrate 110 remains on the substrate 100. In addition, since the interface related to bonding is heated by this heat treatment, a covalent bond is formed at the interface, and the bonding can be further strengthened.

Further, the separated semiconductor substrate 117 becomes a regenerated semiconductor substrate by a regenerating process and can be used again. Since defects due to the embrittled region 112 and the like exist on the surface of the semiconductor substrate 117 after separation, it is desirable to perform treatment for improving flatness.

Note that after the semiconductor substrate 110 is separated, the semiconductor layer 116 and the like may be irradiated with laser light. By irradiating the semiconductor layer 116 with laser light, the semiconductor layer 116 is melted, and a semiconductor layer with further improved surface flatness is obtained by subsequent cooling and solidification.

Further, after the semiconductor substrate 110 is separated, a thinning process for reducing the thickness of the semiconductor layer may be performed. For the thinning of the semiconductor layer, an etching process in which one or both of a dry etching process and a wet etching process are combined can be applied. For example, when the semiconductor layer is made of silicon, the semiconductor layer can be thinned by a dry etching process using SF ₆ and O ₂ as process gases. In the thinning process, a polishing process such as CMP may be performed instead of the etching process, or the etching process and the CMP process may be combined. The thickness of the semiconductor layer 116 can be, for example, not less than 10 nm and not more than 200 nm.

The semiconductor layer 116 after separation of the semiconductor substrate 110, the semiconductor layer 116 after laser light irradiation, and the semiconductor layer 116 after the thinning process are each formed as a semiconductor layer 118 described in Embodiment 1 (see FIG. 1A). It can also be used.

Next, a mask is formed over the semiconductor layer 116, and the semiconductor layer 116 is selectively etched using the mask, whereby the first island-shaped semiconductor layer 120 and the second island-shaped semiconductor layer 121 are formed. . Thereafter, the semiconductor thin film substrate 600 having the first island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 having different thicknesses can be formed by performing irradiation with the laser beam 130. Further, the processing method of the semiconductor layer 116 and the irradiation with the laser light 130 can be performed in a manner similar to that in Embodiment Mode 1 (see FIGS. 1B to 1E), and thus detailed description is omitted. .

The melting of the first island-shaped semiconductor layer 120 irradiated with the laser beam 130 is preferably partial melting. This is because, when completely melted, microcrystallization occurs due to disordered nucleation after becoming a liquid phase, and crystallinity is lowered. On the other hand, in partial melting, crystal growth can be performed based on a solid phase portion that is not melted, so that the crystal quality is improved as compared with the case where the first island-shaped semiconductor layer 120 is completely melted. Can do. Note that in the above, partial melting means that the region where the first island-shaped semiconductor layer 120 is melted by irradiation with the laser beam 130 is kept only near the surface, and the inside of the first island-shaped semiconductor layer 120 is not melted. say. That is, the vicinity of the surface of the first island-shaped semiconductor layer 120 is melted to become a liquid phase, but the inside is not melted and remains in a solid phase. In addition, complete melting means that the first island-shaped semiconductor layer 120 is melted to the inside to be in a liquid state.

The semiconductor layer 116 immediately after the separation has crystal defects due to ions irradiated to form the embrittled region 112. However, the first island-shaped semiconductor layer 120 and the second island-shaped semiconductor layer 121 are irradiated with laser light 130 to partially melt the first island-shaped semiconductor layer 120 and the second island-shaped semiconductor layer 121. As a result, crystal defects can be reduced. Further, since the first island-shaped semiconductor layer 120 aggregates when melted, the first island-shaped semiconductor layer 200 can be formed at the same time.

Through the above steps, the semiconductor thin film substrate 600 illustrated in FIGS. 1D and 3C can be manufactured.

Next, a method for manufacturing the photoelectric conversion element 180, the n-type transistor 380, and the p-type transistor 385 described in Embodiment 2 (see FIGS. 2A and 2B) using the semiconductor thin film substrate 600 is described. explain.

First, a mask is formed over the first island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 and selectively etched, so that the third island-shaped semiconductor layer 210 and the fourth island-shaped semiconductor are formed. Layer 220 is formed. Note that the third island-shaped semiconductor layer 210 and the fourth island-shaped semiconductor layer 220 can be formed in a manner similar to that in Embodiment 1 (see FIG. 1B), and thus detailed description thereof is omitted. .

Next, an insulating layer 154 is formed so as to cover the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220, and a conductive layer is formed over the insulating layer 154 Then, the conductive layer is processed to form the gate electrode 375 and the gate electrode 374 on the third island-shaped semiconductor layer 210 and the fourth island-shaped semiconductor layer 220. Note that the insulating layer 154, the gate electrode 374, and the gate electrode 374 can be formed in a manner similar to that of Embodiment 2 (see FIGS. 3E and 4A), and thus detailed description thereof is omitted. .

Next, an impurity element imparting the first conductivity type and an impurity element imparting the second conductivity type are selectively added using a mask. Note that the impurity element imparting the first conductivity type and the impurity element imparting the second conductivity type are added in the same manner as in Embodiment Mode 2 (see FIGS. 4B to 4D). Since it can be performed, detailed description is omitted.

Next, an interlayer insulating layer 166 is formed so as to cover the insulating layer 154, the gate electrode 375, and the gate electrode 374. Note that the interlayer insulating layer 166 can be formed in a manner similar to that of Embodiment 2 (see FIG. 5A), and thus detailed description thereof is omitted.

Next, the contact hole 170 is formed in the insulating layer 154 and the interlayer insulating layer 166 so that a part of the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220 is exposed. , Contact hole 168, contact hole 368, contact hole 370, contact hole 371, and contact hole 372 are formed. Note that the contact hole 170, the contact hole 168, the contact hole 368, the contact hole 370, the contact hole 371, and the contact hole 372 can be formed in a manner similar to that of Embodiment 2 (see FIG. 5B). Detailed description is omitted.

Next, the first island-shaped semiconductor layer, the third island-shaped semiconductor layer, and the fourth through the contact hole 170, the contact hole 168, the contact hole 368, the contact hole 370, the contact hole 371, and the contact hole 372 A conductive layer in contact with the island-shaped semiconductor layer is formed, and the conductive layer is selectively etched, whereby an electrode 174, an electrode 172, an electrode 376, an electrode 377, an electrode 378, and an electrode 379 are formed. Note that the electrode 174, the electrode 172, the electrode 376, the electrode 377, the electrode 378, and the electrode 379 can be formed in a manner similar to that in Embodiment 2 (see FIG. 5C), and thus detailed description thereof is omitted.

As described above, the photoelectric conversion element 180 including the semiconductor region 162 having the first conductivity type, the semiconductor region 158 having the second conductivity type, and the semiconductor region 164 is manufactured from the first island-shaped semiconductor layer 200. In addition, the n-type transistor 380 including the source region 323, the drain region 324, the LDD region 500, the LDD region 510, and the channel formation region 322 which show the first conductivity type can be manufactured from the third island-shaped semiconductor layer 210. In addition, the p-type transistor 385 including the source region 333, the drain region 334, and the channel formation region 332 each having the second conductivity type can be manufactured from the fourth island-shaped semiconductor layer 220.

In this embodiment, the impurity addition step for the photoelectric conversion element and the transistor is performed at the same time. However, the impurity addition step for the photoelectric conversion element and the transistor may be divided according to required characteristics.

Through the manufacturing process of the semiconductor thin film substrate, a thick semiconductor layer and a thin semiconductor layer can be easily manufactured from one semiconductor layer 116. By manufacturing a photoelectric conversion element using a thick semiconductor layer and manufacturing a transistor using a thin semiconductor layer, individual characteristics can be maximized.

Note that this embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, the case where a semiconductor device is manufactured using another example of a method for manufacturing a semiconductor thin film substrate will be described.

First, a method for manufacturing a semiconductor thin film substrate will be described with reference to FIGS.

First, the substrate 100 is prepared (see FIG. 7A-1), and the insulating layer 101 is formed over the substrate (see FIG. 7A-2). Since the substrate 100 may be referred to Embodiment Mode 3 (FIG. 6A), detailed description is omitted.

As a method for forming the insulating layer 101, a sputtering method, a plasma CVD method, or the like can be used. Since the insulating layer 101 is a layer having a surface for bonding, the insulating layer 101 is preferably formed so that the surface has high flatness. For example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, or the like can be used. The insulating layer 101 can be formed using one or a plurality of materials. For example, when the insulating layer 101 is formed using silicon oxide, the insulating layer 101 with extremely excellent flatness can be obtained by forming the insulating layer 101 using an organic silane gas by a chemical vapor deposition method. Note that the insulating layer 101 can have a single-layer structure or a stacked structure.

Next, the semiconductor substrate 110 is prepared (see FIG. 7B-1). The semiconductor substrate 110 can be prepared in a manner similar to that of Embodiment 3 (see FIG. 6B-1), and thus detailed description thereof is omitted.

Next, the insulating layer 114 is formed over the semiconductor substrate 110, the embrittlement region 112 is formed by ion irradiation, the substrate 100 and the semiconductor substrate 110 are bonded to each other through the insulating layer 101 and the insulating layer 114, and heat treatment is performed. A semiconductor layer 116 is formed over the substrate 100 (see FIGS. 7B-2 to 7D). Since the insulating layer 114 and the semiconductor layer 116 can be formed in a manner similar to that in Embodiment 3 (see FIGS. 6B-2 to 6D), detailed description is omitted. Note that the semiconductor layer 116 can be used as the semiconductor layer 118 described in Embodiment 1 (see FIG. 1A).

Next, a mask is formed over the separated semiconductor layer 116, and the semiconductor layer 116 is selectively etched using the mask, whereby the first island-shaped semiconductor layer 120 as illustrated in FIG. And the second island-shaped semiconductor layer 121, and then the semiconductor thin film having the first island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 having different thicknesses by irradiating the laser beam 130. A substrate 600 can be formed. A patterning method, laser light irradiation, and a method for forming the first island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 are described in Embodiment Mode 1 (see FIGS. 1B to 1E). Therefore, detailed description is omitted.

Further, the first island-like semiconductor layer 120 and the second island-like semiconductor layer 121 as shown in FIG. 1B may be formed immediately after being separated into the semiconductor layer 116 and the semiconductor substrate 117. . Even when the first island-shaped semiconductor layer 120 and the second island-shaped semiconductor layer 121 are formed immediately after being separated into the semiconductor layer 116 and the semiconductor substrate 117, the first embodiment (FIG. 1B to FIG. 1 (E)), the first island-like semiconductor layer 200 and the second island-like semiconductor layer 121 can be formed. Note that the first island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 can be formed in a manner similar to that of Embodiment 1 (see FIGS. 1B to 1E); The detailed explanation is omitted.

Through the above steps, the semiconductor thin film substrate illustrated in FIGS. 1D and 3C can be manufactured.

Next, a method for manufacturing the photoelectric conversion element 180, the n-type transistor 380, and the p-type transistor 385 described in Embodiment 2 (see FIGS. 2A and 2B) using a semiconductor thin film substrate. explain.

First, a mask is formed over the first island-shaped semiconductor layer 200 and the second island-shaped semiconductor layer 121 and selectively etched, so that the third island-shaped semiconductor layer 210 and the fourth island-shaped semiconductor are formed. Layer 220 is formed. Note that the third island-shaped semiconductor layer 210 and the fourth island-shaped semiconductor layer 220 can be formed by a method similar to that in Embodiment 1 (see FIG. 1B); Is omitted.

Next, an insulating layer 154 is formed so as to cover the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220, and a conductive layer is formed over the insulating layer 154 Then, the conductive layer is processed to form the gate electrode 375 and the gate electrode 374 on the third island-shaped semiconductor layer 210 and the fourth island-shaped semiconductor layer 220. Note that the insulating layer 154, the gate electrode 374, and the gate electrode 374 can be formed in a manner similar to that of Embodiment 2 (see FIGS. 3E and 4A), and thus detailed description thereof is omitted. .

Next, an impurity element imparting the first conductivity type and an impurity element imparting the second conductivity type are selectively added using a mask. Note that the impurity element imparting the first conductivity type and the impurity element imparting the second conductivity type are added in the same manner as in Embodiment Mode 2 (see FIGS. 4B to 4D). Since it can be performed, detailed description is omitted.

Next, an interlayer insulating layer 166 is formed so as to cover the insulating layer 154, the gate electrode 375, and the gate electrode 374. Note that the interlayer insulating layer 166 can be formed in a manner similar to that of Embodiment 2 (see FIG. 5A), and thus detailed description thereof is omitted.

Next, the contact hole 170 is formed in the insulating layer 154 and the interlayer insulating layer 166 so that a part of the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the fourth island-shaped semiconductor layer 220 is exposed. , Contact hole 168, contact hole 368, contact hole 370, contact hole 371, and contact hole 372 are formed. Note that the contact hole 170, the contact hole 168, the contact hole 368, the contact hole 370, the contact hole 371, and the contact hole 372 can be formed in a manner similar to that of Embodiment 2 (see FIG. 5B). Detailed description is omitted.

Next, the first island-shaped semiconductor layer 200, the third island-shaped semiconductor layer 210, and the contact hole 170, the contact hole 168, the contact hole 368, the contact hole 370, the contact hole 371, and the contact hole 372, A conductive layer in contact with the fourth island-shaped semiconductor layer 220 is formed, and the conductive layer is selectively etched, so that the electrode 174, the electrode 172, the electrode 376, the electrode 377, the electrode 378, and the electrode 379 are formed. Note that the electrode 174, the electrode 172, the electrode 376, the electrode 377, the electrode 378, and the electrode 379 can be formed in a manner similar to that in Embodiment 2 (see FIG. 5C), and thus detailed description thereof is omitted.

As described above, the photoelectric conversion element 180 including the semiconductor region 162 having the first conductivity type, the semiconductor region 158 having the second conductivity type, and the semiconductor region 164 is manufactured from the first island-shaped semiconductor layer 200. In addition, the n-type transistor 380 including the source region 323, the drain region 324, the LDD region 500, the LDD region 510, and the channel formation region 322 which show the first conductivity type can be manufactured from the third island-shaped semiconductor layer 210. In addition, the p-type transistor 385 including the source region 333, the drain region 334, and the channel formation region 332 each having the second conductivity type can be manufactured from the fourth island-shaped semiconductor layer 220.

In this embodiment, the impurity addition step for the photoelectric conversion element and the transistor is performed at the same time. However, the impurity addition step for the photoelectric conversion element and the transistor may be divided according to required characteristics.

Through the manufacturing process of the semiconductor thin film substrate, a thick semiconductor layer and a thin semiconductor layer can be easily manufactured from one semiconductor layer 116. By manufacturing a photoelectric conversion element using a thick semiconductor layer and manufacturing a transistor using a thin semiconductor layer, individual characteristics can be maximized.

Note that this embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

100 substrate 101 insulating layer 105 substrate 110 semiconductor substrate 112 embrittlement region 114 insulating layer 116 semiconductor layer 117 semiconductor substrate 118 semiconductor layer 120 first island-shaped semiconductor layer 121 second island-shaped semiconductor layer 130 laser beam 152 semiconductor layer 154 insulation Layer 158 Semiconductor region 162 Semiconductor region 164 Semiconductor region 166 Interlayer insulating layer 168 Contact hole 170 Contact hole 172 Electrode 174 Electrode 180 Photoelectric conversion element 200 First island semiconductor layer 210 Third island semiconductor layer 220 Fourth island Semiconductor layer 322 Channel formation region 323 Source region 324 Drain region 328 Semiconductor region 329 Semiconductor region 332 Channel formation region 333 Source region 334 Drain region 352 Semiconductor layer 361 Semiconductor layer 368 Contact hole 370 Contact hole 371 Contact hole 372 Contact hole 374 Gate electrode 375 Gate electrode 376 Electrode 377 Electrode 378 Electrode 379 Electrode 380 Transistor 385 Transistor 400 Mask 401 Mask 405 Mask 406 Mask 407 Mask 408 Mask 409 Mask 410 Mask 411 Mask 500 LDD region 510 LDD region 600 Semiconductor Thin film substrate

Claims (2)

Forming a semiconductor layer on the substrate;
Processing the semiconductor layer to form a first island-like semiconductor layer and a second island-like semiconductor layer;
What line laser irradiation on the first island-shaped semiconductor layer, the Rukoto is partially melting the first semiconductor island, the first island-shaped semiconductor layer, the second island-shaped semiconductor layer more thickness is thicker third island-shaped semiconductor layer,
The planar shape of the first island-shaped semiconductor layer when the substrate is viewed from above is such that the ratio of the length of the short side to the long side is 1: x (x is a number greater than 1) and the short side A method for manufacturing a semiconductor substrate, wherein the length of the semiconductor substrate is 10 μm or less. In claim 1,
The method for manufacturing a semiconductor substrate, wherein the first island-shaped semiconductor layer is aggregated on the insulating layer by the laser irradiation to form a curved surface at an upper end portion.

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