KR100549257B1 - Method of surface smoothing for soi wafer - Google Patents

Method of surface smoothing for soi wafer Download PDF

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KR100549257B1
KR100549257B1 KR1019990055912A KR19990055912A KR100549257B1 KR 100549257 B1 KR100549257 B1 KR 100549257B1 KR 1019990055912 A KR1019990055912 A KR 1019990055912A KR 19990055912 A KR19990055912 A KR 19990055912A KR 100549257 B1 KR100549257 B1 KR 100549257B1
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soi wafer
soi
wafer
hcl gas
gas phase
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KR1019990055912A
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KR20010054917A (en
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홍진균
이재춘
이정섭
유학도
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주식회사 실트론
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

SOI 웨이퍼의 표면 가공 시간을 단축함으로써 생산성을 향상시키며, 박막 및 후막 SOI 웨이퍼의 표면 가공에 적용 가능하며 결함 밀도를 낮춘 고품질의 SOI 웨이퍼를 제조하기 위하여, 수소 이온 주입에 의해 전사된 실리콘 층을 갖는 박막 SOI 웨이퍼 또는 접합 방법에 의해 제작된 후막 SOI 웨이퍼의 표면 요철을 갖는 SOI 웨이퍼를 형성한 후, 수소 가스 분위기에 급속 열처리하여 후속 HCl 기상 식각시의 균일성을 보장한다. 그리고, 상압의 레머널 플로우를 갖는 반응기에서 SOI 웨이퍼를 1050℃ 내지 1200℃로 유지하며 HCl 가스량을 1slm 내지 40slm로 하여 표면 요철을 갖는 SOI 웨이퍼를 HCl 기상 식각하여 평탄화 및 표면 경면화하고, 표면 경면화된 SOI 웨이퍼를 수소 가스 분위기에서 급속 열처리하여 표면 결함을 감소시키고, SOI 웨이퍼를 세정한다. 따라서, 종래와 같은 기계적 연마를 하지 않고 레머널 플로우를 갖는 반응기에서 HCl 기상 식각에 의해 경면화를 실시함으로써 기계적 손상이 없는 SOI 웨이퍼의 표면 평탄화 및 경면화 가공이 가능하며 수소 가스 분위기의 급속 열처리에 의해 SOI 웨이퍼 표면의 결함을 감소시켜 고품질의 SOI 웨이퍼를 제작할 수 있다.In order to improve the productivity by shortening the surface processing time of the SOI wafer, it is applicable to the surface processing of the thin film and thick film SOI wafers, and has a silicon layer transferred by hydrogen ion implantation to produce a high quality SOI wafer with low defect density. After forming the SOI wafer having the surface irregularities of the thin film SOI wafer or the thick film SOI wafer produced by the bonding method, rapid heat treatment in a hydrogen gas atmosphere ensures uniformity during subsequent HCl gas phase etching. In addition, the SOI wafer is maintained at 1050 ° C. to 1200 ° C. and the HCl gas is 1 slm to 40 slm in a reactor having a normal-pressure remnant flow, and the surface irregularities are planarized and surface-mirrified by HCl gas phase etching. The oxidized SOI wafer is rapidly heat treated in a hydrogen gas atmosphere to reduce surface defects and clean the SOI wafer. Therefore, the surface planarization of the SOI wafer without mechanical damage is possible by performing mirror surface treatment by HCl gas phase etching in a reactor having a remnant flow without mechanical polishing as in the prior art, and for rapid heat treatment of a hydrogen gas atmosphere. As a result, defects on the surface of the SOI wafer can be reduced to produce a high quality SOI wafer.

HCl 기상 식각, 레머널 플로우, SOI 웨이퍼, 표면 경면 연마HCl vapor etching, remnant flow, SOI wafers, surface mirror polishing

Description

에스오아이 웨이퍼의 표면 정밀 가공 방법{METHOD OF SURFACE SMOOTHING FOR SOI WAFER}Surface precision machining method of SOHI wafer {METHOD OF SURFACE SMOOTHING FOR SOI WAFER}

도 1은 본 발명의 일 실시예에 따른 에스오아이 웨이퍼의 표면 정밀 가공 방법을 개략적으로 도시한 동작 순서도이고,1 is an operation flowchart schematically showing a surface precision processing method of an SOH wafer according to an embodiment of the present invention,

도 2는 본 발명의 일 실시예에 따라 SOI 웨이퍼를 HCl 기상 식각하는 공정의 반응기 조건을 개략적으로 도시한 것이고,Figure 2 schematically shows the reactor conditions of the process of HCl gas phase etching the SOI wafer in accordance with an embodiment of the present invention,

도 3a는 경면 연마된 일반적인 실리콘웨이퍼의 표면 미소 거칠기를 측정한 것이며,Figure 3a is a measure of the surface micro-roughness of the mirror polished general silicon wafer,

도 3b는 본 발명의 일 실시예에 따른 SOI 웨이퍼의 표면 미소 거칠기를 측정한 것이다.3B is a measure of the surface micro-roughness of the SOI wafer according to an embodiment of the present invention.

본 발명은 반도체 소자 형성을 위한 에스오아이(silicon on insulator; SOI) 웨이퍼를 제조하는 방법에 관한 것으로, 더욱 상세하게는 수소 이온 주입에 의해 전사된 실리콘 층을 갖는 박막 SOI 웨이퍼의 표면 요철이나 접합 방법으로 제작된 후막 SOI 웨이퍼의 연삭 후 표면 요철이 있는 활성층 실리콘 표면을 경면화하기 위 해 정밀 가공하는 SOI 웨이퍼의 표면 정밀 가공 방법에 관한 것이다.The present invention relates to a method for manufacturing a silicon on insulator (SOI) wafer for the formation of a semiconductor device, and more particularly, the surface irregularities or bonding method of a thin film SOI wafer having a silicon layer transferred by hydrogen ion implantation The present invention relates to a method for precision surface processing of an SOI wafer which is precisely processed to mirror the surface of the active layer silicon having surface irregularities after grinding the thick film SOI wafer manufactured by the present invention.

일반적으로 SOI 웨이퍼는 단결정 실리콘 박막이 기판 상의 매몰 산화막(buried oxide)의 상부에 형성되어 있는 3층 구조를 하고 있으며, 트랜지스터 등의 활성층은 SOI 층 상부에 형성된다.In general, an SOI wafer has a three-layer structure in which a single crystal silicon thin film is formed on an buried oxide layer on a substrate, and an active layer such as a transistor is formed on the SOI layer.

이러한 SOI 웨이퍼를 제조하는 방법은 크게 SIMOX(separation by implanted oxygen)와 결합 SOI 웨이퍼로 분류할 수 있다. 그리고, 박막 SOI 웨이퍼인 unibond 기판이나 SiGen 기판의 경우 결합 후 분리된 SOI 웨이퍼의 표면은 분리 방법에 따른 표면 요철을 갖게 된다.Methods of manufacturing such SOI wafers can be broadly classified into separation by implanted oxygen (SIMOX) and bonded SOI wafers. In the case of a unibond substrate or a SiGen substrate, which is a thin SOI wafer, the surface of the separated SOI wafer after bonding has surface irregularities according to a separation method.

이와 같은 SOI 웨이퍼 표면의 표면 요철을 경면화하기 위하여 현재는 CMP(chemical mechanical polishing) 또는 PACE(plasma assisted chemical etching) 방법 등을 사용한다. 또한, 후막 SOI 웨이퍼의 제조 방법인 결합 SOI 웨이퍼의 경우에도 결합된 기판을 원하는 두께로 가공하기 위하여 연마 후 표면을 경면화하기 위해 CMP 또는 PACE 방법 등이 사용된다.In order to mirror the surface irregularities on the surface of the SOI wafer, a chemical mechanical polishing (CMP) or plasma assisted chemical etching (PACE) method is used. In addition, in the case of a bonded SOI wafer, which is a method for manufacturing a thick film SOI wafer, a CMP or PACE method is used to mirror the surface after polishing in order to process the bonded substrate to a desired thickness.

그러나 CMP에 의한 표면 경면화 작업은 슬러리(slurry) 및 기계적 마찰에 의한 기판 손상의 발생과 기판 가장 자리부가 연마 패드의 점탄성 변형 때문에 연마의 균일성에 영향을 미치는 에지 라운딩(edge rounding) 현상이 발생해 공정 관리에 어려움이 많다.However, surface mirroring by CMP results in substrate damage due to slurry and mechanical friction and edge rounding, which affects the uniformity of polishing due to viscoelastic deformation of the polishing pad. Difficulties in process control

또한 고속, 저소비 전력화 상보형 모스 소자에서는 SOI 층의 완전 공핍화를 위해 SOI 층의 두께가 더욱 얇아지고 고도의 면내 두께 균일성을 요구하기 때문에 CMP 가공에 의해서는 더 이상의 박막화와 경면화에 어려움이 많다.In addition, in the high-speed, low-power-complementary MOS device, the thickness of the SOI layer is thinner and the in-plane thickness uniformity is required for the complete depletion of the SOI layer. many.

PACE 방법 또한 기존의 연삭 연마법으로 박막화된 결합 SOI 웨이퍼를 특별한 장치에 의해 정밀 연마하는 것으로, 웨이퍼 전체의 두께 균일성은 개선할 수 있으나 국소적 식각 도구의 특성으로 인한 PACE 연마에 의해 형성된 주기적인 표면 요철을 남겨 고주파 형상을 지닌 표면의 형상 개선에 어려움이 있다. 또한 PACE 전극 주사에 의한 흔적이 막 두께 차이에 의해 얼룩으로 나타나는 경우가 종종 있으며 생산성이 낮은 단점이 있다.The PACE method is also used to precisely polish the bonded SOI wafer thinned by the conventional grinding method by a special device, which can improve the thickness uniformity of the entire wafer, but the periodic surface formed by the PACE polishing due to the characteristics of the local etching tool. It is difficult to improve the shape of the surface having high frequency shape by leaving unevenness. In addition, traces due to PACE electrode scanning are often spotted due to the difference in film thickness, which has the disadvantage of low productivity.

본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 그 목적은 SOI 웨이퍼의 표면 가공 시간을 단축함으로써 생산성을 향상시키며, 박막 및 후막 SOI 웨이퍼의 표면 가공에 적용 가능하며 결함 밀도를 낮춘 고품질의 SOI 웨이퍼를 제조할 수 있도록 하는 SOI 웨이퍼의 표면 정밀 가공 방법을 제공하는 데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and its object is to improve the productivity by shortening the surface processing time of the SOI wafer, and to apply to the surface processing of the thin film and thick film SOI wafers and to reduce the defect density. The present invention provides a method for precise surface machining of an SOI wafer.

상기와 같은 목적을 달성하기 위한 본 발명의 SOI 웨이퍼의 표면 정밀 가공 방법은, 수소 이온 주입에 의해 전사된 실리콘 층을 갖는 박막 SOI 웨이퍼 또는 접합 방법에 의해 제작된 후막 SOI 웨이퍼의 표면 요철을 갖는 SOI 웨이퍼를 형성하는 단계와; 상기 표면 요철을 갖는 SOI 웨이퍼를 상압의 레머널 플로우를 갖는 반응기에서 HCl 기상 식각을 실시하여 평탄화 및 표면 경면화하는 단계와; 상기 표면 경면화된 SOI 웨이퍼를 수소 가스 분위기에서 급속 열처리하여 표면 결함을 감소시키는 단계와; 상기 SOI 웨이퍼를 세정하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the SOI wafer surface precision processing method of the present invention is a thin film SOI wafer having a silicon layer transferred by hydrogen ion implantation or an SOI having surface irregularities of a thick film SOI wafer produced by a bonding method. Forming a wafer; Planarizing and surface mirroring the SOI wafer having surface irregularities by performing HCl gas phase etching in a reactor having a normal-pressure remnant flow; Rapidly heat treating the surface mirrored SOI wafer in a hydrogen gas atmosphere to reduce surface defects; Cleaning the SOI wafer.

또한 본 발명은 표면 요철을 갖는 SOI 웨이퍼를 HCl 기상 식각하여 평탄화 및 표면 경면화를 하기 이전에, 표면 요철을 갖는 SOI 웨이퍼를 수소 가스 분위기 에 급속 열처리하여 후속 HCl 기상 식각시의 균일성을 보장하는 것을 특징으로 한다.In addition, the present invention is to provide a uniform heat treatment during subsequent HCl gas phase etching by rapid heat treatment of the SOI wafer having surface irregularities in a hydrogen gas atmosphere before the planarization and surface mirroring of SOI wafers having surface irregularities It is characterized by.

상기에서 HCl 기상 식각은, SOI 웨이퍼를 1050℃ 내지 1200℃로 유지하며 HCl 가스량을 1slm 내지 40slm로 하는 것이 바람직하다.In the HCl gas phase etching, the SOI wafer is preferably maintained at 1050 ° C. to 1200 ° C., and the HCl gas amount is 1 slm to 40 slm.

이하, 첨부된 도면을 참조하여 본 발명에 따른 바람직한 일 실시예를 설명한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 1은 본 발명의 일 실시예에 따른 SOI 웨이퍼의 표면 정밀 가공 방법을 개략적으로 도시한 동작 순서도이다.1 is a flowchart schematically illustrating a method for precisely machining a surface of an SOI wafer according to an exemplary embodiment of the present invention.

먼저 쵸크랄스키 결정 성장법 또는 플로트 존 결정 성장법에 따라 실리콘 단결정 봉을 생산하고 이를 얇게 절단하여 웨이퍼의 한 면을 경면 연마하고 세정한 후 최종 검사하여 실리콘웨이퍼를 제조한다. 이후 제조된 실리콘웨이퍼를 이용하여 SOI 웨이퍼를 제조하기 위하여, 박막 SOI 웨이퍼의 경우에는 실리콘웨이퍼에 산화막을 형성한 후 수소 이온 주입을 실시하고, 핸들 웨이퍼와 결합한 후 특정 방법에 의해 분리시키고 열처리하며, 후막 SOI 웨이퍼의 경우에는 산화막을 형성시킨 디바이스 웨이퍼와 지지 기판 웨이퍼를 여러 가지 방법에 의해 결합시킨 후 열처리한다. 그리고, 열처리한 웨이퍼를 원하는 두께로 그라인더(연삭기)를 이용해 연삭함으로써 표면 요철이 있는 SOI 웨이퍼를 형성한다(S1).First, silicon single crystal rods are produced according to Czochralski crystal growth method or float zone crystal growth method, and thinly cut and polished one surface of the wafer, and then cleaned, and finally a silicon wafer is manufactured. Then, in order to manufacture an SOI wafer using the manufactured silicon wafer, in the case of a thin film SOI wafer, an oxide film is formed on the silicon wafer, hydrogen ion implantation is carried out, and after being combined with a handle wafer, separated and heat treated by a specific method, In the case of a thick film SOI wafer, a device wafer and an supporting substrate wafer on which an oxide film is formed are bonded by various methods and then heat-treated. Then, the heat-treated wafer is ground to a desired thickness using a grinder (grinding machine) to form an SOI wafer with surface irregularities (S1).

이때, 분리된 박막 SOI 웨이퍼의 표면 거칠기는 AFM(면적 :

Figure 111999016621848-pat00001
)으로 측정시 수십 Å의 값을 나타내며, 정밀 연삭된 후막 SOI 웨이퍼는 100Å 이상의 표 면 미소 거칠기 값(Rms)을 나타낸다.At this time, the surface roughness of the separated thin film SOI wafer is AFM (area:
Figure 111999016621848-pat00001
When measured with a square wave, it shows a value of several tens of microseconds, and the finely ground thick film SOI wafer shows a surface micro-roughness value (Rms) of 100 microns or more.

그 다음 표면 요철이 있는 SOI 웨이퍼를 수소 가스 분위기에서 급속 열처리(rapid thermal processing)하여 SOI 웨이퍼의 표면 요철을 일부 개선시킨다(S2). 이는 후속 HCl 기상 식각 공정에서의 표면 균일성을 보장하기 위해 특히, HCl 기상 식각으로 제거되는 두께가 1

Figure 111999016621848-pat00002
이하인 박막 SOI 웨이퍼의 경우에는 매우 효과적이다. 그러나, 제거되는 두께가 2
Figure 111999016621848-pat00003
이상인 후막 SOI 웨이퍼의 경우에는 수소 가스 분위기의 빠른 열처리를 생략해도 무방하다.Then, the SOI wafer with surface irregularities is rapidly thermally treated in a hydrogen gas atmosphere to partially improve the surface irregularities of the SOI wafer (S2). It has a thickness of 1 removed in particular with HCl gas phase etching to ensure surface uniformity in subsequent HCl gas phase etching processes.
Figure 111999016621848-pat00002
In the case of the following thin film SOI wafer, it is very effective. However, the thickness to be removed 2
Figure 111999016621848-pat00003
In the case of the thick film SOI wafer described above, the rapid heat treatment in the hydrogen gas atmosphere may be omitted.

그 다음 SOI 웨이퍼를 레머널(laminar) 플로우(flow)를 갖는 반응기, 일 예로 에피 반응기(epi reactor)에 장입하여 도 2에서와 같은 조건으로 SOI 웨이퍼를 HCl 기상 식각(vapor etching)하여 표면 요철이 있는 SOI 웨이퍼 표면의 평탄화 및 경면화 작업을 실시한다(S3).Then, the SOI wafer is charged into a reactor having a laminar flow, for example, an epi reactor, and HCl vapor etching the SOI wafer under the conditions as shown in FIG. The planarization and mirror-mirror operation | work of the surface of the SOI wafer which exists is performed (S3).

이때, HCl 기상 식각은 상압(atmospheric pressure)에서 진행하는 것이 바람직하다.At this time, HCl gas phase etching is preferably performed at atmospheric pressure (atmospheric pressure).

그리고, 식각 균일성을 유지하기 위하여 SOI 웨이퍼의 온도를 1050℃ 내지 1200℃정도의 고온에서 유지하고 식각율을 제어하기 위하여 HCl 가스량을 1slm 내지 40slm 범위 내에서 가변 조정하는 것이 바람직하며, SOI 웨이퍼 온도 및 HCl 가스량의 공정 조건에 따른 SOI 박막의 식각되는 두께를 표 1에 예시적으로 나타내었다.In order to maintain the etching uniformity, the temperature of the SOI wafer is maintained at a high temperature of about 1050 ° C. to 1200 ° C. and the amount of HCl gas is controlled to be adjusted within the range of 1 slm to 40 slm to control the etching rate. And etched thickness of the SOI thin film according to the process conditions of the amount of HCl gas is shown in Table 1 by way of example.

또한, 식각 공정에서의 오염을 방지하기 위하여 HCl 가스는 고순도를 사용하 는 것이 바람직하며, 도 2에서의 온도 상승 속도 및 온도 하강 속도는 예시적으로 도시한 것으로 본 발명에 한정되는 것은 아니다.In addition, in order to prevent contamination in the etching process, it is preferable to use HCl gas with high purity, and the temperature rising rate and the temperature falling rate in FIG. 2 are exemplarily illustrated and are not limited to the present invention.

시험exam 온도(℃)Temperature (℃) HCl(slm)HCl (slm) 시간(sec)Time (sec) 제거 두께(

Figure 111999016621848-pat00004
)Removal thickness (
Figure 111999016621848-pat00004
) #1#One 11301130 1One 3030 0.170.17 #2#2 11301130 1010 3030 4.394.39 #3# 3 11901190 1One 3030 0.180.18 #4#4 11901190 1010 3030 7.707.70

그 다음 HCl 기상 식각에 의해 표면 경면화된 SOI 웨이퍼를 수소 가스 분위기에서 급속 열처리하여 SOI 웨이퍼의 표면 결함을 감소시킨다(S4). 그 다음 SOI 웨이퍼를 세정함으로써 표면이 정밀 가공된 SOI 웨이퍼를 완성한다.Then, the SOI wafer surface mirrored by HCl gas phase etching is rapidly heat-treated in a hydrogen gas atmosphere to reduce surface defects of the SOI wafer (S4). The SOI wafer is then cleaned to complete an SOI wafer with a fine surface.

이러한 실시예에 따라 표면이 정밀 가공된 SOI 웨이퍼의 표면 미소 거칠기(Rms)를 AFM에 의해 측정한 결과를 도 3b에 도시하였으며, 도 3a의 표면 미소 거칠기(Rms)가 0.68Å 이하인 경면 연마된 실리콘웨이퍼와 비교하여 볼 때 도 3b의 본 발명에 따라 HCl 기상 식각한 SOI 웨이퍼의 표면 미소 거칠기(Rms)가 0.61Å 이하로 경면 연마된 실리콘웨이퍼와 동등하거나 다소 우수한 미소 거칠기 값을 얻을 수 있다.According to this embodiment, the surface micro-roughness (Rms) of the SOI wafer whose surface is precisely processed by AFM is shown in FIG. 3B, and the surface-grinded silicon having the surface micro-roughness (Rms) of FIG. 3A is 0.68 GPa or less. Compared to the wafer, according to the present invention of FIG. 3B, the surface micro-roughness (Rms) of the HCl vapor-etched SOI wafer is equal to or slightly better than that of the mirror-polished silicon wafer of 0.61 Å or less.

이와 같이 본 발명은 표면 요철이 있는 박막 SOI 웨이퍼나 후막 SOI 웨이퍼의 표면 경면화에 적용할 수 있으며, 종래와 같은 기계적 연마를 하지 않고 레머널 플로우를 갖는 반응기에서 HCl 기상 식각에 의해 경면화를 실시함으로써 기계적 손상이 없는 SOI 웨이퍼의 표면 평탄화 및 경면화 가공이 가능하며 수소 가스 분위기의 급속 열처리에 의해 SOI 웨이퍼 표면의 결함을 감소시켜 고품질의 SOI 웨이퍼를 제작할 수 있다.As described above, the present invention can be applied to the surface mirroring of a thin film SOI wafer or a thick film SOI wafer having surface irregularities, and is mirror-hardened by HCl gas phase etching in a reactor having a normal flow without mechanical polishing. As a result, surface planarization and mirror-hardening processing of the SOI wafer without mechanical damage is possible, and defects on the surface of the SOI wafer can be reduced by rapid heat treatment in a hydrogen gas atmosphere, thereby producing a high quality SOI wafer.

Claims (5)

수소 이온 주입에 의해 전사된 실리콘 층을 갖는 박막 SOI 웨이퍼 또는 접합 방법에 의해 제작된 후막 SOI 웨이퍼의 표면 요철을 갖는 SOI 웨이퍼를 형성하는 단계와;Forming a SOI wafer having surface irregularities of a thin film SOI wafer having a silicon layer transferred by hydrogen ion implantation or a thick film SOI wafer fabricated by a bonding method; 상기 표면 요철을 갖는 SOI 웨이퍼를 상압의 레머널 플로우를 갖는 반응기에서 HCl 기상 식각을 실시하여 평탄화 및 표면 경면화하는 단계와;Planarizing and surface mirroring the SOI wafer having surface irregularities by performing HCl gas phase etching in a reactor having a normal-pressure remnant flow; 상기 표면 경면화된 SOI 웨이퍼를 수소 가스 분위기에서 급속 열처리하여 표면 결함을 감소시키는 단계와;Rapidly heat treating the surface mirrored SOI wafer in a hydrogen gas atmosphere to reduce surface defects; 상기 SOI 웨이퍼를 세정하는 단계를 포함하는 SOI 웨이퍼의 표면 정밀 가공 방법.And cleaning the SOI wafer. 제 1 항에 있어서, 상기 표면 요철을 갖는 SOI 웨이퍼를 HCl 기상 식각하여 평탄화 및 표면 경면화하는 단계 이전에,The method of claim 1, wherein before the planarization and surface mirroring of the SOI wafer having surface irregularities by HCl gas phase etching, 상기 표면 요철을 갖는 SOI 웨이퍼를 수소 가스 분위기에 급속 열처리하는 단계를 더 포함하는 SOI 웨이퍼의 표면 정밀 가공 방법.And rapidly heat-treating the SOI wafer having the surface irregularities in a hydrogen gas atmosphere. 제 1 항 또는 제 2 항에 있어서, 상기 HCl 기상 식각은,The method of claim 1 or 2, wherein the HCl gas phase etching, 상기 SOI 웨이퍼를 1050℃ 내지 1200℃로 유지하며 HCl 가스량을 1slm 내지 40slm로 하는 SOI 웨이퍼의 표면 정밀 가공 방법.The method for precise surface processing of an SOI wafer, wherein the SOI wafer is maintained at 1050 ° C to 1200 ° C and the amount of HCl gas is 1 slm to 40 slm. 삭제delete 삭제delete
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582448A (en) * 1991-09-20 1993-04-02 Nec Corp Formation of soi
US5759908A (en) * 1995-05-16 1998-06-02 University Of Cincinnati Method for forming SiC-SOI structures
KR19980079501A (en) * 1997-03-31 1998-11-25 기타오카 타카시 Silicon Wafer Manufacturing Method and Silicon Wafer
EP0917188A2 (en) * 1997-11-05 1999-05-19 Shin-Etsu Handotai Company Limited Method for heat treatment of SOI wafer and SOI wafer heat-treated by the method
KR20000011406A (en) * 1998-07-07 2000-02-25 와다 다다시 A method of fabricating an soi wafer and soi wafer fabricated by the method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0582448A (en) * 1991-09-20 1993-04-02 Nec Corp Formation of soi
US5759908A (en) * 1995-05-16 1998-06-02 University Of Cincinnati Method for forming SiC-SOI structures
KR19980079501A (en) * 1997-03-31 1998-11-25 기타오카 타카시 Silicon Wafer Manufacturing Method and Silicon Wafer
EP0917188A2 (en) * 1997-11-05 1999-05-19 Shin-Etsu Handotai Company Limited Method for heat treatment of SOI wafer and SOI wafer heat-treated by the method
KR20000011406A (en) * 1998-07-07 2000-02-25 와다 다다시 A method of fabricating an soi wafer and soi wafer fabricated by the method

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