JP2002334854A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize streamlining of manufacturing processes in terms of cost and time by omitting a mirror polishing process by a chemical-mechanical polishing(CMP) method for a product, such as transistor for horizontal-deflection output or the like, for which strict wafer characteristics are not required. SOLUTION: The wafer is ground half-off and is simultaneously subjected to a half-mirror polishing under the grinding condition, to keep the work-strain layer to be 0.2 μm or shallower. By initially forming a thermal oxide film in forming the device, silicon is consumed to eliminate the work-strain layer. By adopting this method for a wafer for which not so strict characteristics are required as a user's demand, wastage can be eliminated in time terms of and cost, to realize streamlining of the manufacturing processes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which realizes rationalization in mirror-finish processing of a wafer.

[0002]

2. Description of the Related Art The surface area of a silicon wafer on which an IC is manufactured is mirror-polished due to strict flatness requirements.

FIGS. 3 and 4 show a conventional method of manufacturing a wafer, taking an n-type silicon wafer as an example. 3 is a process chart, and FIG. 4 is a cross-sectional view of a wafer in each process.

[0004] First, the outer peripheral portion of a silicon single crystal ingot is ground and sliced into individual wafers. Thereafter, the side surface of the wafer is polished parabolically in a chamfering step. This is to minimize chipping of side surfaces and introduction of crystal defects due to distortion from the periphery due to heat treatment or the like when handling the wafer in the IC manufacturing process. After the chamfering, a lapping process 12 (FIG. 4A) for mechanically polishing the wafer 11 is performed using a polishing liquid containing a polishing agent having a fine particle diameter to smooth the surface.

Next, a high concentration layer 13 of phosphorus or the like is formed by diffusion, and collector regions are formed on the upper and lower surfaces of the wafer (FIG. 4B).

The silicon wafer is half-offed by grinding 14 to obtain a desired wafer thickness (FIG. 4).
(C)). The whetstone in this case is about # 2000. Since the grinding 14 is a rough cutting, the surface of the wafer becomes a work distortion layer 15 including a work defect and an incomplete crystal region.

Further, the wafer is placed on a turntable,
Chemical and mechanical polishing (CMP: Chemical Mechanica)
l Polishing) to remove the work distortion layer 15 by grinding. Thereafter, a device is formed on the mirror-finished surface 16 of the wafer through a known diffusion process or the like.

[0008]

SUMMARY OF THE INVENTION Silicon wafers are required to have various geometrical, crystalline and performance characteristics. For the shape surface, the caliber size, thickness, the degree of finish of the front / back and side surfaces are determined. In terms of quality, there are strict standards for flatness and warpage, as well as scratch and dirt.

Since the grinding is a rough cutting, if a processing defect in this step or a processing strain layer which is an incomplete crystal region remains, a leakage current becomes large due to the processing defect after device formation, thereby deteriorating device characteristics. I will. Conventionally, a chemical-mechanical polishing process (CMP) has been indispensable in order to remove the processing strain layer and flatten the wafer surface.

Here, the CMP process will be described in detail below. First, the wafer is fixed to a ceramic plate with wax. A wafer is set on a polishing machine, and a table and a ceramic plate of the polishing machine on which a polishing cloth is stretched are simultaneously rotated to polish with a polishing liquid. After polishing, the wafer is peeled off from the ceramic plate, wax remaining on the back surface of the wafer is removed, and the wafer is washed.

In advanced ICs with advanced microfabrication, the wafer surface is naturally required to have strict flatness. Of course, wafers whose characteristics are not so severe are also required by the market.
Even in such a case, there is a problem that the mirror surface processing by CMP is performed as described above, and the manufacturing process cannot be rationalized.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and comprises a step of forming a high-concentration layer on a lap-processed wafer, then half-off by grinding, and simultaneously performing a half-mirror processing under grinding conditions. Forming a desired thermal oxide film in a first thermal oxidation step when forming a device on the wafer, and removing a processing strain layer of the wafer. By grinding the strained layer so as to be as small as possible in the prior art, the processed strained layer is removed by a thermal oxide film in a thermal oxidation step at the time of device formation. For products that do not require severe wafer characteristics, such as horizontal deflection output transistors, use this method for chemical and mechanical polishing (CMP).
By omitting the mirror finishing step, the cost and time rationalization of the manufacturing process can be realized.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, an embodiment of the present invention will be described in detail by taking an n-type silicon wafer as an example. In FIG.
FIG. 2 is a process diagram of the manufacturing method of the present invention, and FIG. 2 is a sectional view of a wafer in each process of FIG.

As shown in FIG. 1, the method of manufacturing a semiconductor device according to the present invention comprises, as shown in FIG. 1, a step of forming a high-concentration layer on a lap-processed wafer, half-off by grinding, and half-mirror processing at the same time under grinding conditions. Forming a desired thermal oxide film in an initial thermal oxidation step when a device is formed on the wafer, and removing a work distortion layer of the wafer.

First, the outer periphery of a silicon single crystal ingot is ground and sliced into individual wafers. Thereafter, the side surface of the wafer is polished parabolically in a chamfering step. This is to minimize chipping of side surfaces and introduction of crystal defects due to distortion from the periphery due to heat treatment or the like when handling the wafer in the IC manufacturing process. After the chamfering, a lapping process 2 (FIG. 2 (A)) for mechanically polishing the wafer 1 using a polishing liquid containing an abrasive having a fine particle diameter is performed to smooth the surface.

Next, a high concentration layer 3 of phosphorus or the like is formed by diffusion, and collector regions are formed on the upper and lower surfaces of the wafer (FIG. 2).
(B)).

Here, the grinding which is the first feature of the present invention is performed. The silicon wafer 1 is half-off by grinding 4 to obtain a desired wafer thickness, and at the same time, a desired half mirror finishing 4 is performed (FIG. 2).
(C)). In this case, a grindstone of about # 2000 to # 4000 is used, and the surface roughness is set to 200 ° or less. Further, the depth of the work strain layer 5 is made as small as possible, specifically, 0.2 μm.
grinding to less than m. Thus, the half mirror finishing 4 can be performed under the grinding condition simultaneously with the half-off of the wafer 1. What is important in this step is that the depth of the work strained layer 5 is set to 0.2 μm depending on desired grinding conditions.
m or less and half mirror surface processing 4 is performed.

Next, the second feature of the present invention, that is, thermal oxidation, is performed. By forming a desired thermal oxide film 6 in the first thermal oxidation step (diffusion step) when forming a device on the wafer, it is possible to remove processing defects and incomplete crystals on the wafer surface (FIG. 2
(D)). The processing strain layer 5 is shallower than the conventional one and has a thickness of 0.2 μm or less, and is flattened by the half mirror surface processing 4. For this reason, when a thermal oxide film 6 having a desired film thickness is generated in the first thermal oxidation step (diffusion step) at the time of device formation, generally, 45% of the silicon film of the thermal oxide film 6 is etched. As a result, processing defects and incomplete crystals can be removed.

More specifically, for example, in the case of a transistor for horizontal deflection output, a processing strain layer 5 containing a processing defect and an incomplete crystal is formed by a thermal oxide film 6 of about 10,000 to 20000 °.
Was found to be removable. However, the present invention is not limited to this, and can be applied to other devices as long as wafer characteristics that meet user requirements can be obtained.

The first thermal oxidation step at the time of device formation is a step to be carried out by any type. In other words, by making the work strained layer shallower than before by grinding in advance, and performing flattening by applying half mirror finishing, CM
Even if the step of P is omitted, the work distortion layer can be removed.

As described above, the wafer has various shapes and shapes.
Crystalline and performance characteristics are required. In advanced ICs with advanced microfabrication, the wafer surface is naturally required to have strict flatness, but there is naturally a market demand for wafers with less severe characteristics. If such mirror processing (CMP) is performed on such a wafer, the manufacturing process cannot be rationalized. In other words, for a product such as a transistor for horizontal deflection output, which does not have such severe characteristics as flatness of a wafer, half mirror-off is performed at the same time as half-off of grind grinding, and a half-mirror surface process is performed under the grinding condition to form a processed strain layer of 0.1 mm. If the thickness is less than 2 μm, the work-strained layer can be removed by thermal oxidation during device formation. As a result, time and cost loss due to CMP can be reduced, and the manufacturing process can be rationalized.

[0022]

According to the present invention, the wafer is subjected to half mirror finishing under the grinding condition simultaneously with the half-off of the wafer under the desired grinding condition to form a processed strained layer of 0.2 μm or less. As a result, the silicon surface is shaved by the first step of forming a thermal oxide film for device formation, which is a later step, and the work-strained layer can be removed. For example, by adopting the method of the present invention for a product whose characteristics such as wafer flattening are not so severe at the request of the user, such as a transistor for horizontal deflection output, etc.
Conventional chemical and mechanical polishing (CMP)
Can be omitted. In other words,
This enables cost reduction and contributes to rationalization of the manufacturing process.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is an explanatory diagram of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is an explanatory diagram of a conventional method for manufacturing a semiconductor device.

FIG. 4 is an explanatory view of a conventional method for manufacturing a semiconductor device.

Claims (3)

[Claims] 1. A step of forming a high-concentration layer on a lap-processed wafer, half-off by grinding, and simultaneously half-mirror processing under grinding conditions, and a first thermal oxidation step for forming a device on the wafer Forming a desired thermal oxide film and removing a work-strained layer of the wafer. 2. The surface roughness of the grinding is 200 °.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: 3. The wafer according to claim 1, wherein the depth of the work-strained layer is 0.5 mm.
The method according to claim 1, wherein the thickness is 2 μm or less.